From 6bfa5a0dcec6a9bd42cea94ba11eeae1a17a7f2c Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Wed, 11 Oct 2023 03:41:10 +0200
Subject: [PATCH] rtc/bd fixes.

---
 data/registers/pwr_u5.yaml  | 16 +++-------------
 data/registers/pwr_wba.yaml |  6 +++---
 stm32-data-gen/src/chips.rs |  1 +
 3 files changed, 7 insertions(+), 16 deletions(-)

diff --git a/data/registers/pwr_u5.yaml b/data/registers/pwr_u5.yaml
index 334724f..047a2a4 100644
--- a/data/registers/pwr_u5.yaml
+++ b/data/registers/pwr_u5.yaml
@@ -41,10 +41,10 @@ block/PWR:
     description: Backup domain control register 2
     byte_offset: 36
     fieldset: BDCR2
-  - name: DBPR
+  - name: DBPCR
     description: disable Backup domain register
     byte_offset: 40
-    fieldset: DBPR
+    fieldset: DBPCR
   - name: UCPDR
     description: USB Type-C™ and Power Delivery register
     byte_offset: 44
@@ -309,14 +309,13 @@ fieldset/CR3:
     description: Fast soft start
     bit_offset: 2
     bit_size: 1
-fieldset/DBPR:
+fieldset/DBPCR:
   description: disable Backup domain register
   fields:
   - name: DBP
     description: "Disable Backup domain write protection\r In reset state, all registers and SRAM in Backup domain are protected against parasitic write access. This bit must be set to enable the write access to these registers."
     bit_offset: 0
     bit_size: 1
-    enum: DBP
 fieldset/PCR:
   description: Power Port pull control register
   fields:
@@ -643,15 +642,6 @@ enum/ACTVOS:
   - name: Range1
     description: Range 1 (highest frequency)
     value: 3
-enum/DBP:
-  bit_size: 1
-  variants:
-  - name: Disabled
-    description: Write access to Backup domain disabled
-    value: 0
-  - name: Enabled
-    description: Write access to Backup domain enabled
-    value: 1
 enum/FLASHFWU:
   bit_size: 1
   variants:
diff --git a/data/registers/pwr_wba.yaml b/data/registers/pwr_wba.yaml
index b1d12af..5ce7382 100644
--- a/data/registers/pwr_wba.yaml
+++ b/data/registers/pwr_wba.yaml
@@ -33,10 +33,10 @@ block/PWR:
     description: wakeup control register 3
     byte_offset: 28
     fieldset: WUCR3
-  - name: DBPR
+  - name: DBPCR
     description: disable Backup domain register
     byte_offset: 40
-    fieldset: DBPR
+    fieldset: DBPCR
   - name: SECCFGR
     description: security configuration register
     byte_offset: 48
@@ -136,7 +136,7 @@ fieldset/CR3:
     description: Fast soft start
     bit_offset: 2
     bit_size: 1
-fieldset/DBPR:
+fieldset/DBPCR:
   description: disable Backup domain register
   fields:
   - name: DBP
diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs
index 2704a1f..7d09ea5 100644
--- a/stm32-data-gen/src/chips.rs
+++ b/stm32-data-gen/src/chips.rs
@@ -254,6 +254,7 @@ impl PeriMatcher {
             ("STM32L4.*:RTC:rtc2_.*", ("rtc", "v2l4", "RTC")),
             ("STM32WBA.*:RTC:rtc2_.*", ("rtc", "v3u5", "RTC")),
             ("STM32WB.*:RTC:rtc2_.*", ("rtc", "v2wb", "RTC")),
+            ("STM32H5.*:RTC:rtc2_.*", ("rtc", "v3u5", "RTC")),
             ("STM32U5.*:RTC:rtc2_.*", ("rtc", "v3u5", "RTC")), // Cube says v2, but it's v3 with security stuff
             (".*:RTC:rtc3_v1_0", ("rtc", "v3", "RTC")),
             (".*:RTC:rtc3_v1_1", ("rtc", "v3", "RTC")),