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Add RCC for F3, F7, G4, H7AB, L1, L5, WB*, WL5, WLE

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This commit is contained in:
Dario Nieuwenhuis 2021-08-19 19:13:30 +02:00
parent bd402a58f2
commit 6af9f2c0d1
9 changed files with 9348 additions and 8 deletions
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1082
data/registers/rcc_f3.yaml Normal file
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data/registers/rcc_f7.yaml Normal file
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data/registers/rcc_g4.yaml Normal file
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data/registers/rcc_l1.yaml Normal file
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data/registers/rcc_l5.yaml Normal file
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data/registers/rcc_wb55.yaml → data/registers/rcc_wb.yaml
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data/registers/rcc_wl5x.yaml → data/registers/rcc_wl5.yaml
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data/registers/rcc_wle.yaml Normal file
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parse.py
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@ -352,18 +352,26 @@ perimap = [
('STM32G0.*:SYS:.*', 'syscfg_g0/SYSCFG'),
('STM32WB55.*:SYS:.*', 'syscfg_wb55/SYSCFG'),
('STM32WL.*:SYS:.*', 'syscfg_wl5x/SYSCFG'),
('STM32L0.*:RCC:.*', 'rcc_l0/RCC'),
('STM32L4.*:RCC:.*', 'rcc_l4/RCC'),
('STM32F410.*:RCC:.*', 'rcc_f410/RCC'),
('STM32F4.*:RCC:.*', 'rcc_f4/RCC'),
('STM32WL.*:RCC:.*', 'rcc_wl5x/RCC'),
('STM32F0.0.*:RCC:.*', 'rcc_f0x0/RCC'),
('STM32F0.*:RCC:.*', 'rcc_f0/RCC'),
('STM32F1.*:RCC:.*', 'rcc_f1/RCC'),
('STM32F3.*:RCC:.*', 'rcc_f3/RCC'),
('STM32F410.*:RCC:.*', 'rcc_f410/RCC'),
('STM32F4.*:RCC:.*', 'rcc_f4/RCC'),
('STM32F7.*:RCC:.*', 'rcc_f7/RCC'),
('STM32G0.*:RCC:.*', 'rcc_g0/RCC'),
('.*:STM32H7AB_rcc_v1_0', ''), # rcc_h7ab/RCC
('.*:STM32H7_rcc_v1_0', 'rcc_h7/RCC'),
('.*:STM32W_rcc_v1_0', 'rcc_wb55/RCC'),
('STM32G4.*:RCC:.*', 'rcc_g4/RCC'),
('STM32H7[AB].*:RCC:.*', 'rcc_h7ab/RCC'),
('STM32H7.*:RCC:.*', 'rcc_h7/RCC'),
('STM32L0.*:RCC:.*', 'rcc_l0/RCC'),
('STM32L1.*:RCC:.*', 'rcc_l1/RCC'),
('STM32L4.*:RCC:.*', 'rcc_l4/RCC'),
('STM32L5.*:RCC:.*', 'rcc_l5/RCC'),
('STM32WB.*:RCC:.*', 'rcc_wb/RCC'),
('STM32WL5.*:RCC:.*', 'rcc_wl5/RCC'),
('STM32WLE.*:RCC:.*', 'rcc_wle/RCC'),
('.*:STM32L0_crs_v1_0', 'crs_l0/CRS'),
('.*SDMMC:sdmmc2_v1_0', 'sdmmc_v2/SDMMC'),
('STM32H7(42|43|53|50).*:STM32H7_pwr_v1_0', 'pwr_h7/PWR'),