diff --git a/data/registers/rcc_f3.yaml b/data/registers/rcc_f3.yaml new file mode 100644 index 0000000..55db1f4 --- /dev/null +++ b/data/registers/rcc_f3.yaml @@ -0,0 +1,1082 @@ +--- +block/RCC: + description: Reset and clock control + items: + - name: CR + description: Clock control register + byte_offset: 0 + fieldset: CR + - name: CFGR + description: Clock configuration register (RCC_CFGR) + byte_offset: 4 + fieldset: CFGR + - name: CIR + description: Clock interrupt register (RCC_CIR) + byte_offset: 8 + fieldset: CIR + - name: APB2RSTR + description: APB2 peripheral reset register (RCC_APB2RSTR) + byte_offset: 12 + fieldset: APB2RSTR + - name: APB1RSTR + description: APB1 peripheral reset register (RCC_APB1RSTR) + byte_offset: 16 + fieldset: APB1RSTR + - name: AHBENR + description: AHB Peripheral Clock enable register (RCC_AHBENR) + byte_offset: 20 + fieldset: AHBENR + - name: APB2ENR + description: APB2 peripheral clock enable register (RCC_APB2ENR) + byte_offset: 24 + fieldset: APB2ENR + - name: APB1ENR + description: APB1 peripheral clock enable register (RCC_APB1ENR) + byte_offset: 28 + fieldset: APB1ENR + - name: BDCR + description: Backup domain control register (RCC_BDCR) + byte_offset: 32 + fieldset: BDCR + - name: CSR + description: Control/status register (RCC_CSR) + byte_offset: 36 + fieldset: CSR + - name: AHBRSTR + description: AHB peripheral reset register + byte_offset: 40 + fieldset: AHBRSTR + - name: CFGR2 + description: Clock configuration register 2 + byte_offset: 44 + fieldset: CFGR2 + - name: CFGR3 + description: Clock configuration register 3 + byte_offset: 48 + fieldset: CFGR3 +fieldset/AHBENR: + description: AHB Peripheral Clock enable register (RCC_AHBENR) + fields: + - name: DMA1EN + description: DMA1 clock enable + bit_offset: 0 + bit_size: 1 + - name: SRAMEN + description: SRAM interface clock enable + bit_offset: 2 + bit_size: 1 + - name: FLITFEN + description: FLITF clock enable + bit_offset: 4 + bit_size: 1 + - name: CRCEN + description: CRC clock enable + bit_offset: 6 + bit_size: 1 + - name: IOPAEN + description: I/O port A clock enable + bit_offset: 17 + bit_size: 1 + - name: IOPBEN + description: I/O port B clock enable + bit_offset: 18 + bit_size: 1 + - name: IOPCEN + description: I/O port C clock enable + bit_offset: 19 + bit_size: 1 + - name: IOPDEN + description: I/O port D clock enable + bit_offset: 20 + bit_size: 1 + - name: IOPFEN + description: I/O port F clock enable + bit_offset: 22 + bit_size: 1 + - name: TSCEN + description: Touch sensing controller clock enable + bit_offset: 24 + bit_size: 1 + - name: ADC12EN + description: ADC1 and ADC2 clock enable + bit_offset: 28 + bit_size: 1 + - name: ADC34EN + description: ADC3 and ADC4 clock enable + bit_offset: 29 + bit_size: 1 +fieldset/AHBRSTR: + description: AHB peripheral reset register + fields: + - name: IOPARST + description: I/O port A reset + bit_offset: 17 + bit_size: 1 + - name: IOPBRST + description: I/O port B reset + bit_offset: 18 + bit_size: 1 + - name: IOPCRST + description: I/O port C reset + bit_offset: 19 + bit_size: 1 + - name: IOPDRST + description: I/O port D reset + bit_offset: 20 + bit_size: 1 + - name: IOPFRST + description: I/O port F reset + bit_offset: 22 + bit_size: 1 + - name: TSCRST + description: Touch sensing controller reset + bit_offset: 24 + bit_size: 1 + - name: ADC12RST + description: ADC1 and ADC2 reset + bit_offset: 28 + bit_size: 1 +fieldset/APB1ENR: + description: APB1 peripheral clock enable register (RCC_APB1ENR) + fields: + - name: TIM2EN + description: Timer 2 clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: Timer 3 clock enable + bit_offset: 1 + bit_size: 1 + - name: TIM6EN + description: Timer 6 clock enable + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: Timer 7 clock enable + bit_offset: 5 + bit_size: 1 + - name: WWDGEN + description: Window watchdog clock enable + bit_offset: 11 + bit_size: 1 + - name: USART2EN + description: USART 2 clock enable + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: USART3 clock enable + bit_offset: 18 + bit_size: 1 + - name: I2C1EN + description: I2C 1 clock enable + bit_offset: 21 + bit_size: 1 + - name: CANEN + description: CAN clock enable + bit_offset: 25 + bit_size: 1 + - name: DAC2EN + description: DAC2 interface clock enable + bit_offset: 26 + bit_size: 1 + - name: PWREN + description: Power interface clock enable + bit_offset: 28 + bit_size: 1 + - name: DAC1EN + description: DAC interface clock enable + bit_offset: 29 + bit_size: 1 +fieldset/APB1RSTR: + description: APB1 peripheral reset register (RCC_APB1RSTR) + fields: + - name: TIM2RST + description: Timer 2 reset + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: Timer 3 reset + bit_offset: 1 + bit_size: 1 + - name: TIM6RST + description: Timer 6 reset + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: Timer 7 reset + bit_offset: 5 + bit_size: 1 + - name: WWDGRST + description: Window watchdog reset + bit_offset: 11 + bit_size: 1 + - name: USART2RST + description: USART 2 reset + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: USART3 reset + bit_offset: 18 + bit_size: 1 + - name: I2C1RST + description: I2C1 reset + bit_offset: 21 + bit_size: 1 + - name: CANRST + description: CAN reset + bit_offset: 25 + bit_size: 1 + - name: DAC2RST + description: DAC2 interface reset + bit_offset: 26 + bit_size: 1 + - name: PWRRST + description: Power interface reset + bit_offset: 28 + bit_size: 1 + - name: DAC1RST + description: DAC interface reset + bit_offset: 29 + bit_size: 1 +fieldset/APB2ENR: + description: APB2 peripheral clock enable register (RCC_APB2ENR) + fields: + - name: SYSCFGEN + description: SYSCFG clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM1EN + description: TIM1 Timer clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: SPI 1 clock enable + bit_offset: 12 + bit_size: 1 + - name: USART1EN + description: USART1 clock enable + bit_offset: 14 + bit_size: 1 + - name: TIM15EN + description: TIM15 timer clock enable + bit_offset: 16 + bit_size: 1 + - name: TIM16EN + description: TIM16 timer clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: TIM17 timer clock enable + bit_offset: 18 + bit_size: 1 + - name: HRTIM1EN + description: High Resolution Timer 1 clock enable + bit_offset: 29 + bit_size: 1 +fieldset/APB2RSTR: + description: APB2 peripheral reset register (RCC_APB2RSTR) + fields: + - name: SYSCFGRST + description: SYSCFG and COMP reset + bit_offset: 0 + bit_size: 1 + - name: TIM1RST + description: TIM1 timer reset + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: SPI 1 reset + bit_offset: 12 + bit_size: 1 + - name: USART1RST + description: USART1 reset + bit_offset: 14 + bit_size: 1 + - name: TIM15RST + description: TIM15 timer reset + bit_offset: 16 + bit_size: 1 + - name: TIM16RST + description: TIM16 timer reset + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: TIM17 timer reset + bit_offset: 18 + bit_size: 1 + - name: HRTIM1RST + description: High Resolution Timer1 reset + bit_offset: 29 + bit_size: 1 +fieldset/BDCR: + description: Backup domain control register (RCC_BDCR) + fields: + - name: LSEON + description: External Low Speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: External Low Speed oscillator ready + bit_offset: 1 + bit_size: 1 + enum_read: LSERDYR + - name: LSEBYP + description: External Low Speed oscillator bypass + bit_offset: 2 + bit_size: 1 + enum: LSEBYP + - name: LSEDRV + description: LSE oscillator drive capability + bit_offset: 3 + bit_size: 2 + enum: LSEDRV + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: Backup domain software reset + bit_offset: 16 + bit_size: 1 +fieldset/CFGR: + description: Clock configuration register (RCC_CFGR) + fields: + - name: SW + description: System clock Switch + bit_offset: 0 + bit_size: 2 + enum: SW + - name: SWS + description: System Clock Switch Status + bit_offset: 2 + bit_size: 2 + enum_read: SWSR + - name: HPRE + description: AHB prescaler + bit_offset: 4 + bit_size: 4 + enum: HPRE + - name: PPRE1 + description: APB Low speed prescaler (APB1) + bit_offset: 8 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: APB high speed prescaler (APB2) + bit_offset: 11 + bit_size: 3 + enum: PPRE + - name: PLLSRC + description: PLL entry clock source + bit_offset: 16 + bit_size: 1 + enum: PLLSRC + - name: PLLXTPRE + description: HSE divider for PLL entry + bit_offset: 17 + bit_size: 1 + enum: PLLXTPRE + - name: PLLMUL + description: PLL Multiplication Factor + bit_offset: 18 + bit_size: 4 + enum: PLLMUL + - name: MCO + description: Microcontroller clock output + bit_offset: 24 + bit_size: 3 + enum: MCO + - name: MCOPRE + description: Microcontroller Clock Output Prescaler + bit_offset: 28 + bit_size: 3 + enum: MCOPRE + - name: PLLNODIV + description: Do not divide PLL to MCO + bit_offset: 31 + bit_size: 1 + enum: PLLNODIV +fieldset/CFGR2: + description: Clock configuration register 2 + fields: + - name: PREDIV + description: PREDIV division factor + bit_offset: 0 + bit_size: 4 + enum: PREDIV + - name: ADC12PRES + description: ADC1 and ADC2 prescaler + bit_offset: 4 + bit_size: 5 + enum: ADCPRES +fieldset/CFGR3: + description: Clock configuration register 3 + fields: + - name: USART1SW + description: USART1 clock source selection + bit_offset: 0 + bit_size: 2 + enum: USARTSW + - name: I2C1SW + description: I2C1 clock source selection + bit_offset: 4 + bit_size: 1 + enum: ICSW + - name: TIM1SW + description: Timer1 clock source selection + bit_offset: 8 + bit_size: 1 + enum: TIMSW +fieldset/CIR: + description: Clock interrupt register (RCC_CIR) + fields: + - name: LSIRDYF + description: LSI Ready Interrupt flag + bit_offset: 0 + bit_size: 1 + enum_read: LSIRDYFR + - name: LSERDYF + description: LSE Ready Interrupt flag + bit_offset: 1 + bit_size: 1 + enum_read: LSIRDYFR + - name: HSIRDYF + description: HSI Ready Interrupt flag + bit_offset: 2 + bit_size: 1 + enum_read: LSIRDYFR + - name: HSERDYF + description: HSE Ready Interrupt flag + bit_offset: 3 + bit_size: 1 + enum_read: LSIRDYFR + - name: PLLRDYF + description: PLL Ready Interrupt flag + bit_offset: 4 + bit_size: 1 + enum_read: LSIRDYFR + - name: CSSF + description: Clock Security System Interrupt flag + bit_offset: 7 + bit_size: 1 + enum_read: CSSFR + - name: LSIRDYIE + description: LSI Ready Interrupt Enable + bit_offset: 8 + bit_size: 1 + enum: LSIRDYIE + - name: LSERDYIE + description: LSE Ready Interrupt Enable + bit_offset: 9 + bit_size: 1 + enum: LSIRDYIE + - name: HSIRDYIE + description: HSI Ready Interrupt Enable + bit_offset: 10 + bit_size: 1 + enum: LSIRDYIE + - name: HSERDYIE + description: HSE Ready Interrupt Enable + bit_offset: 11 + bit_size: 1 + enum: LSIRDYIE + - name: PLLRDYIE + description: PLL Ready Interrupt Enable + bit_offset: 12 + bit_size: 1 + enum: LSIRDYIE + - name: LSIRDYC + description: LSI Ready Interrupt Clear + bit_offset: 16 + bit_size: 1 + enum_write: LSIRDYCW + - name: LSERDYC + description: LSE Ready Interrupt Clear + bit_offset: 17 + bit_size: 1 + enum_write: LSIRDYCW + - name: HSIRDYC + description: HSI Ready Interrupt Clear + bit_offset: 18 + bit_size: 1 + enum_write: LSIRDYCW + - name: HSERDYC + description: HSE Ready Interrupt Clear + bit_offset: 19 + bit_size: 1 + enum_write: LSIRDYCW + - name: PLLRDYC + description: PLL Ready Interrupt Clear + bit_offset: 20 + bit_size: 1 + enum_write: LSIRDYCW + - name: CSSC + description: Clock security system interrupt clear + bit_offset: 23 + bit_size: 1 + enum_write: CSSCW +fieldset/CR: + description: Clock control register + fields: + - name: HSION + description: Internal High Speed clock enable + bit_offset: 0 + bit_size: 1 + - name: HSIRDY + description: Internal High Speed clock ready flag + bit_offset: 1 + bit_size: 1 + enum_read: HSIRDYR + - name: HSITRIM + description: Internal High Speed clock trimming + bit_offset: 3 + bit_size: 5 + - name: HSICAL + description: Internal High Speed clock Calibration + bit_offset: 8 + bit_size: 8 + - name: HSEON + description: External High Speed clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: External High Speed clock ready flag + bit_offset: 17 + bit_size: 1 + enum_read: HSIRDYR + - name: HSEBYP + description: External High Speed clock Bypass + bit_offset: 18 + bit_size: 1 + enum: HSEBYP + - name: CSSON + description: Clock Security System enable + bit_offset: 19 + bit_size: 1 + - name: PLLON + description: PLL enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: PLL clock ready flag + bit_offset: 25 + bit_size: 1 + enum_read: HSIRDYR +fieldset/CSR: + description: Control/status register (RCC_CSR) + fields: + - name: LSION + description: Internal low speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: Internal low speed oscillator ready + bit_offset: 1 + bit_size: 1 + enum_read: LSIRDYR + - name: V18PWRRSTF + description: Reset flag of the 1.8 V domain + bit_offset: 23 + bit_size: 1 + enum_read: OBLRSTFR + - name: RMVF + description: Remove reset flag + bit_offset: 24 + bit_size: 1 + enum_write: RMVFW + - name: OBLRSTF + description: Option byte loader reset flag + bit_offset: 25 + bit_size: 1 + enum_read: OBLRSTFR + - name: PINRSTF + description: PIN reset flag + bit_offset: 26 + bit_size: 1 + enum_read: OBLRSTFR + - name: PORRSTF + description: POR/PDR reset flag + bit_offset: 27 + bit_size: 1 + enum_read: OBLRSTFR + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + enum_read: OBLRSTFR + - name: IWDGRSTF + description: Independent watchdog reset flag + bit_offset: 29 + bit_size: 1 + enum_read: OBLRSTFR + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + enum_read: OBLRSTFR + - name: LPWRRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 + enum_read: OBLRSTFR +enum/ADCPRES: + bit_size: 5 + variants: + - name: NoClock + description: No clock + value: 0 + - name: Div1 + description: PLL clock not divided + value: 16 + - name: Div2 + description: PLL clock divided by 2 + value: 17 + - name: Div4 + description: PLL clock divided by 4 + value: 18 + - name: Div6 + description: PLL clock divided by 6 + value: 19 + - name: Div8 + description: PLL clock divided by 8 + value: 20 + - name: Div10 + description: PLL clock divided by 10 + value: 21 + - name: Div12 + description: PLL clock divided by 12 + value: 22 + - name: Div16 + description: PLL clock divided by 16 + value: 23 + - name: Div32 + description: PLL clock divided by 32 + value: 24 + - name: Div64 + description: PLL clock divided by 64 + value: 25 + - name: Div128 + description: PLL clock divided by 128 + value: 26 + - name: Div256 + description: PLL clock divided by 256 + value: 27 +enum/CSSCW: + bit_size: 1 + variants: + - name: Clear + description: Clear CSSF flag + value: 1 +enum/CSSFR: + bit_size: 1 + variants: + - name: NotInterrupted + description: No clock security interrupt caused by HSE clock failure + value: 0 + - name: Interrupted + description: Clock security interrupt caused by HSE clock failure + value: 1 +enum/HPRE: + bit_size: 4 + variants: + - name: Div1 + description: SYSCLK not divided + value: 0 + - name: Div2 + description: SYSCLK divided by 2 + value: 8 + - name: Div4 + description: SYSCLK divided by 4 + value: 9 + - name: Div8 + description: SYSCLK divided by 8 + value: 10 + - name: Div16 + description: SYSCLK divided by 16 + value: 11 + - name: Div64 + description: SYSCLK divided by 64 + value: 12 + - name: Div128 + description: SYSCLK divided by 128 + value: 13 + - name: Div256 + description: SYSCLK divided by 256 + value: 14 + - name: Div512 + description: SYSCLK divided by 512 + value: 15 +enum/HSEBYP: + bit_size: 1 + variants: + - name: NotBypassed + description: HSE crystal oscillator not bypassed + value: 0 + - name: Bypassed + description: HSE crystal oscillator bypassed with external clock + value: 1 +enum/HSIRDYR: + bit_size: 1 + variants: + - name: NotReady + description: Clock not ready + value: 0 + - name: Ready + description: Clock ready + value: 1 +enum/ICSW: + bit_size: 1 + variants: + - name: HSI + description: HSI clock selected as I2C clock source + value: 0 + - name: SYSCLK + description: SYSCLK clock selected as I2C clock source + value: 1 +enum/LSEBYP: + bit_size: 1 + variants: + - name: NotBypassed + description: LSE crystal oscillator not bypassed + value: 0 + - name: Bypassed + description: LSE crystal oscillator bypassed with external clock + value: 1 +enum/LSEDRV: + bit_size: 2 + variants: + - name: Low + description: Low drive capacity + value: 0 + - name: MediumHigh + description: Medium-high drive capacity + value: 1 + - name: MediumLow + description: Medium-low drive capacity + value: 2 + - name: High + description: High drive capacity + value: 3 +enum/LSERDYR: + bit_size: 1 + variants: + - name: NotReady + description: LSE oscillator not ready + value: 0 + - name: Ready + description: LSE oscillator ready + value: 1 +enum/LSIRDYCW: + bit_size: 1 + variants: + - name: Clear + description: Clear interrupt flag + value: 1 +enum/LSIRDYFR: + bit_size: 1 + variants: + - name: NotInterrupted + description: No clock ready interrupt + value: 0 + - name: Interrupted + description: Clock ready interrupt + value: 1 +enum/LSIRDYIE: + bit_size: 1 + variants: + - name: Disabled + description: Interrupt disabled + value: 0 + - name: Enabled + description: Interrupt enabled + value: 1 +enum/LSIRDYR: + bit_size: 1 + variants: + - name: NotReady + description: LSI oscillator not ready + value: 0 + - name: Ready + description: LSI oscillator ready + value: 1 +enum/MCO: + bit_size: 3 + variants: + - name: NoMCO + description: "MCO output disabled, no clock on MCO" + value: 0 + - name: LSI + description: Internal low speed (LSI) oscillator clock selected + value: 2 + - name: LSE + description: External low speed (LSE) oscillator clock selected + value: 3 + - name: SYSCLK + description: System clock selected + value: 4 + - name: HSI + description: Internal RC 8 MHz (HSI) oscillator clock selected + value: 5 + - name: HSE + description: External 4-32 MHz (HSE) oscillator clock selected + value: 6 + - name: PLL + description: "PLL clock selected (divided by 1 or 2, depending en PLLNODIV)" + value: 7 +enum/MCOPRE: + bit_size: 3 + variants: + - name: Div1 + description: MCO is divided by 1 + value: 0 + - name: Div2 + description: MCO is divided by 2 + value: 1 + - name: Div4 + description: MCO is divided by 4 + value: 2 + - name: Div8 + description: MCO is divided by 8 + value: 3 + - name: Div16 + description: MCO is divided by 16 + value: 4 + - name: Div32 + description: MCO is divided by 32 + value: 5 + - name: Div64 + description: MCO is divided by 64 + value: 6 + - name: Div128 + description: MCO is divided by 128 + value: 7 +enum/OBLRSTFR: + bit_size: 1 + variants: + - name: NoReset + description: No reset has occured + value: 0 + - name: Reset + description: A reset has occured + value: 1 +enum/PLLMUL: + bit_size: 4 + variants: + - name: Mul2 + description: PLL input clock x2 + value: 0 + - name: Mul3 + description: PLL input clock x3 + value: 1 + - name: Mul4 + description: PLL input clock x4 + value: 2 + - name: Mul5 + description: PLL input clock x5 + value: 3 + - name: Mul6 + description: PLL input clock x6 + value: 4 + - name: Mul7 + description: PLL input clock x7 + value: 5 + - name: Mul8 + description: PLL input clock x8 + value: 6 + - name: Mul9 + description: PLL input clock x9 + value: 7 + - name: Mul10 + description: PLL input clock x10 + value: 8 + - name: Mul11 + description: PLL input clock x11 + value: 9 + - name: Mul12 + description: PLL input clock x12 + value: 10 + - name: Mul13 + description: PLL input clock x13 + value: 11 + - name: Mul14 + description: PLL input clock x14 + value: 12 + - name: Mul15 + description: PLL input clock x15 + value: 13 + - name: Mul16 + description: PLL input clock x16 + value: 14 + - name: Mul16x + description: PLL input clock x16 + value: 15 +enum/PLLNODIV: + bit_size: 1 + variants: + - name: Div2 + description: PLL is divided by 2 for MCO + value: 0 + - name: Div1 + description: PLL is not divided for MCO + value: 1 +enum/PLLSRC: + bit_size: 1 + variants: + - name: HSI_Div2 + description: HSI divided by 2 selected as PLL input clock + value: 0 + - name: HSE_Div_PREDIV + description: HSE divided by PREDIV selected as PLL input clock + value: 1 +enum/PLLXTPRE: + bit_size: 1 + variants: + - name: Div1 + description: HSE clock not divided + value: 0 + - name: Div2 + description: HSE clock divided by 2 + value: 1 +enum/PPRE: + bit_size: 3 + variants: + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 +enum/PREDIV: + bit_size: 4 + variants: + - name: Div1 + description: PREDIV input clock not divided + value: 0 + - name: Div2 + description: PREDIV input clock divided by 2 + value: 1 + - name: Div3 + description: PREDIV input clock divided by 3 + value: 2 + - name: Div4 + description: PREDIV input clock divided by 4 + value: 3 + - name: Div5 + description: PREDIV input clock divided by 5 + value: 4 + - name: Div6 + description: PREDIV input clock divided by 6 + value: 5 + - name: Div7 + description: PREDIV input clock divided by 7 + value: 6 + - name: Div8 + description: PREDIV input clock divided by 8 + value: 7 + - name: Div9 + description: PREDIV input clock divided by 9 + value: 8 + - name: Div10 + description: PREDIV input clock divided by 10 + value: 9 + - name: Div11 + description: PREDIV input clock divided by 11 + value: 10 + - name: Div12 + description: PREDIV input clock divided by 12 + value: 11 + - name: Div13 + description: PREDIV input clock divided by 13 + value: 12 + - name: Div14 + description: PREDIV input clock divided by 14 + value: 13 + - name: Div15 + description: PREDIV input clock divided by 15 + value: 14 + - name: Div16 + description: PREDIV input clock divided by 16 + value: 15 +enum/RMVFW: + bit_size: 1 + variants: + - name: Clear + description: Clears the reset flag + value: 1 +enum/RTCSEL: + bit_size: 2 + variants: + - name: NoClock + description: No clock + value: 0 + - name: LSE + description: LSE oscillator clock used as RTC clock + value: 1 + - name: LSI + description: LSI oscillator clock used as RTC clock + value: 2 + - name: HSE + description: HSE oscillator clock divided by a prescaler used as RTC clock + value: 3 +enum/SW: + bit_size: 2 + variants: + - name: HSI + description: HSI selected as system clock + value: 0 + - name: HSE + description: HSE selected as system clock + value: 1 + - name: PLL + description: PLL selected as system clock + value: 2 +enum/SWSR: + bit_size: 2 + variants: + - name: HSI + description: HSI oscillator used as system clock + value: 0 + - name: HSE + description: HSE oscillator used as system clock + value: 1 + - name: PLL + description: PLL used as system clock + value: 2 +enum/TIMSW: + bit_size: 1 + variants: + - name: PCLK2 + description: PCLK2 clock (doubled frequency when prescaled) + value: 0 + - name: PLL + description: PLL vco output (running up to 144 MHz) + value: 1 +enum/USARTSW: + bit_size: 2 + variants: + - name: PCLK + description: PCLK selected as USART clock source + value: 0 + - name: SYSCLK + description: SYSCLK selected as USART clock source + value: 1 + - name: LSE + description: LSE selected as USART clock source + value: 2 + - name: HSI + description: HSI selected as USART clock source + value: 3 diff --git a/data/registers/rcc_f7.yaml b/data/registers/rcc_f7.yaml new file mode 100644 index 0000000..4639c96 --- /dev/null +++ b/data/registers/rcc_f7.yaml @@ -0,0 +1,2350 @@ +block/RCC: + description: Reset and clock control + items: + - byte_offset: 0 + description: clock control register + fieldset: CR + name: CR + - byte_offset: 4 + description: PLL configuration register + fieldset: PLLCFGR + name: PLLCFGR + - byte_offset: 8 + description: clock configuration register + fieldset: CFGR + name: CFGR + - byte_offset: 12 + description: clock interrupt register + fieldset: CIR + name: CIR + - byte_offset: 16 + description: AHB1 peripheral reset register + fieldset: AHB1RSTR + name: AHB1RSTR + - byte_offset: 20 + description: AHB2 peripheral reset register + fieldset: AHB2RSTR + name: AHB2RSTR + - byte_offset: 24 + description: AHB3 peripheral reset register + fieldset: AHB3RSTR + name: AHB3RSTR + - byte_offset: 32 + description: APB1 peripheral reset register + fieldset: APB1RSTR + name: APB1RSTR + - byte_offset: 36 + description: APB2 peripheral reset register + fieldset: APB2RSTR + name: APB2RSTR + - byte_offset: 48 + description: AHB1 peripheral clock register + fieldset: AHB1ENR + name: AHB1ENR + - byte_offset: 52 + description: AHB2 peripheral clock enable register + fieldset: AHB2ENR + name: AHB2ENR + - byte_offset: 56 + description: AHB3 peripheral clock enable register + fieldset: AHB3ENR + name: AHB3ENR + - byte_offset: 64 + description: APB1 peripheral clock enable register + fieldset: APB1ENR + name: APB1ENR + - byte_offset: 68 + description: APB2 peripheral clock enable register + fieldset: APB2ENR + name: APB2ENR + - byte_offset: 80 + description: AHB1 peripheral clock enable in low power mode register + fieldset: AHB1LPENR + name: AHB1LPENR + - byte_offset: 84 + description: AHB2 peripheral clock enable in low power mode register + fieldset: AHB2LPENR + name: AHB2LPENR + - byte_offset: 88 + description: AHB3 peripheral clock enable in low power mode register + fieldset: AHB3LPENR + name: AHB3LPENR + - byte_offset: 96 + description: APB1 peripheral clock enable in low power mode register + fieldset: APB1LPENR + name: APB1LPENR + - byte_offset: 100 + description: APB2 peripheral clock enabled in low power mode register + fieldset: APB2LPENR + name: APB2LPENR + - byte_offset: 112 + description: Backup domain control register + fieldset: BDCR + name: BDCR + - byte_offset: 116 + description: clock control & status register + fieldset: CSR + name: CSR + - byte_offset: 128 + description: spread spectrum clock generation register + fieldset: SSCGR + name: SSCGR + - byte_offset: 132 + description: PLLI2S configuration register + fieldset: PLLI2SCFGR + name: PLLI2SCFGR + - byte_offset: 136 + description: PLL configuration register + fieldset: PLLSAICFGR + name: PLLSAICFGR + - byte_offset: 140 + description: dedicated clocks configuration register + fieldset: DCKCFGR1 + name: DCKCFGR1 + - byte_offset: 144 + description: dedicated clocks configuration register + fieldset: DCKCFGR2 + name: DCKCFGR2 +enum/ADFSDMSEL: + bit_size: 1 + variants: + - description: SAI1 clock selected as DFSDM1 Audio clock source + name: SAI1 + value: 0 + - description: SAI2 clock selected as DFSDM1 Audio clock source + name: SAI2 + value: 1 +enum/CECSEL: + bit_size: 1 + variants: + - description: LSE clock is selected as HDMI-CEC clock + name: LSE + value: 0 + - description: HSI divided by 488 clock is selected as HDMI-CEC clock + name: HSI_Div488 + value: 1 +enum/CKMSEL: + bit_size: 1 + variants: + - description: 48MHz clock from PLL is selected + name: PLL + value: 0 + - description: 48MHz clock from PLLSAI is selected + name: PLLSAI + value: 1 +enum/CSSCW: + bit_size: 1 + variants: + - description: Clear CSSF flag + name: Clear + value: 1 +enum/CSSFR: + bit_size: 1 + variants: + - description: No clock security interrupt caused by HSE clock failure + name: NotInterrupted + value: 0 + - description: Clock security interrupt caused by HSE clock failure + name: Interrupted + value: 1 +enum/DFSDMSEL: + bit_size: 1 + variants: + - description: APB2 clock (PCLK2) selected as DFSDM1 Kernel clock source + name: APB2 + value: 0 + - description: System clock (SYSCLK) clock selected as DFSDM1 Kernel clock source + name: SYSCLK + value: 1 +enum/DSISEL: + bit_size: 1 + variants: + - description: DSI-PHY used as DSI byte lane clock source (usual case) + name: DSI_PHY + value: 0 + - description: PLLR used as DSI byte lane clock source, used in case DSI PLL and + DSI-PHY are off (low power mode) + name: PLLR + value: 1 +enum/HPRE: + bit_size: 4 + variants: + - description: SYSCLK not divided + name: Div1 + value: 0 + - description: SYSCLK divided by 2 + name: Div2 + value: 8 + - description: SYSCLK divided by 4 + name: Div4 + value: 9 + - description: SYSCLK divided by 8 + name: Div8 + value: 10 + - description: SYSCLK divided by 16 + name: Div16 + value: 11 + - description: SYSCLK divided by 64 + name: Div64 + value: 12 + - description: SYSCLK divided by 128 + name: Div128 + value: 13 + - description: SYSCLK divided by 256 + name: Div256 + value: 14 + - description: SYSCLK divided by 512 + name: Div512 + value: 15 +enum/HSEBYP: + bit_size: 1 + variants: + - description: HSE crystal oscillator not bypassed + name: NotBypassed + value: 0 + - description: HSE crystal oscillator bypassed with external clock + name: Bypassed + value: 1 +enum/ICSEL: + bit_size: 2 + variants: + - description: APB clock selected as I2C clock + name: APB + value: 0 + - description: System clock selected as I2C clock + name: SYSCLK + value: 1 + - description: HSI clock selected as I2C clock + name: HSI + value: 2 +enum/ISSRC: + bit_size: 1 + variants: + - description: PLLI2S clock used as I2S clock source + name: PLLI2S + value: 0 + - description: External clock mapped on the I2S_CKIN pin used as I2S clock source + name: CKIN + value: 1 +enum/LPTIMSEL: + bit_size: 2 + variants: + - description: APB1 clock (PCLK1) selected as LPTILM1 clock + name: APB1 + value: 0 + - description: LSI clock is selected as LPTILM1 clock + name: LSI + value: 1 + - description: HSI clock is selected as LPTILM1 clock + name: HSI + value: 2 + - description: LSE clock is selected as LPTILM1 clock + name: LSE + value: 3 +enum/LPWRRSTFR: + bit_size: 1 + variants: + - description: No reset has occured + name: NoReset + value: 0 + - description: A reset has occured + name: Reset + value: 1 +enum/LSEBYP: + bit_size: 1 + variants: + - description: LSE crystal oscillator not bypassed + name: NotBypassed + value: 0 + - description: LSE crystal oscillator bypassed with external clock + name: Bypassed + value: 1 +enum/LSEDRV: + bit_size: 2 + variants: + - description: Low drive capacity + name: Low + value: 0 + - description: Medium-high drive capacity + name: MediumHigh + value: 1 + - description: Medium-low drive capacity + name: MediumLow + value: 2 + - description: High drive capacity + name: High + value: 3 +enum/LSERDYR: + bit_size: 1 + variants: + - description: LSE oscillator not ready + name: NotReady + value: 0 + - description: LSE oscillator ready + name: Ready + value: 1 +enum/LSIRDYR: + bit_size: 1 + variants: + - description: LSI oscillator not ready + name: NotReady + value: 0 + - description: LSI oscillator ready + name: Ready + value: 1 +enum/MCO1: + bit_size: 2 + variants: + - description: HSI clock selected + name: HSI + value: 0 + - description: LSE oscillator selected + name: LSE + value: 1 + - description: HSE oscillator clock selected + name: HSE + value: 2 + - description: PLL clock selected + name: PLL + value: 3 +enum/MCO2: + bit_size: 2 + variants: + - description: System clock (SYSCLK) selected + name: SYSCLK + value: 0 + - description: PLLI2S clock selected + name: PLLI2S + value: 1 + - description: HSE oscillator clock selected + name: HSE + value: 2 + - description: PLL clock selected + name: PLL + value: 3 +enum/MCOPRE: + bit_size: 3 + variants: + - description: No division + name: Div1 + value: 0 + - description: Division by 2 + name: Div2 + value: 4 + - description: Division by 3 + name: Div3 + value: 5 + - description: Division by 4 + name: Div4 + value: 6 + - description: Division by 5 + name: Div5 + value: 7 +enum/PLLISDIVQ: + bit_size: 5 + variants: + - description: PLLI2SDIVQ = /1 + name: Div1 + value: 0 + - description: PLLI2SDIVQ = /2 + name: Div2 + value: 1 + - description: PLLI2SDIVQ = /3 + name: Div3 + value: 2 + - description: PLLI2SDIVQ = /4 + name: Div4 + value: 3 + - description: PLLI2SDIVQ = /5 + name: Div5 + value: 4 + - description: PLLI2SDIVQ = /6 + name: Div6 + value: 5 + - description: PLLI2SDIVQ = /7 + name: Div7 + value: 6 + - description: PLLI2SDIVQ = /8 + name: Div8 + value: 7 + - description: PLLI2SDIVQ = /9 + name: Div9 + value: 8 + - description: PLLI2SDIVQ = /10 + name: Div10 + value: 9 + - description: PLLI2SDIVQ = /11 + name: Div11 + value: 10 + - description: PLLI2SDIVQ = /12 + name: Div12 + value: 11 + - description: PLLI2SDIVQ = /13 + name: Div13 + value: 12 + - description: PLLI2SDIVQ = /14 + name: Div14 + value: 13 + - description: PLLI2SDIVQ = /15 + name: Div15 + value: 14 + - description: PLLI2SDIVQ = /16 + name: Div16 + value: 15 + - description: PLLI2SDIVQ = /17 + name: Div17 + value: 16 + - description: PLLI2SDIVQ = /18 + name: Div18 + value: 17 + - description: PLLI2SDIVQ = /19 + name: Div19 + value: 18 + - description: PLLI2SDIVQ = /20 + name: Div20 + value: 19 + - description: PLLI2SDIVQ = /21 + name: Div21 + value: 20 + - description: PLLI2SDIVQ = /22 + name: Div22 + value: 21 + - description: PLLI2SDIVQ = /23 + name: Div23 + value: 22 + - description: PLLI2SDIVQ = /24 + name: Div24 + value: 23 + - description: PLLI2SDIVQ = /25 + name: Div25 + value: 24 + - description: PLLI2SDIVQ = /26 + name: Div26 + value: 25 + - description: PLLI2SDIVQ = /27 + name: Div27 + value: 26 + - description: PLLI2SDIVQ = /28 + name: Div28 + value: 27 + - description: PLLI2SDIVQ = /29 + name: Div29 + value: 28 + - description: PLLI2SDIVQ = /30 + name: Div30 + value: 29 + - description: PLLI2SDIVQ = /31 + name: Div31 + value: 30 + - description: PLLI2SDIVQ = /32 + name: Div32 + value: 31 +enum/PLLISP: + bit_size: 2 + variants: + - description: PLL*P=2 + name: Div2 + value: 0 + - description: PLL*P=4 + name: Div4 + value: 1 + - description: PLL*P=6 + name: Div6 + value: 2 + - description: PLL*P=8 + name: Div8 + value: 3 +enum/PLLISRDYR: + bit_size: 1 + variants: + - description: Clock not ready + name: NotReady + value: 0 + - description: Clock ready + name: Ready + value: 1 +enum/PLLP: + bit_size: 2 + variants: + - description: PLLP=2 + name: Div2 + value: 0 + - description: PLLP=4 + name: Div4 + value: 1 + - description: PLLP=6 + name: Div6 + value: 2 + - description: PLLP=8 + name: Div8 + value: 3 +enum/PLLSAIDIVQ: + bit_size: 5 + variants: + - description: PLLSAIDIVQ = /1 + name: Div1 + value: 0 + - description: PLLSAIDIVQ = /2 + name: Div2 + value: 1 + - description: PLLSAIDIVQ = /3 + name: Div3 + value: 2 + - description: PLLSAIDIVQ = /4 + name: Div4 + value: 3 + - description: PLLSAIDIVQ = /5 + name: Div5 + value: 4 + - description: PLLSAIDIVQ = /6 + name: Div6 + value: 5 + - description: PLLSAIDIVQ = /7 + name: Div7 + value: 6 + - description: PLLSAIDIVQ = /8 + name: Div8 + value: 7 + - description: PLLSAIDIVQ = /9 + name: Div9 + value: 8 + - description: PLLSAIDIVQ = /10 + name: Div10 + value: 9 + - description: PLLSAIDIVQ = /11 + name: Div11 + value: 10 + - description: PLLSAIDIVQ = /12 + name: Div12 + value: 11 + - description: PLLSAIDIVQ = /13 + name: Div13 + value: 12 + - description: PLLSAIDIVQ = /14 + name: Div14 + value: 13 + - description: PLLSAIDIVQ = /15 + name: Div15 + value: 14 + - description: PLLSAIDIVQ = /16 + name: Div16 + value: 15 + - description: PLLSAIDIVQ = /17 + name: Div17 + value: 16 + - description: PLLSAIDIVQ = /18 + name: Div18 + value: 17 + - description: PLLSAIDIVQ = /19 + name: Div19 + value: 18 + - description: PLLSAIDIVQ = /20 + name: Div20 + value: 19 + - description: PLLSAIDIVQ = /21 + name: Div21 + value: 20 + - description: PLLSAIDIVQ = /22 + name: Div22 + value: 21 + - description: PLLSAIDIVQ = /23 + name: Div23 + value: 22 + - description: PLLSAIDIVQ = /24 + name: Div24 + value: 23 + - description: PLLSAIDIVQ = /25 + name: Div25 + value: 24 + - description: PLLSAIDIVQ = /26 + name: Div26 + value: 25 + - description: PLLSAIDIVQ = /27 + name: Div27 + value: 26 + - description: PLLSAIDIVQ = /28 + name: Div28 + value: 27 + - description: PLLSAIDIVQ = /29 + name: Div29 + value: 28 + - description: PLLSAIDIVQ = /30 + name: Div30 + value: 29 + - description: PLLSAIDIVQ = /31 + name: Div31 + value: 30 + - description: PLLSAIDIVQ = /32 + name: Div32 + value: 31 +enum/PLLSAIDIVR: + bit_size: 2 + variants: + - description: PLLSAIDIVR = /2 + name: Div2 + value: 0 + - description: PLLSAIDIVR = /4 + name: Div4 + value: 1 + - description: PLLSAIDIVR = /8 + name: Div8 + value: 2 + - description: PLLSAIDIVR = /16 + name: Div16 + value: 3 +enum/PLLSAIP: + bit_size: 2 + variants: + - description: PLL*P=2 + name: Div2 + value: 0 + - description: PLL*P=4 + name: Div4 + value: 1 + - description: PLL*P=6 + name: Div6 + value: 2 + - description: PLL*P=8 + name: Div8 + value: 3 +enum/PLLSAIRDYCW: + bit_size: 1 + variants: + - description: Clear interrupt flag + name: Clear + value: 1 +enum/PLLSAIRDYFR: + bit_size: 1 + variants: + - description: No clock ready interrupt + name: NotInterrupted + value: 0 + - description: Clock ready interrupt + name: Interrupted + value: 1 +enum/PLLSAIRDYIE: + bit_size: 1 + variants: + - description: Interrupt disabled + name: Disabled + value: 0 + - description: Interrupt enabled + name: Enabled + value: 1 +enum/PLLSRC: + bit_size: 1 + variants: + - description: HSI clock selected as PLL and PLLI2S clock entry + name: HSI + value: 0 + - description: HSE oscillator clock selected as PLL and PLLI2S clock entry + name: HSE + value: 1 +enum/PPRE: + bit_size: 3 + variants: + - description: HCLK not divided + name: Div1 + value: 0 + - description: HCLK divided by 2 + name: Div2 + value: 4 + - description: HCLK divided by 4 + name: Div4 + value: 5 + - description: HCLK divided by 8 + name: Div8 + value: 6 + - description: HCLK divided by 16 + name: Div16 + value: 7 +enum/RMVFW: + bit_size: 1 + variants: + - description: Clears the reset flag + name: Clear + value: 1 +enum/RTCSEL: + bit_size: 2 + variants: + - description: No clock + name: NoClock + value: 0 + - description: LSE oscillator clock used as RTC clock + name: LSE + value: 1 + - description: LSI oscillator clock used as RTC clock + name: LSI + value: 2 + - description: HSE oscillator clock divided by a prescaler used as RTC clock + name: HSE + value: 3 +enum/SAISEL: + bit_size: 2 + variants: + - description: SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ + name: PLLSAI + value: 0 + - description: SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ + name: PLLI2S + value: 1 + - description: SAI2 clock frequency = Alternate function input frequency + name: AFIF + value: 2 + - description: SAI2 clock frequency = HSI or HSE + name: HSI_HSE + value: 3 +enum/SDMMCSEL: + bit_size: 1 + variants: + - description: 48 MHz clock is selected as SD clock + name: CK48M + value: 0 + - description: System clock is selected as SD clock + name: SYSCLK + value: 1 +enum/SPREADSEL: + bit_size: 1 + variants: + - description: Center spread + name: Center + value: 0 + - description: Down spread + name: Down + value: 1 +enum/SW: + bit_size: 2 + variants: + - description: HSI selected as system clock + name: HSI + value: 0 + - description: HSE selected as system clock + name: HSE + value: 1 + - description: PLL selected as system clock + name: PLL + value: 2 +enum/SWSR: + bit_size: 2 + variants: + - description: HSI oscillator used as system clock + name: HSI + value: 0 + - description: HSE oscillator used as system clock + name: HSE + value: 1 + - description: PLL used as system clock + name: PLL + value: 2 +enum/TIMPRE: + bit_size: 1 + variants: + - description: If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, + TIMxCLK = 2xPCLKx + name: Mul2 + value: 0 + - description: If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, + TIMxCLK = 4xPCLKx + name: Mul4 + value: 1 +enum/USART1SEL: + bit_size: 2 + variants: + - description: APB2 clock (PCLK2) is selected as USART clock + name: APB2 + value: 0 + - description: System clock is selected as USART clock + name: SYSCLK + value: 1 + - description: HSI clock is selected as USART clock + name: HSI + value: 2 + - description: LSE clock is selected as USART clock + name: LSE + value: 3 +enum/USART2SEL: + bit_size: 2 + variants: + - description: APB1 clock (PCLK1) is selected as USART clock + name: APB1 + value: 0 + - description: System clock is selected as USART clock + name: SYSCLK + value: 1 + - description: HSI clock is selected as USART clock + name: HSI + value: 2 + - description: LSE clock is selected as USART clock + name: LSE + value: 3 +fieldset/AHB1ENR: + description: AHB1 peripheral clock register + fields: + - bit_offset: 0 + bit_size: 1 + description: IO port A clock enable + name: GPIOAEN + - bit_offset: 1 + bit_size: 1 + description: IO port B clock enable + name: GPIOBEN + - bit_offset: 2 + bit_size: 1 + description: IO port C clock enable + name: GPIOCEN + - bit_offset: 3 + bit_size: 1 + description: IO port D clock enable + name: GPIODEN + - bit_offset: 4 + bit_size: 1 + description: IO port E clock enable + name: GPIOEEN + - bit_offset: 5 + bit_size: 1 + description: IO port F clock enable + name: GPIOFEN + - bit_offset: 6 + bit_size: 1 + description: IO port G clock enable + name: GPIOGEN + - bit_offset: 7 + bit_size: 1 + description: IO port H clock enable + name: GPIOHEN + - bit_offset: 8 + bit_size: 1 + description: IO port I clock enable + name: GPIOIEN + - bit_offset: 9 + bit_size: 1 + description: IO port J clock enable + name: GPIOJEN + - bit_offset: 10 + bit_size: 1 + description: IO port K clock enable + name: GPIOKEN + - bit_offset: 12 + bit_size: 1 + description: CRC clock enable + name: CRCEN + - bit_offset: 18 + bit_size: 1 + description: Backup SRAM interface clock enable + name: BKPSRAMEN + - bit_offset: 20 + bit_size: 1 + description: CCM data RAM clock enable + name: DTCMRAMEN + - bit_offset: 20 + bit_size: 1 + description: CCM data RAM clock enable + name: CCMDATARAMEN + - bit_offset: 21 + bit_size: 1 + description: DMA1 clock enable + name: DMA1EN + - bit_offset: 22 + bit_size: 1 + description: DMA2 clock enable + name: DMA2EN + - bit_offset: 23 + bit_size: 1 + description: DMA2D clock enable + name: DMA2DEN + - bit_offset: 25 + bit_size: 1 + description: Ethernet MAC clock enable + name: ETHMACEN + - bit_offset: 26 + bit_size: 1 + description: Ethernet Transmission clock enable + name: ETHMACTXEN + - bit_offset: 27 + bit_size: 1 + description: Ethernet Reception clock enable + name: ETHMACRXEN + - bit_offset: 28 + bit_size: 1 + description: Ethernet PTP clock enable + name: ETHMACPTPEN + - bit_offset: 29 + bit_size: 1 + description: USB OTG HS clock enable + name: OTGHSEN + - bit_offset: 30 + bit_size: 1 + description: USB OTG HSULPI clock enable + name: OTGHSULPIEN +fieldset/AHB1LPENR: + description: AHB1 peripheral clock enable in low power mode register + fields: + - bit_offset: 0 + bit_size: 1 + description: IO port A clock enable during sleep mode + name: GPIOALPEN + - bit_offset: 1 + bit_size: 1 + description: IO port B clock enable during Sleep mode + name: GPIOBLPEN + - bit_offset: 2 + bit_size: 1 + description: IO port C clock enable during Sleep mode + name: GPIOCLPEN + - bit_offset: 3 + bit_size: 1 + description: IO port D clock enable during Sleep mode + name: GPIODLPEN + - bit_offset: 4 + bit_size: 1 + description: IO port E clock enable during Sleep mode + name: GPIOELPEN + - bit_offset: 5 + bit_size: 1 + description: IO port F clock enable during Sleep mode + name: GPIOFLPEN + - bit_offset: 6 + bit_size: 1 + description: IO port G clock enable during Sleep mode + name: GPIOGLPEN + - bit_offset: 7 + bit_size: 1 + description: IO port H clock enable during Sleep mode + name: GPIOHLPEN + - bit_offset: 8 + bit_size: 1 + description: IO port I clock enable during Sleep mode + name: GPIOILPEN + - bit_offset: 9 + bit_size: 1 + description: IO port J clock enable during Sleep mode + name: GPIOJLPEN + - bit_offset: 10 + bit_size: 1 + description: IO port K clock enable during Sleep mode + name: GPIOKLPEN + - bit_offset: 12 + bit_size: 1 + description: CRC clock enable during Sleep mode + name: CRCLPEN + - bit_offset: 13 + bit_size: 1 + description: AXI to AHB bridge clock enable during Sleep mode + name: AXILPEN + - bit_offset: 15 + bit_size: 1 + description: Flash interface clock enable during Sleep mode + name: FLITFLPEN + - bit_offset: 16 + bit_size: 1 + description: SRAM 1interface clock enable during Sleep mode + name: SRAM1LPEN + - bit_offset: 17 + bit_size: 1 + description: SRAM 2 interface clock enable during Sleep mode + name: SRAM2LPEN + - bit_offset: 18 + bit_size: 1 + description: Backup SRAM interface clock enable during Sleep mode + name: BKPSRAMLPEN + - bit_offset: 19 + bit_size: 1 + description: SRAM 3 interface clock enable during Sleep mode + name: SRAM3LPEN + - bit_offset: 20 + bit_size: 1 + description: DTCM RAM interface clock enable during Sleep mode + name: DTCMLPEN + - bit_offset: 21 + bit_size: 1 + description: DMA1 clock enable during Sleep mode + name: DMA1LPEN + - bit_offset: 22 + bit_size: 1 + description: DMA2 clock enable during Sleep mode + name: DMA2LPEN + - bit_offset: 23 + bit_size: 1 + description: DMA2D clock enable during Sleep mode + name: DMA2DLPEN + - bit_offset: 25 + bit_size: 1 + description: Ethernet MAC clock enable during Sleep mode + name: ETHMACLPEN + - bit_offset: 26 + bit_size: 1 + description: Ethernet transmission clock enable during Sleep mode + name: ETHMACTXLPEN + - bit_offset: 27 + bit_size: 1 + description: Ethernet reception clock enable during Sleep mode + name: ETHMACRXLPEN + - bit_offset: 28 + bit_size: 1 + description: Ethernet PTP clock enable during Sleep mode + name: ETHMACPTPLPEN + - bit_offset: 29 + bit_size: 1 + description: USB OTG HS clock enable during Sleep mode + name: OTGHSLPEN + - bit_offset: 30 + bit_size: 1 + description: USB OTG HS ULPI clock enable during Sleep mode + name: OTGHSULPILPEN +fieldset/AHB1RSTR: + description: AHB1 peripheral reset register + fields: + - bit_offset: 0 + bit_size: 1 + description: IO port A reset + name: GPIOARST + - bit_offset: 1 + bit_size: 1 + description: IO port B reset + name: GPIOBRST + - bit_offset: 2 + bit_size: 1 + description: IO port C reset + name: GPIOCRST + - bit_offset: 3 + bit_size: 1 + description: IO port D reset + name: GPIODRST + - bit_offset: 4 + bit_size: 1 + description: IO port E reset + name: GPIOERST + - bit_offset: 5 + bit_size: 1 + description: IO port F reset + name: GPIOFRST + - bit_offset: 6 + bit_size: 1 + description: IO port G reset + name: GPIOGRST + - bit_offset: 7 + bit_size: 1 + description: IO port H reset + name: GPIOHRST + - bit_offset: 8 + bit_size: 1 + description: IO port I reset + name: GPIOIRST + - bit_offset: 9 + bit_size: 1 + description: IO port J reset + name: GPIOJRST + - bit_offset: 10 + bit_size: 1 + description: IO port K reset + name: GPIOKRST + - bit_offset: 12 + bit_size: 1 + description: CRC reset + name: CRCRST + - bit_offset: 21 + bit_size: 1 + description: DMA2 reset + name: DMA1RST + - bit_offset: 22 + bit_size: 1 + description: DMA2 reset + name: DMA2RST + - bit_offset: 23 + bit_size: 1 + description: DMA2D reset + name: DMA2DRST + - bit_offset: 25 + bit_size: 1 + description: Ethernet MAC reset + name: ETHMACRST + - bit_offset: 29 + bit_size: 1 + description: USB OTG HS module reset + name: OTGHSRST +fieldset/AHB2ENR: + description: AHB2 peripheral clock enable register + fields: + - bit_offset: 0 + bit_size: 1 + description: Camera interface enable + name: DCMIEN + - bit_offset: 4 + bit_size: 1 + description: AES module clock enable + name: AESEN + - bit_offset: 4 + bit_size: 1 + description: Cryptographic modules clock enable + name: CRYPEN + - bit_offset: 5 + bit_size: 1 + description: Hash modules clock enable + name: HASHEN + - bit_offset: 6 + bit_size: 1 + description: Random number generator clock enable + name: RNGEN + - bit_offset: 7 + bit_size: 1 + description: USB OTG FS clock enable + name: OTGFSEN +fieldset/AHB2LPENR: + description: AHB2 peripheral clock enable in low power mode register + fields: + - bit_offset: 0 + bit_size: 1 + description: Camera interface enable during Sleep mode + name: DCMILPEN + - bit_offset: 4 + bit_size: 1 + description: AES module clock enable during Sleep mode + name: AESLPEN + - bit_offset: 4 + bit_size: 1 + description: Cryptography modules clock enable during Sleep mode + name: CRYPLPEN + - bit_offset: 5 + bit_size: 1 + description: Hash modules clock enable during Sleep mode + name: HASHLPEN + - bit_offset: 6 + bit_size: 1 + description: Random number generator clock enable during Sleep mode + name: RNGLPEN + - bit_offset: 7 + bit_size: 1 + description: USB OTG FS clock enable during Sleep mode + name: OTGFSLPEN +fieldset/AHB2RSTR: + description: AHB2 peripheral reset register + fields: + - bit_offset: 0 + bit_size: 1 + description: Camera interface reset + name: DCMIRST + - bit_offset: 4 + bit_size: 1 + description: AES module reset + name: AESRST + - bit_offset: 4 + bit_size: 1 + description: Cryptographic module reset + name: CRYPRST + - bit_offset: 5 + bit_size: 1 + description: Hash module reset + name: HSAHRST + - bit_offset: 6 + bit_size: 1 + description: Random number generator module reset + name: RNGRST + - bit_offset: 7 + bit_size: 1 + description: USB OTG FS module reset + name: OTGFSRST +fieldset/AHB3ENR: + description: AHB3 peripheral clock enable register + fields: + - bit_offset: 0 + bit_size: 1 + description: Flexible memory controller module clock enable + name: FMCEN + - bit_offset: 1 + bit_size: 1 + description: Quad SPI memory controller clock enable + name: QSPIEN +fieldset/AHB3LPENR: + description: AHB3 peripheral clock enable in low power mode register + fields: + - bit_offset: 0 + bit_size: 1 + description: Flexible memory controller module clock enable during Sleep mode + name: FMCLPEN + - bit_offset: 1 + bit_size: 1 + description: Quand SPI memory controller clock enable during Sleep mode + name: QSPILPEN +fieldset/AHB3RSTR: + description: AHB3 peripheral reset register + fields: + - bit_offset: 0 + bit_size: 1 + description: Flexible memory controller module reset + name: FMCRST + - bit_offset: 1 + bit_size: 1 + description: Quad SPI memory controller reset + name: QSPIRST +fieldset/APB1ENR: + description: APB1 peripheral clock enable register + fields: + - bit_offset: 0 + bit_size: 1 + description: TIM2 clock enable + name: TIM2EN + - bit_offset: 1 + bit_size: 1 + description: TIM3 clock enable + name: TIM3EN + - bit_offset: 2 + bit_size: 1 + description: TIM4 clock enable + name: TIM4EN + - bit_offset: 3 + bit_size: 1 + description: TIM5 clock enable + name: TIM5EN + - bit_offset: 4 + bit_size: 1 + description: TIM6 clock enable + name: TIM6EN + - bit_offset: 5 + bit_size: 1 + description: TIM7 clock enable + name: TIM7EN + - bit_offset: 6 + bit_size: 1 + description: TIM12 clock enable + name: TIM12EN + - bit_offset: 7 + bit_size: 1 + description: TIM13 clock enable + name: TIM13EN + - bit_offset: 8 + bit_size: 1 + description: TIM14 clock enable + name: TIM14EN + - bit_offset: 9 + bit_size: 1 + description: Low power timer 1 clock enable + name: LPTIM1EN + - bit_offset: 9 + bit_size: 1 + description: Low power timer 1 clock enable + name: LPTMI1EN + - bit_offset: 10 + bit_size: 1 + description: RTCAPB clock enable + name: RTCAPBEN + - bit_offset: 11 + bit_size: 1 + description: Window watchdog clock enable + name: WWDGEN + - bit_offset: 14 + bit_size: 1 + description: SPI2 clock enable + name: SPI2EN + - bit_offset: 15 + bit_size: 1 + description: SPI3 clock enable + name: SPI3EN + - bit_offset: 16 + bit_size: 1 + description: SPDIF-RX clock enable + name: SPDIFRXEN + - bit_offset: 17 + bit_size: 1 + description: USART 2 clock enable + name: USART2EN + - bit_offset: 18 + bit_size: 1 + description: USART3 clock enable + name: USART3EN + - bit_offset: 19 + bit_size: 1 + description: UART4 clock enable + name: UART4EN + - bit_offset: 20 + bit_size: 1 + description: UART5 clock enable + name: UART5EN + - bit_offset: 21 + bit_size: 1 + description: I2C1 clock enable + name: I2C1EN + - bit_offset: 22 + bit_size: 1 + description: I2C2 clock enable + name: I2C2EN + - bit_offset: 23 + bit_size: 1 + description: I2C3 clock enable + name: I2C3EN + - bit_offset: 24 + bit_size: 1 + description: I2C4 clock enable + name: I2C4EN + - bit_offset: 25 + bit_size: 1 + description: CAN 1 clock enable + name: CAN1EN + - bit_offset: 26 + bit_size: 1 + description: CAN 2 clock enable + name: CAN2EN + - bit_offset: 27 + bit_size: 1 + description: HDMI-CEN clock enable + name: CECEN + - bit_offset: 28 + bit_size: 1 + description: Power interface clock enable + name: PWREN + - bit_offset: 29 + bit_size: 1 + description: DAC interface clock enable + name: DACEN + - bit_offset: 30 + bit_size: 1 + description: UART7 clock enable + name: UART7EN + - bit_offset: 31 + bit_size: 1 + description: UART8 clock enable + name: UART8EN +fieldset/APB1LPENR: + description: APB1 peripheral clock enable in low power mode register + fields: + - bit_offset: 0 + bit_size: 1 + description: TIM2 clock enable during Sleep mode + name: TIM2LPEN + - bit_offset: 1 + bit_size: 1 + description: TIM3 clock enable during Sleep mode + name: TIM3LPEN + - bit_offset: 2 + bit_size: 1 + description: TIM4 clock enable during Sleep mode + name: TIM4LPEN + - bit_offset: 3 + bit_size: 1 + description: TIM5 clock enable during Sleep mode + name: TIM5LPEN + - bit_offset: 4 + bit_size: 1 + description: TIM6 clock enable during Sleep mode + name: TIM6LPEN + - bit_offset: 5 + bit_size: 1 + description: TIM7 clock enable during Sleep mode + name: TIM7LPEN + - bit_offset: 6 + bit_size: 1 + description: TIM12 clock enable during Sleep mode + name: TIM12LPEN + - bit_offset: 7 + bit_size: 1 + description: TIM13 clock enable during Sleep mode + name: TIM13LPEN + - bit_offset: 8 + bit_size: 1 + description: TIM14 clock enable during Sleep mode + name: TIM14LPEN + - bit_offset: 9 + bit_size: 1 + description: low power timer 1 clock enable during Sleep mode + name: LPTIM1LPEN + - bit_offset: 11 + bit_size: 1 + description: Window watchdog clock enable during Sleep mode + name: WWDGLPEN + - bit_offset: 14 + bit_size: 1 + description: SPI2 clock enable during Sleep mode + name: SPI2LPEN + - bit_offset: 15 + bit_size: 1 + description: SPI3 clock enable during Sleep mode + name: SPI3LPEN + - bit_offset: 16 + bit_size: 1 + description: SPDIF-RX clock enable during sleep mode + name: SPDIFRXLPEN + - bit_offset: 17 + bit_size: 1 + description: USART2 clock enable during Sleep mode + name: USART2LPEN + - bit_offset: 18 + bit_size: 1 + description: USART3 clock enable during Sleep mode + name: USART3LPEN + - bit_offset: 19 + bit_size: 1 + description: UART4 clock enable during Sleep mode + name: UART4LPEN + - bit_offset: 20 + bit_size: 1 + description: UART5 clock enable during Sleep mode + name: UART5LPEN + - bit_offset: 21 + bit_size: 1 + description: I2C1 clock enable during Sleep mode + name: I2C1LPEN + - bit_offset: 22 + bit_size: 1 + description: I2C2 clock enable during Sleep mode + name: I2C2LPEN + - bit_offset: 23 + bit_size: 1 + description: I2C3 clock enable during Sleep mode + name: I2C3LPEN + - bit_offset: 24 + bit_size: 1 + description: I2C4 clock enable during Sleep mode + name: I2C4LPEN + - bit_offset: 25 + bit_size: 1 + description: CAN 1 clock enable during Sleep mode + name: CAN1LPEN + - bit_offset: 26 + bit_size: 1 + description: CAN 2 clock enable during Sleep mode + name: CAN2LPEN + - bit_offset: 27 + bit_size: 1 + description: HDMI-CEN clock enable during Sleep mode + name: CECLPEN + - bit_offset: 28 + bit_size: 1 + description: Power interface clock enable during Sleep mode + name: PWRLPEN + - bit_offset: 29 + bit_size: 1 + description: DAC interface clock enable during Sleep mode + name: DACLPEN + - bit_offset: 30 + bit_size: 1 + description: UART7 clock enable during Sleep mode + name: UART7LPEN + - bit_offset: 31 + bit_size: 1 + description: UART8 clock enable during Sleep mode + name: UART8LPEN +fieldset/APB1RSTR: + description: APB1 peripheral reset register + fields: + - bit_offset: 0 + bit_size: 1 + description: TIM2 reset + name: TIM2RST + - bit_offset: 1 + bit_size: 1 + description: TIM3 reset + name: TIM3RST + - bit_offset: 2 + bit_size: 1 + description: TIM4 reset + name: TIM4RST + - bit_offset: 3 + bit_size: 1 + description: TIM5 reset + name: TIM5RST + - bit_offset: 4 + bit_size: 1 + description: TIM6 reset + name: TIM6RST + - bit_offset: 5 + bit_size: 1 + description: TIM7 reset + name: TIM7RST + - bit_offset: 6 + bit_size: 1 + description: TIM12 reset + name: TIM12RST + - bit_offset: 7 + bit_size: 1 + description: TIM13 reset + name: TIM13RST + - bit_offset: 8 + bit_size: 1 + description: TIM14 reset + name: TIM14RST + - bit_offset: 9 + bit_size: 1 + description: Low power timer 1 reset + name: LPTIM1RST + - bit_offset: 11 + bit_size: 1 + description: Window watchdog reset + name: WWDGRST + - bit_offset: 14 + bit_size: 1 + description: SPI 2 reset + name: SPI2RST + - bit_offset: 15 + bit_size: 1 + description: SPI 3 reset + name: SPI3RST + - bit_offset: 16 + bit_size: 1 + description: SPDIF-RX reset + name: SPDIFRXRST + - bit_offset: 17 + bit_size: 1 + description: USART 2 reset + name: UART2RST + - bit_offset: 18 + bit_size: 1 + description: USART 3 reset + name: UART3RST + - bit_offset: 19 + bit_size: 1 + description: USART 4 reset + name: UART4RST + - bit_offset: 20 + bit_size: 1 + description: USART 5 reset + name: UART5RST + - bit_offset: 21 + bit_size: 1 + description: I2C 1 reset + name: I2C1RST + - bit_offset: 22 + bit_size: 1 + description: I2C 2 reset + name: I2C2RST + - bit_offset: 23 + bit_size: 1 + description: I2C3 reset + name: I2C3RST + - bit_offset: 24 + bit_size: 1 + description: I2C 4 reset + name: I2C4RST + - bit_offset: 25 + bit_size: 1 + description: CAN1 reset + name: CAN1RST + - bit_offset: 26 + bit_size: 1 + description: CAN2 reset + name: CAN2RST + - bit_offset: 27 + bit_size: 1 + description: HDMI-CEC reset + name: CECRST + - bit_offset: 28 + bit_size: 1 + description: Power interface reset + name: PWRRST + - bit_offset: 29 + bit_size: 1 + description: DAC reset + name: DACRST + - bit_offset: 30 + bit_size: 1 + description: UART7 reset + name: UART7RST + - bit_offset: 31 + bit_size: 1 + description: UART8 reset + name: UART8RST +fieldset/APB2ENR: + description: APB2 peripheral clock enable register + fields: + - bit_offset: 0 + bit_size: 1 + description: TIM1 clock enable + name: TIM1EN + - bit_offset: 1 + bit_size: 1 + description: TIM8 clock enable + name: TIM8EN + - bit_offset: 4 + bit_size: 1 + description: USART1 clock enable + name: USART1EN + - bit_offset: 5 + bit_size: 1 + description: USART6 clock enable + name: USART6EN + - bit_offset: 7 + bit_size: 1 + description: SDMMC2 clock enable + name: SDMMC2EN + - bit_offset: 8 + bit_size: 1 + description: ADC1 clock enable + name: ADC1EN + - bit_offset: 9 + bit_size: 1 + description: ADC2 clock enable + name: ADC2EN + - bit_offset: 10 + bit_size: 1 + description: ADC3 clock enable + name: ADC3EN + - bit_offset: 11 + bit_size: 1 + description: SDMMC1 clock enable + name: SDMMC1EN + - bit_offset: 12 + bit_size: 1 + description: SPI1 clock enable + name: SPI1EN + - bit_offset: 13 + bit_size: 1 + description: SPI4 clock enable + name: SPI4EN + - bit_offset: 14 + bit_size: 1 + description: System configuration controller clock enable + name: SYSCFGEN + - bit_offset: 16 + bit_size: 1 + description: TIM9 clock enable + name: TIM9EN + - bit_offset: 17 + bit_size: 1 + description: TIM10 clock enable + name: TIM10EN + - bit_offset: 18 + bit_size: 1 + description: TIM11 clock enable + name: TIM11EN + - bit_offset: 20 + bit_size: 1 + description: SPI5 clock enable + name: SPI5EN + - bit_offset: 21 + bit_size: 1 + description: SPI6 clock enable + name: SPI6EN + - bit_offset: 22 + bit_size: 1 + description: SAI1 clock enable + name: SAI1EN + - bit_offset: 23 + bit_size: 1 + description: SAI2 clock enable + name: SAI2EN + - bit_offset: 26 + bit_size: 1 + description: LTDC clock enable + name: LTDCEN + - bit_offset: 30 + bit_size: 1 + description: MDIO clock enable + name: MDIOEN + - bit_offset: 31 + bit_size: 1 + description: USB OTG HS PHY controller clock enable + name: USBPHYCEN +fieldset/APB2LPENR: + description: APB2 peripheral clock enabled in low power mode register + fields: + - bit_offset: 0 + bit_size: 1 + description: TIM1 clock enable during Sleep mode + name: TIM1LPEN + - bit_offset: 1 + bit_size: 1 + description: TIM8 clock enable during Sleep mode + name: TIM8LPEN + - bit_offset: 4 + bit_size: 1 + description: USART1 clock enable during Sleep mode + name: USART1LPEN + - bit_offset: 5 + bit_size: 1 + description: USART6 clock enable during Sleep mode + name: USART6LPEN + - bit_offset: 7 + bit_size: 1 + description: SDMMC2 clock enable during Sleep mode + name: SDMMC2LPEN + - bit_offset: 8 + bit_size: 1 + description: ADC1 clock enable during Sleep mode + name: ADC1LPEN + - bit_offset: 9 + bit_size: 1 + description: ADC2 clock enable during Sleep mode + name: ADC2LPEN + - bit_offset: 10 + bit_size: 1 + description: ADC 3 clock enable during Sleep mode + name: ADC3LPEN + - bit_offset: 11 + bit_size: 1 + description: SDMMC1 clock enable during Sleep mode + name: SDMMC1LPEN + - bit_offset: 12 + bit_size: 1 + description: SPI 1 clock enable during Sleep mode + name: SPI1LPEN + - bit_offset: 13 + bit_size: 1 + description: SPI 4 clock enable during Sleep mode + name: SPI4LPEN + - bit_offset: 14 + bit_size: 1 + description: System configuration controller clock enable during Sleep mode + name: SYSCFGLPEN + - bit_offset: 16 + bit_size: 1 + description: TIM9 clock enable during sleep mode + name: TIM9LPEN + - bit_offset: 17 + bit_size: 1 + description: TIM10 clock enable during Sleep mode + name: TIM10LPEN + - bit_offset: 18 + bit_size: 1 + description: TIM11 clock enable during Sleep mode + name: TIM11LPEN + - bit_offset: 20 + bit_size: 1 + description: SPI 5 clock enable during Sleep mode + name: SPI5LPEN + - bit_offset: 21 + bit_size: 1 + description: SPI 6 clock enable during Sleep mode + name: SPI6LPEN + - bit_offset: 22 + bit_size: 1 + description: SAI1 clock enable during sleep mode + name: SAI1LPEN + - bit_offset: 23 + bit_size: 1 + description: SAI2 clock enable during sleep mode + name: SAI2LPEN + - bit_offset: 26 + bit_size: 1 + description: LTDC clock enable during sleep mode + name: LTDCLPEN +fieldset/APB2RSTR: + description: APB2 peripheral reset register + fields: + - bit_offset: 0 + bit_size: 1 + description: TIM1 reset + name: TIM1RST + - bit_offset: 1 + bit_size: 1 + description: TIM8 reset + name: TIM8RST + - bit_offset: 4 + bit_size: 1 + description: USART1 reset + name: USART1RST + - bit_offset: 5 + bit_size: 1 + description: USART6 reset + name: USART6RST + - bit_offset: 7 + bit_size: 1 + description: SDMMC2 reset + name: SDMMC2RST + - bit_offset: 8 + bit_size: 1 + description: ADC interface reset (common to all ADCs) + name: ADCRST + - bit_offset: 11 + bit_size: 1 + description: SDMMC1 reset + name: SDMMC1RST + - bit_offset: 12 + bit_size: 1 + description: SPI 1 reset + name: SPI1RST + - bit_offset: 13 + bit_size: 1 + description: SPI4 reset + name: SPI4RST + - bit_offset: 14 + bit_size: 1 + description: System configuration controller reset + name: SYSCFGRST + - bit_offset: 16 + bit_size: 1 + description: TIM9 reset + name: TIM9RST + - bit_offset: 17 + bit_size: 1 + description: TIM10 reset + name: TIM10RST + - bit_offset: 18 + bit_size: 1 + description: TIM11 reset + name: TIM11RST + - bit_offset: 20 + bit_size: 1 + description: SPI5 reset + name: SPI5RST + - bit_offset: 21 + bit_size: 1 + description: SPI6 reset + name: SPI6RST + - bit_offset: 22 + bit_size: 1 + description: SAI1 reset + name: SAI1RST + - bit_offset: 23 + bit_size: 1 + description: SAI2 reset + name: SAI2RST + - bit_offset: 26 + bit_size: 1 + description: LTDC reset + name: LTDCRST + - bit_offset: 31 + bit_size: 1 + description: USB OTG HS PHY controller reset + name: USBPHYCRST +fieldset/BDCR: + description: Backup domain control register + fields: + - bit_offset: 0 + bit_size: 1 + description: External low-speed oscillator enable + name: LSEON + - bit_offset: 1 + bit_size: 1 + description: External low-speed oscillator ready + enum_read: LSERDYR + name: LSERDY + - bit_offset: 2 + bit_size: 1 + description: External low-speed oscillator bypass + enum: LSEBYP + name: LSEBYP + - bit_offset: 3 + bit_size: 2 + description: LSE oscillator drive capability + enum: LSEDRV + name: LSEDRV + - bit_offset: 8 + bit_size: 2 + description: RTC clock source selection + enum: RTCSEL + name: RTCSEL + - bit_offset: 15 + bit_size: 1 + description: RTC clock enable + name: RTCEN + - bit_offset: 16 + bit_size: 1 + description: Backup domain software reset + name: BDRST +fieldset/CFGR: + description: clock configuration register + fields: + - bit_offset: 0 + bit_size: 2 + description: System clock switch + enum: SW + name: SW + - bit_offset: 2 + bit_size: 2 + description: System clock switch status + enum_read: SWSR + name: SWS + - bit_offset: 4 + bit_size: 4 + description: AHB prescaler + enum: HPRE + name: HPRE + - bit_offset: 10 + bit_size: 3 + description: APB Low speed prescaler (APB1) + enum: PPRE + name: PPRE1 + - bit_offset: 13 + bit_size: 3 + description: APB high-speed prescaler (APB2) + enum: PPRE + name: PPRE2 + - bit_offset: 16 + bit_size: 5 + description: HSE division factor for RTC clock + name: RTCPRE + - bit_offset: 21 + bit_size: 2 + description: Microcontroller clock output 1 + enum: MCO1 + name: MCO1 + - bit_offset: 23 + bit_size: 1 + description: I2S clock selection + enum: ISSRC + name: I2SSRC + - bit_offset: 24 + bit_size: 3 + description: MCO1 prescaler + enum: MCOPRE + name: MCO1PRE + - bit_offset: 27 + bit_size: 3 + description: MCO2 prescaler + enum: MCOPRE + name: MCO2PRE + - bit_offset: 30 + bit_size: 2 + description: Microcontroller clock output 2 + enum: MCO2 + name: MCO2 +fieldset/CIR: + description: clock interrupt register + fields: + - bit_offset: 0 + bit_size: 1 + description: LSI ready interrupt flag + enum_read: PLLSAIRDYFR + name: LSIRDYF + - bit_offset: 1 + bit_size: 1 + description: LSE ready interrupt flag + enum_read: PLLSAIRDYFR + name: LSERDYF + - bit_offset: 2 + bit_size: 1 + description: HSI ready interrupt flag + enum_read: PLLSAIRDYFR + name: HSIRDYF + - bit_offset: 3 + bit_size: 1 + description: HSE ready interrupt flag + enum_read: PLLSAIRDYFR + name: HSERDYF + - bit_offset: 4 + bit_size: 1 + description: Main PLL (PLL) ready interrupt flag + enum_read: PLLSAIRDYFR + name: PLLRDYF + - bit_offset: 5 + bit_size: 1 + description: PLLI2S ready interrupt flag + enum_read: PLLSAIRDYFR + name: PLLI2SRDYF + - bit_offset: 6 + bit_size: 1 + description: PLLSAI ready interrupt flag + enum_read: PLLSAIRDYFR + name: PLLSAIRDYF + - bit_offset: 7 + bit_size: 1 + description: Clock security system interrupt flag + enum_read: CSSFR + name: CSSF + - bit_offset: 8 + bit_size: 1 + description: LSI ready interrupt enable + enum: PLLSAIRDYIE + name: LSIRDYIE + - bit_offset: 9 + bit_size: 1 + description: LSE ready interrupt enable + enum: PLLSAIRDYIE + name: LSERDYIE + - bit_offset: 10 + bit_size: 1 + description: HSI ready interrupt enable + enum: PLLSAIRDYIE + name: HSIRDYIE + - bit_offset: 11 + bit_size: 1 + description: HSE ready interrupt enable + enum: PLLSAIRDYIE + name: HSERDYIE + - bit_offset: 12 + bit_size: 1 + description: Main PLL (PLL) ready interrupt enable + enum: PLLSAIRDYIE + name: PLLRDYIE + - bit_offset: 13 + bit_size: 1 + description: PLLI2S ready interrupt enable + enum: PLLSAIRDYIE + name: PLLI2SRDYIE + - bit_offset: 14 + bit_size: 1 + description: PLLSAI Ready Interrupt Enable + enum: PLLSAIRDYIE + name: PLLSAIRDYIE + - bit_offset: 16 + bit_size: 1 + description: LSI ready interrupt clear + enum_write: PLLSAIRDYCW + name: LSIRDYC + - bit_offset: 17 + bit_size: 1 + description: LSE ready interrupt clear + enum_write: PLLSAIRDYCW + name: LSERDYC + - bit_offset: 18 + bit_size: 1 + description: HSI ready interrupt clear + enum_write: PLLSAIRDYCW + name: HSIRDYC + - bit_offset: 19 + bit_size: 1 + description: HSE ready interrupt clear + enum_write: PLLSAIRDYCW + name: HSERDYC + - bit_offset: 20 + bit_size: 1 + description: Main PLL(PLL) ready interrupt clear + enum_write: PLLSAIRDYCW + name: PLLRDYC + - bit_offset: 21 + bit_size: 1 + description: PLLI2S ready interrupt clear + enum_write: PLLSAIRDYCW + name: PLLI2SRDYC + - bit_offset: 22 + bit_size: 1 + description: PLLSAI Ready Interrupt Clear + enum_write: PLLSAIRDYCW + name: PLLSAIRDYC + - bit_offset: 23 + bit_size: 1 + description: Clock security system interrupt clear + enum_write: CSSCW + name: CSSC +fieldset/CR: + description: clock control register + fields: + - bit_offset: 0 + bit_size: 1 + description: Internal high-speed clock enable + name: HSION + - bit_offset: 1 + bit_size: 1 + description: Internal high-speed clock ready flag + enum_read: PLLISRDYR + name: HSIRDY + - bit_offset: 3 + bit_size: 5 + description: Internal high-speed clock trimming + name: HSITRIM + - bit_offset: 8 + bit_size: 8 + description: Internal high-speed clock calibration + name: HSICAL + - bit_offset: 16 + bit_size: 1 + description: HSE clock enable + name: HSEON + - bit_offset: 17 + bit_size: 1 + description: HSE clock ready flag + enum_read: PLLISRDYR + name: HSERDY + - bit_offset: 18 + bit_size: 1 + description: HSE clock bypass + enum: HSEBYP + name: HSEBYP + - bit_offset: 19 + bit_size: 1 + description: Clock security system enable + name: CSSON + - bit_offset: 24 + bit_size: 1 + description: Main PLL (PLL) enable + name: PLLON + - bit_offset: 25 + bit_size: 1 + description: Main PLL (PLL) clock ready flag + enum_read: PLLISRDYR + name: PLLRDY + - bit_offset: 26 + bit_size: 1 + description: PLLI2S enable + name: PLLI2SON + - bit_offset: 27 + bit_size: 1 + description: PLLI2S clock ready flag + enum_read: PLLISRDYR + name: PLLI2SRDY + - bit_offset: 28 + bit_size: 1 + description: PLLSAI enable + name: PLLSAION + - bit_offset: 29 + bit_size: 1 + description: PLLSAI clock ready flag + enum_read: PLLISRDYR + name: PLLSAIRDY +fieldset/CSR: + description: clock control & status register + fields: + - bit_offset: 0 + bit_size: 1 + description: Internal low-speed oscillator enable + name: LSION + - bit_offset: 1 + bit_size: 1 + description: Internal low-speed oscillator ready + enum_read: LSIRDYR + name: LSIRDY + - bit_offset: 24 + bit_size: 1 + description: Remove reset flag + enum_write: RMVFW + name: RMVF + - bit_offset: 25 + bit_size: 1 + description: BOR reset flag + enum_read: LPWRRSTFR + name: BORRSTF + - bit_offset: 26 + bit_size: 1 + description: PIN reset flag + enum_read: LPWRRSTFR + name: PADRSTF + - bit_offset: 27 + bit_size: 1 + description: POR/PDR reset flag + enum_read: LPWRRSTFR + name: PORRSTF + - bit_offset: 28 + bit_size: 1 + description: Software reset flag + enum_read: LPWRRSTFR + name: SFTRSTF + - bit_offset: 29 + bit_size: 1 + description: Independent watchdog reset flag + enum_read: LPWRRSTFR + name: WDGRSTF + - bit_offset: 30 + bit_size: 1 + description: Window watchdog reset flag + enum_read: LPWRRSTFR + name: WWDGRSTF + - bit_offset: 31 + bit_size: 1 + description: Low-power reset flag + enum_read: LPWRRSTFR + name: LPWRRSTF +fieldset/DCKCFGR1: + description: dedicated clocks configuration register + fields: + - bit_offset: 0 + bit_size: 5 + description: PLLI2S division factor for SAI1 clock + enum: PLLISDIVQ + name: PLLI2SDIVQ + - bit_offset: 8 + bit_size: 5 + description: PLLSAI division factor for SAI1 clock + enum: PLLSAIDIVQ + name: PLLSAIDIVQ + - bit_offset: 16 + bit_size: 2 + description: division factor for LCD_CLK + enum: PLLSAIDIVR + name: PLLSAIDIVR + - bit_offset: 20 + bit_size: 2 + description: SAI1 clock source selection + enum: SAISEL + name: SAI1SEL + - bit_offset: 22 + bit_size: 2 + description: SAI2 clock source selection + enum: SAISEL + name: SAI2SEL + - bit_offset: 24 + bit_size: 1 + description: Timers clocks prescalers selection + enum: TIMPRE + name: TIMPRE + - bit_offset: 25 + bit_size: 1 + description: DFSDM1 clock source selection + enum: DFSDMSEL + name: DFSDM1SEL + - bit_offset: 26 + bit_size: 1 + description: DFSDM1 AUDIO clock source selection + enum: ADFSDMSEL + name: ADFSDM1SEL +fieldset/DCKCFGR2: + description: dedicated clocks configuration register + fields: + - bit_offset: 0 + bit_size: 2 + description: USART 1 clock source selection + enum: USART1SEL + name: USART1SEL + - bit_offset: 2 + bit_size: 2 + description: USART 2 clock source selection + enum: USART2SEL + name: USART2SEL + - bit_offset: 4 + bit_size: 2 + description: USART 3 clock source selection + enum: USART2SEL + name: USART3SEL + - bit_offset: 6 + bit_size: 2 + description: UART 4 clock source selection + enum: USART2SEL + name: UART4SEL + - bit_offset: 8 + bit_size: 2 + description: UART 5 clock source selection + enum: USART2SEL + name: UART5SEL + - bit_offset: 10 + bit_size: 2 + description: USART 6 clock source selection + enum: USART1SEL + name: USART6SEL + - bit_offset: 12 + bit_size: 2 + description: UART 7 clock source selection + enum: USART2SEL + name: UART7SEL + - bit_offset: 14 + bit_size: 2 + description: UART 8 clock source selection + enum: USART2SEL + name: UART8SEL + - bit_offset: 16 + bit_size: 2 + description: I2C1 clock source selection + enum: ICSEL + name: I2C1SEL + - bit_offset: 18 + bit_size: 2 + description: I2C2 clock source selection + enum: ICSEL + name: I2C2SEL + - bit_offset: 20 + bit_size: 2 + description: I2C3 clock source selection + enum: ICSEL + name: I2C3SEL + - bit_offset: 22 + bit_size: 2 + description: I2C4 clock source selection + enum: ICSEL + name: I2C4SEL + - bit_offset: 24 + bit_size: 2 + description: Low power timer 1 clock source selection + enum: LPTIMSEL + name: LPTIM1SEL + - bit_offset: 26 + bit_size: 1 + description: HDMI-CEC clock source selection + enum: CECSEL + name: CECSEL + - bit_offset: 27 + bit_size: 1 + description: 48MHz clock source selection + enum: CKMSEL + name: CK48MSEL + - bit_offset: 28 + bit_size: 1 + description: SDMMC1 clock source selection + enum: SDMMCSEL + name: SDMMC1SEL + - bit_offset: 29 + bit_size: 1 + description: SDMMC2 clock source selection + enum: SDMMCSEL + name: SDMMC2SEL + - bit_offset: 30 + bit_size: 1 + description: DSI clock source selection + enum: DSISEL + name: DSISEL +fieldset/PLLCFGR: + description: PLL configuration register + fields: + - bit_offset: 0 + bit_size: 6 + description: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input + clock + name: PLLM + - bit_offset: 6 + bit_size: 9 + description: Main PLL (PLL) multiplication factor for VCO + name: PLLN + - bit_offset: 16 + bit_size: 2 + description: Main PLL (PLL) division factor for main system clock + enum: PLLP + name: PLLP + - bit_offset: 22 + bit_size: 1 + description: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source + enum: PLLSRC + name: PLLSRC + - bit_offset: 24 + bit_size: 4 + description: Main PLL (PLL) division factor for USB OTG FS, SDIO and random number + generator clocks + name: PLLQ + - bit_offset: 28 + bit_size: 3 + description: PLL division factor for DSI clock + name: PLLR +fieldset/PLLI2SCFGR: + description: PLLI2S configuration register + fields: + - bit_offset: 6 + bit_size: 9 + description: PLLI2S multiplication factor for VCO + name: PLLI2SN + - bit_offset: 16 + bit_size: 2 + description: PLLI2S division factor for SPDIFRX clock + enum: PLLISP + name: PLLI2SP + - bit_offset: 24 + bit_size: 4 + description: PLLI2S division factor for SAI1 clock + name: PLLI2SQ + - bit_offset: 28 + bit_size: 3 + description: PLLI2S division factor for I2S clocks + name: PLLI2SR +fieldset/PLLSAICFGR: + description: PLL configuration register + fields: + - bit_offset: 6 + bit_size: 9 + description: PLLSAI division factor for VCO + name: PLLSAIN + - bit_offset: 16 + bit_size: 2 + description: PLLSAI division factor for 48MHz clock + enum: PLLSAIP + name: PLLSAIP + - bit_offset: 24 + bit_size: 4 + description: PLLSAI division factor for SAI clock + name: PLLSAIQ + - bit_offset: 28 + bit_size: 3 + description: PLLSAI division factor for LCD clock + name: PLLSAIR +fieldset/SSCGR: + description: spread spectrum clock generation register + fields: + - bit_offset: 0 + bit_size: 13 + description: Modulation period + name: MODPER + - bit_offset: 13 + bit_size: 15 + description: Incrementation step + name: INCSTEP + - bit_offset: 30 + bit_size: 1 + description: Spread Select + enum: SPREADSEL + name: SPREADSEL + - bit_offset: 31 + bit_size: 1 + description: Spread spectrum modulation enable + name: SSCGEN diff --git a/data/registers/rcc_g4.yaml b/data/registers/rcc_g4.yaml new file mode 100644 index 0000000..891f7eb --- /dev/null +++ b/data/registers/rcc_g4.yaml @@ -0,0 +1,1324 @@ +--- +block/RCC: + description: Reset and clock control + items: + - name: CR + description: Clock control register + byte_offset: 0 + fieldset: CR + - name: ICSCR + description: Internal clock sources calibration register + byte_offset: 4 + fieldset: ICSCR + - name: CFGR + description: Clock configuration register + byte_offset: 8 + fieldset: CFGR + - name: PLLCFGR + description: PLL configuration register + byte_offset: 12 + fieldset: PLLCFGR + - name: CIER + description: Clock interrupt enable register + byte_offset: 24 + fieldset: CIER + - name: CIFR + description: Clock interrupt flag register + byte_offset: 28 + access: Read + fieldset: CIFR + - name: CICR + description: Clock interrupt clear register + byte_offset: 32 + access: Write + fieldset: CICR + - name: AHB1RSTR + description: AHB1 peripheral reset register + byte_offset: 40 + fieldset: AHB1RSTR + - name: AHB2RSTR + description: AHB2 peripheral reset register + byte_offset: 44 + fieldset: AHB2RSTR + - name: AHB3RSTR + description: AHB3 peripheral reset register + byte_offset: 48 + fieldset: AHB3RSTR + - name: APB1RSTR1 + description: APB1 peripheral reset register 1 + byte_offset: 56 + fieldset: APB1RSTR1 + - name: APB1RSTR2 + description: APB1 peripheral reset register 2 + byte_offset: 60 + fieldset: APB1RSTR2 + - name: APB2RSTR + description: APB2 peripheral reset register + byte_offset: 64 + fieldset: APB2RSTR + - name: AHB1ENR + description: AHB1 peripheral clock enable register + byte_offset: 72 + fieldset: AHB1ENR + - name: AHB2ENR + description: AHB2 peripheral clock enable register + byte_offset: 76 + fieldset: AHB2ENR + - name: AHB3ENR + description: AHB3 peripheral clock enable register + byte_offset: 80 + fieldset: AHB3ENR + - name: APB1ENR1 + description: APB1ENR1 + byte_offset: 88 + fieldset: APB1ENR1 + - name: APB1ENR2 + description: APB1 peripheral clock enable register 2 + byte_offset: 92 + fieldset: APB1ENR2 + - name: APB2ENR + description: APB2ENR + byte_offset: 96 + fieldset: APB2ENR + - name: AHB1SMENR + description: AHB1 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 104 + fieldset: AHB1SMENR + - name: AHB2SMENR + description: AHB2 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 108 + fieldset: AHB2SMENR + - name: AHB3SMENR + description: AHB3 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 112 + fieldset: AHB3SMENR + - name: APB1SMENR1 + description: APB1SMENR1 + byte_offset: 120 + fieldset: APB1SMENR1 + - name: APB1SMENR2 + description: APB1 peripheral clocks enable in Sleep and Stop modes register 2 + byte_offset: 124 + fieldset: APB1SMENR2 + - name: APB2SMENR + description: APB2SMENR + byte_offset: 128 + fieldset: APB2SMENR + - name: CCIPR + description: CCIPR + byte_offset: 136 + fieldset: CCIPR + - name: BDCR + description: BDCR + byte_offset: 144 + fieldset: BDCR + - name: CSR + description: CSR + byte_offset: 148 + fieldset: CSR + - name: CRRCR + description: Clock recovery RC register + byte_offset: 152 + fieldset: CRRCR + - name: CCIPR2 + description: Peripherals independent clock configuration register + byte_offset: 156 + fieldset: CCIPR2 +fieldset/AHB1ENR: + description: AHB1 peripheral clock enable register + fields: + - name: DMA1EN + description: DMA1 clock enable + bit_offset: 0 + bit_size: 1 + - name: DMA2EN + description: DMA2 clock enable + bit_offset: 1 + bit_size: 1 + - name: DMAMUXEN + description: DMAMUX clock enable + bit_offset: 2 + bit_size: 1 + - name: CORDICEN + description: CORDIC clock enable + bit_offset: 3 + bit_size: 1 + - name: FMACEN + description: FMAC clock enable + bit_offset: 4 + bit_size: 1 + - name: FLASHEN + description: Flash memory interface clock enable + bit_offset: 8 + bit_size: 1 + - name: CRCEN + description: CRC clock enable + bit_offset: 12 + bit_size: 1 +fieldset/AHB1RSTR: + description: AHB1 peripheral reset register + fields: + - name: DMA1RST + description: DMA1 reset + bit_offset: 0 + bit_size: 1 + - name: DMA2RST + description: DMA2 reset + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1RST + description: DMAMUXRST + bit_offset: 2 + bit_size: 1 + - name: CORDICRST + description: CORDIC reset + bit_offset: 3 + bit_size: 1 + - name: FMACRST + description: FMAC reset + bit_offset: 4 + bit_size: 1 + - name: FLASHRST + description: Flash memory interface reset + bit_offset: 8 + bit_size: 1 + - name: CRCRST + description: CRC reset + bit_offset: 12 + bit_size: 1 +fieldset/AHB1SMENR: + description: AHB1 peripheral clocks enable in Sleep and Stop modes register + fields: + - name: DMA1SMEN + description: DMA1 clocks enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 + - name: DMA2SMEN + description: DMA2 clocks enable during Sleep and Stop modes + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1SMEN + description: DMAMUX clock enable during Sleep and Stop modes + bit_offset: 2 + bit_size: 1 + - name: CORDICSMEN + description: CORDIC clock enable during sleep mode + bit_offset: 3 + bit_size: 1 + - name: FMACSMEN + description: FMACSM clock enable + bit_offset: 4 + bit_size: 1 + - name: FLASHSMEN + description: Flash memory interface clocks enable during Sleep and Stop modes + bit_offset: 8 + bit_size: 1 + - name: SRAM1SMEN + description: SRAM1 interface clocks enable during Sleep and Stop modes + bit_offset: 9 + bit_size: 1 + - name: CRCSMEN + description: CRCSMEN + bit_offset: 12 + bit_size: 1 +fieldset/AHB2ENR: + description: AHB2 peripheral clock enable register + fields: + - name: GPIOAEN + description: IO port A clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: IO port B clock enable + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: IO port C clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIODEN + description: IO port D clock enable + bit_offset: 3 + bit_size: 1 + - name: GPIOEEN + description: IO port E clock enable + bit_offset: 4 + bit_size: 1 + - name: GPIOFEN + description: IO port F clock enable + bit_offset: 5 + bit_size: 1 + - name: GPIOGEN + description: IO port G clock enable + bit_offset: 6 + bit_size: 1 + - name: ADC12EN + description: ADC clock enable + bit_offset: 13 + bit_size: 1 + - name: ADC345EN + description: DCMI clock enable + bit_offset: 14 + bit_size: 1 + - name: DAC1EN + description: AES accelerator clock enable + bit_offset: 16 + bit_size: 1 + - name: DAC2EN + description: HASH clock enable + bit_offset: 17 + bit_size: 1 + - name: DAC3EN + description: Random Number Generator clock enable + bit_offset: 18 + bit_size: 1 + - name: DAC4EN + description: DAC4 clock enable + bit_offset: 19 + bit_size: 1 + - name: AESEN + description: AES clock enable + bit_offset: 24 + bit_size: 1 + - name: RNGEN + description: Random Number Generator clock enable + bit_offset: 26 + bit_size: 1 +fieldset/AHB2RSTR: + description: AHB2 peripheral reset register + fields: + - name: GPIOARST + description: IO port A reset + bit_offset: 0 + bit_size: 1 + - name: GPIOBRST + description: IO port B reset + bit_offset: 1 + bit_size: 1 + - name: GPIOCRST + description: IO port C reset + bit_offset: 2 + bit_size: 1 + - name: GPIODRST + description: IO port D reset + bit_offset: 3 + bit_size: 1 + - name: GPIOERST + description: IO port E reset + bit_offset: 4 + bit_size: 1 + - name: GPIOFRST + description: IO port F reset + bit_offset: 5 + bit_size: 1 + - name: GPIOGRST + description: IO port G reset + bit_offset: 6 + bit_size: 1 + - name: ADC12RST + description: ADC reset + bit_offset: 13 + bit_size: 1 + - name: ADC345RST + description: SAR ADC345 interface reset + bit_offset: 14 + bit_size: 1 + - name: DAC1RST + description: DAC1 interface reset + bit_offset: 16 + bit_size: 1 + - name: DAC2RST + description: DAC2 interface reset + bit_offset: 17 + bit_size: 1 + - name: DAC3RST + description: DAC3 interface reset + bit_offset: 18 + bit_size: 1 + - name: DAC4RST + description: DAC4 interface reset + bit_offset: 19 + bit_size: 1 + - name: AESRST + description: Cryptography module reset + bit_offset: 24 + bit_size: 1 + - name: RNGRST + description: Random Number Generator module reset + bit_offset: 26 + bit_size: 1 +fieldset/AHB2SMENR: + description: AHB2 peripheral clocks enable in Sleep and Stop modes register + fields: + - name: GPIOASMEN + description: IO port A clocks enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 + - name: GPIOBSMEN + description: IO port B clocks enable during Sleep and Stop modes + bit_offset: 1 + bit_size: 1 + - name: GPIOCSMEN + description: IO port C clocks enable during Sleep and Stop modes + bit_offset: 2 + bit_size: 1 + - name: GPIODSMEN + description: IO port D clocks enable during Sleep and Stop modes + bit_offset: 3 + bit_size: 1 + - name: GPIOESMEN + description: IO port E clocks enable during Sleep and Stop modes + bit_offset: 4 + bit_size: 1 + - name: GPIOFSMEN + description: IO port F clocks enable during Sleep and Stop modes + bit_offset: 5 + bit_size: 1 + - name: GPIOGSMEN + description: IO port G clocks enable during Sleep and Stop modes + bit_offset: 6 + bit_size: 1 + - name: CCMSRAMSMEN + description: CCM SRAM interface clocks enable during Sleep and Stop modes + bit_offset: 9 + bit_size: 1 + - name: SRAM2SMEN + description: SRAM2 interface clocks enable during Sleep and Stop modes + bit_offset: 10 + bit_size: 1 + - name: ADC12SMEN + description: ADC clocks enable during Sleep and Stop modes + bit_offset: 13 + bit_size: 1 + - name: ADC345SMEN + description: DCMI clock enable during Sleep and Stop modes + bit_offset: 14 + bit_size: 1 + - name: DAC1SMEN + description: AES accelerator clocks enable during Sleep and Stop modes + bit_offset: 16 + bit_size: 1 + - name: DAC2SMEN + description: HASH clock enable during Sleep and Stop modes + bit_offset: 17 + bit_size: 1 + - name: DAC3SMEN + description: DAC3 clock enable during sleep mode + bit_offset: 18 + bit_size: 1 + - name: DAC4SMEN + description: DAC4 clock enable during sleep mode + bit_offset: 19 + bit_size: 1 + - name: AESMEN + description: Cryptography clock enable during sleep mode + bit_offset: 24 + bit_size: 1 + - name: RNGEN + description: Random Number Generator clock enable during sleep mode + bit_offset: 26 + bit_size: 1 +fieldset/AHB3ENR: + description: AHB3 peripheral clock enable register + fields: + - name: FMCEN + description: Flexible memory controller clock enable + bit_offset: 0 + bit_size: 1 + - name: QSPIEN + description: QUADSPI memory interface clock enable + bit_offset: 8 + bit_size: 1 +fieldset/AHB3RSTR: + description: AHB3 peripheral reset register + fields: + - name: FMCRST + description: Flexible memory controller reset + bit_offset: 0 + bit_size: 1 + - name: QSPIRST + description: Quad SPI 1 module reset + bit_offset: 8 + bit_size: 1 +fieldset/AHB3SMENR: + description: AHB3 peripheral clocks enable in Sleep and Stop modes register + fields: + - name: FMCSMEN + description: Flexible memory controller clocks enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 + - name: QSPISMEN + description: QUADSPI memory interface clock enable during Sleep and Stop modes + bit_offset: 8 + bit_size: 1 +fieldset/APB1ENR1: + description: APB1ENR1 + fields: + - name: TIM2EN + description: TIM2 timer clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: TIM3 timer clock enable + bit_offset: 1 + bit_size: 1 + - name: TIM4EN + description: TIM4 timer clock enable + bit_offset: 2 + bit_size: 1 + - name: TIM5EN + description: TIM5 timer clock enable + bit_offset: 3 + bit_size: 1 + - name: TIM6EN + description: TIM6 timer clock enable + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: TIM7 timer clock enable + bit_offset: 5 + bit_size: 1 + - name: CRSEN + description: CRSclock enable + bit_offset: 8 + bit_size: 1 + - name: RTCAPBEN + description: RTC APB clock enable + bit_offset: 10 + bit_size: 1 + - name: WWDGEN + description: Window watchdog clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI2 clock enable + bit_offset: 14 + bit_size: 1 + - name: SPI3EN + description: SPI3 clock enable + bit_offset: 15 + bit_size: 1 + - name: USART2EN + description: USART2 clock enable + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: USART3 clock enable + bit_offset: 18 + bit_size: 1 + - name: UART4EN + description: UART4 clock enable + bit_offset: 19 + bit_size: 1 + - name: UART5EN + description: UART5 clock enable + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: I2C1 clock enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C2 clock enable + bit_offset: 22 + bit_size: 1 + - name: USBEN + description: USB device clock enable + bit_offset: 23 + bit_size: 1 + - name: FDCANEN + description: FDCAN clock enable + bit_offset: 25 + bit_size: 1 + - name: PWREN + description: Power interface clock enable + bit_offset: 28 + bit_size: 1 + - name: I2C3EN + description: I2C3 clock enable + bit_offset: 30 + bit_size: 1 + - name: LPTIM1EN + description: Low power timer 1 clock enable + bit_offset: 31 + bit_size: 1 +fieldset/APB1ENR2: + description: APB1 peripheral clock enable register 2 + fields: + - name: LPUART1EN + description: Low power UART 1 clock enable + bit_offset: 0 + bit_size: 1 + - name: I2C4EN + description: I2C4 clock enable + bit_offset: 1 + bit_size: 1 + - name: UCPD1EN + description: UCPD1 clock enable + bit_offset: 8 + bit_size: 1 +fieldset/APB1RSTR1: + description: APB1 peripheral reset register 1 + fields: + - name: TIM2RST + description: TIM2 timer reset + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: TIM3 timer reset + bit_offset: 1 + bit_size: 1 + - name: TIM4RST + description: TIM3 timer reset + bit_offset: 2 + bit_size: 1 + - name: TIM5RST + description: TIM5 timer reset + bit_offset: 3 + bit_size: 1 + - name: TIM6RST + description: TIM6 timer reset + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: TIM7 timer reset + bit_offset: 5 + bit_size: 1 + - name: CRSRST + description: Clock recovery system reset + bit_offset: 8 + bit_size: 1 + - name: SPI2RST + description: SPI2 reset + bit_offset: 14 + bit_size: 1 + - name: SPI3RST + description: SPI3 reset + bit_offset: 15 + bit_size: 1 + - name: USART2RST + description: USART2 reset + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: USART3 reset + bit_offset: 18 + bit_size: 1 + - name: UART4RST + description: UART4 reset + bit_offset: 19 + bit_size: 1 + - name: UART5RST + description: UART5 reset + bit_offset: 20 + bit_size: 1 + - name: I2C1RST + description: I2C1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C2 reset + bit_offset: 22 + bit_size: 1 + - name: USBRST + description: USBD reset + bit_offset: 23 + bit_size: 1 + - name: FDCANRST + description: FDCAN reset + bit_offset: 25 + bit_size: 1 + - name: PWRRST + description: Power interface reset + bit_offset: 28 + bit_size: 1 + - name: I2C3RST + description: I2C3 interface reset + bit_offset: 30 + bit_size: 1 + - name: LPTIM1RST + description: Low Power Timer 1 reset + bit_offset: 31 + bit_size: 1 +fieldset/APB1RSTR2: + description: APB1 peripheral reset register 2 + fields: + - name: LPUART1RST + description: Low-power UART 1 reset + bit_offset: 0 + bit_size: 1 + - name: I2C4RST + description: I2C4 reset + bit_offset: 1 + bit_size: 1 + - name: UCPD1RST + description: UCPD1 reset + bit_offset: 8 + bit_size: 1 +fieldset/APB1SMENR1: + description: APB1SMENR1 + fields: + - name: TIM2SMEN + description: TIM2 timer clocks enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 + - name: TIM3SMEN + description: TIM3 timer clocks enable during Sleep and Stop modes + bit_offset: 1 + bit_size: 1 + - name: TIM4SMEN + description: TIM4 timer clocks enable during Sleep and Stop modes + bit_offset: 2 + bit_size: 1 + - name: TIM5SMEN + description: TIM5 timer clocks enable during Sleep and Stop modes + bit_offset: 3 + bit_size: 1 + - name: TIM6SMEN + description: TIM6 timer clocks enable during Sleep and Stop modes + bit_offset: 4 + bit_size: 1 + - name: TIM7SMEN + description: TIM7 timer clocks enable during Sleep and Stop modes + bit_offset: 5 + bit_size: 1 + - name: CRSSMEN + description: CRS clock enable during sleep mode + bit_offset: 8 + bit_size: 1 + - name: RTCAPBSMEN + description: RTC APB clock enable during Sleep and Stop modes + bit_offset: 10 + bit_size: 1 + - name: WWDGSMEN + description: Window watchdog clocks enable during Sleep and Stop modes + bit_offset: 11 + bit_size: 1 + - name: SPI2SMEN + description: SPI2 clocks enable during Sleep and Stop modes + bit_offset: 14 + bit_size: 1 + - name: SP3SMEN + description: SPI3 clocks enable during Sleep and Stop modes + bit_offset: 15 + bit_size: 1 + - name: USART2SMEN + description: USART2 clocks enable during Sleep and Stop modes + bit_offset: 17 + bit_size: 1 + - name: USART3SMEN + description: USART3 clocks enable during Sleep and Stop modes + bit_offset: 18 + bit_size: 1 + - name: UART4SMEN + description: UART4 clocks enable during Sleep and Stop modes + bit_offset: 19 + bit_size: 1 + - name: UART5SMEN + description: UART5 clocks enable during Sleep and Stop modes + bit_offset: 20 + bit_size: 1 + - name: I2C1SMEN + description: I2C1 clocks enable during Sleep and Stop modes + bit_offset: 21 + bit_size: 1 + - name: I2C2SMEN + description: I2C2 clocks enable during Sleep and Stop modes + bit_offset: 22 + bit_size: 1 + - name: USBSMEN + description: USB device clocks enable during Sleep and Stop modes + bit_offset: 23 + bit_size: 1 + - name: FDCANSMEN + description: FDCAN clock enable during sleep mode + bit_offset: 25 + bit_size: 1 + - name: PWRSMEN + description: Power interface clocks enable during Sleep and Stop modes + bit_offset: 28 + bit_size: 1 + - name: I2C3SMEN + description: I2C3 clocks enable during Sleep and Stop modes + bit_offset: 30 + bit_size: 1 + - name: LPTIM1SMEN + description: Low Power Timer1 clock enable during sleep mode + bit_offset: 31 + bit_size: 1 +fieldset/APB1SMENR2: + description: APB1 peripheral clocks enable in Sleep and Stop modes register 2 + fields: + - name: LPUART1SMEN + description: Low power UART 1 clocks enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 + - name: I2C4SMEN + description: I2C4 clocks enable during Sleep and Stop modes + bit_offset: 1 + bit_size: 1 + - name: UCPD1SMEN + description: UCPD1 clocks enable during Sleep and Stop modes + bit_offset: 8 + bit_size: 1 +fieldset/APB2ENR: + description: APB2ENR + fields: + - name: SYSCFGEN + description: SYSCFG clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM1EN + description: TIM1 timer clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: SPI1 clock enable + bit_offset: 12 + bit_size: 1 + - name: TIM8EN + description: TIM8 timer clock enable + bit_offset: 13 + bit_size: 1 + - name: USART1EN + description: USART1clock enable + bit_offset: 14 + bit_size: 1 + - name: SPI4EN + description: SPI 4 clock enable + bit_offset: 15 + bit_size: 1 + - name: TIM15EN + description: TIM15 timer clock enable + bit_offset: 16 + bit_size: 1 + - name: TIM16EN + description: TIM16 timer clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: TIM17 timer clock enable + bit_offset: 18 + bit_size: 1 + - name: TIM20EN + description: Timer 20 clock enable + bit_offset: 20 + bit_size: 1 + - name: SAI1EN + description: SAI1 clock enable + bit_offset: 21 + bit_size: 1 + - name: HRTIM1EN + description: HRTIMER clock enable + bit_offset: 26 + bit_size: 1 +fieldset/APB2RSTR: + description: APB2 peripheral reset register + fields: + - name: SYSCFGRST + description: System configuration (SYSCFG) reset + bit_offset: 0 + bit_size: 1 + - name: TIM1RST + description: TIM1 timer reset + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: SPI1 reset + bit_offset: 12 + bit_size: 1 + - name: TIM8RST + description: TIM8 timer reset + bit_offset: 13 + bit_size: 1 + - name: USART1RST + description: USART1 reset + bit_offset: 14 + bit_size: 1 + - name: SPI4RST + description: SPI 4 reset + bit_offset: 15 + bit_size: 1 + - name: TIM15RST + description: TIM15 timer reset + bit_offset: 16 + bit_size: 1 + - name: TIM16RST + description: TIM16 timer reset + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: TIM17 timer reset + bit_offset: 18 + bit_size: 1 + - name: TIM20RST + description: Timer 20 reset + bit_offset: 20 + bit_size: 1 + - name: SAI1RST + description: Serial audio interface 1 (SAI1) reset + bit_offset: 21 + bit_size: 1 + - name: HRTIM1RST + description: HRTIMER reset + bit_offset: 26 + bit_size: 1 +fieldset/APB2SMENR: + description: APB2SMENR + fields: + - name: SYSCFGSMEN + description: SYSCFG clocks enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 + - name: TIM1SMEN + description: TIM1 timer clocks enable during Sleep and Stop modes + bit_offset: 11 + bit_size: 1 + - name: SPI1SMEN + description: SPI1 clocks enable during Sleep and Stop modes + bit_offset: 12 + bit_size: 1 + - name: TIM8SMEN + description: TIM8 timer clocks enable during Sleep and Stop modes + bit_offset: 13 + bit_size: 1 + - name: USART1SMEN + description: USART1clocks enable during Sleep and Stop modes + bit_offset: 14 + bit_size: 1 + - name: SPI4SMEN + description: SPI4 timer clocks enable during Sleep and Stop modes + bit_offset: 15 + bit_size: 1 + - name: TIM15SMEN + description: TIM15 timer clocks enable during Sleep and Stop modes + bit_offset: 16 + bit_size: 1 + - name: TIM16SMEN + description: TIM16 timer clocks enable during Sleep and Stop modes + bit_offset: 17 + bit_size: 1 + - name: TIM17SMEN + description: TIM17 timer clocks enable during Sleep and Stop modes + bit_offset: 18 + bit_size: 1 + - name: TIM20SMEN + description: Timer 20clock enable during sleep mode + bit_offset: 20 + bit_size: 1 + - name: SAI1SMEN + description: SAI1 clock enable during sleep mode + bit_offset: 21 + bit_size: 1 + - name: HRTIM1SMEN + description: HRTIMER clock enable during sleep mode + bit_offset: 26 + bit_size: 1 +fieldset/BDCR: + description: BDCR + fields: + - name: LSEON + description: LSE oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: LSE oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: LSE oscillator bypass + bit_offset: 2 + bit_size: 1 + - name: LSEDRV + description: SE oscillator drive capability + bit_offset: 3 + bit_size: 2 + - name: LSECSSON + description: LSECSSON + bit_offset: 5 + bit_size: 1 + - name: LSECSSD + description: LSECSSD + bit_offset: 6 + bit_size: 1 + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: RTC domain software reset + bit_offset: 16 + bit_size: 1 + - name: LSCOEN + description: Low speed clock output enable + bit_offset: 24 + bit_size: 1 + - name: LSCOSEL + description: Low speed clock output selection + bit_offset: 25 + bit_size: 1 +fieldset/CCIPR: + description: CCIPR + fields: + - name: USART1SEL + description: USART1 clock source selection + bit_offset: 0 + bit_size: 2 + - name: USART2SEL + description: USART2 clock source selection + bit_offset: 2 + bit_size: 2 + - name: USART3SEL + description: USART3 clock source selection + bit_offset: 4 + bit_size: 2 + - name: UART4SEL + description: UART4 clock source selection + bit_offset: 6 + bit_size: 2 + - name: UART5SEL + description: UART5 clock source selection + bit_offset: 8 + bit_size: 2 + - name: LPUART1SEL + description: LPUART1 clock source selection + bit_offset: 10 + bit_size: 2 + - name: I2C1SEL + description: I2C1 clock source selection + bit_offset: 12 + bit_size: 2 + - name: I2C2SEL + description: I2C2 clock source selection + bit_offset: 14 + bit_size: 2 + - name: I2C3SEL + description: I2C3 clock source selection + bit_offset: 16 + bit_size: 2 + - name: LPTIM1SEL + description: Low power timer 1 clock source selection + bit_offset: 18 + bit_size: 2 + - name: SAI1SEL + description: Low power timer 2 clock source selection + bit_offset: 20 + bit_size: 2 + - name: I2S23SEL + description: SAI1 clock source selection + bit_offset: 22 + bit_size: 2 + - name: FDCANSEL + description: SAI2 clock source selection + bit_offset: 24 + bit_size: 2 + - name: CLK48SEL + description: 48 MHz clock source selection + bit_offset: 26 + bit_size: 2 + - name: ADC12SEL + description: ADCs clock source selection + bit_offset: 28 + bit_size: 2 + - name: ADC345SEL + description: ADC3/4/5 clock source selection + bit_offset: 30 + bit_size: 2 +fieldset/CCIPR2: + description: Peripherals independent clock configuration register + fields: + - name: I2C4SEL + description: I2C4 clock source selection + bit_offset: 0 + bit_size: 2 + - name: QSPISEL + description: Octospi clock source selection + bit_offset: 20 + bit_size: 2 +fieldset/CFGR: + description: Clock configuration register + fields: + - name: SW + description: System clock switch + bit_offset: 0 + bit_size: 2 + - name: SWS + description: System clock switch status + bit_offset: 2 + bit_size: 2 + - name: HPRE + description: AHB prescaler + bit_offset: 4 + bit_size: 4 + - name: PPRE1 + description: PB low-speed prescaler (APB1) + bit_offset: 8 + bit_size: 3 + - name: PPRE2 + description: APB high-speed prescaler (APB2) + bit_offset: 11 + bit_size: 3 + - name: MCOSEL + description: Microcontroller clock output + bit_offset: 24 + bit_size: 4 + - name: MCOPRE + description: Microcontroller clock output prescaler + bit_offset: 28 + bit_size: 3 +fieldset/CICR: + description: Clock interrupt clear register + fields: + - name: LSIRDYC + description: LSI ready interrupt clear + bit_offset: 0 + bit_size: 1 + - name: LSERDYC + description: LSE ready interrupt clear + bit_offset: 1 + bit_size: 1 + - name: HSIRDYC + description: HSI ready interrupt clear + bit_offset: 3 + bit_size: 1 + - name: HSERDYC + description: HSE ready interrupt clear + bit_offset: 4 + bit_size: 1 + - name: PLLRDYC + description: PLL ready interrupt clear + bit_offset: 5 + bit_size: 1 + - name: CSSC + description: Clock security system interrupt clear + bit_offset: 8 + bit_size: 1 + - name: LSECSSC + description: LSE Clock security system interrupt clear + bit_offset: 9 + bit_size: 1 + - name: HSI48RDYC + description: HSI48 oscillator ready interrupt clear + bit_offset: 10 + bit_size: 1 +fieldset/CIER: + description: Clock interrupt enable register + fields: + - name: LSIRDYIE + description: LSI ready interrupt enable + bit_offset: 0 + bit_size: 1 + - name: LSERDYIE + description: LSE ready interrupt enable + bit_offset: 1 + bit_size: 1 + - name: HSIRDYIE + description: HSI ready interrupt enable + bit_offset: 3 + bit_size: 1 + - name: HSERDYIE + description: HSE ready interrupt enable + bit_offset: 4 + bit_size: 1 + - name: PLLRDYIE + description: PLL ready interrupt enable + bit_offset: 5 + bit_size: 1 + - name: LSECSSIE + description: LSE clock security system interrupt enable + bit_offset: 9 + bit_size: 1 + - name: HSI48RDYIE + description: HSI48 ready interrupt enable + bit_offset: 10 + bit_size: 1 +fieldset/CIFR: + description: Clock interrupt flag register + fields: + - name: LSIRDYF + description: LSI ready interrupt flag + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE ready interrupt flag + bit_offset: 1 + bit_size: 1 + - name: HSIRDYF + description: HSI ready interrupt flag + bit_offset: 3 + bit_size: 1 + - name: HSERDYF + description: HSE ready interrupt flag + bit_offset: 4 + bit_size: 1 + - name: PLLRDYF + description: PLL ready interrupt flag + bit_offset: 5 + bit_size: 1 + - name: CSSF + description: Clock security system interrupt flag + bit_offset: 8 + bit_size: 1 + - name: LSECSSF + description: LSE Clock security system interrupt flag + bit_offset: 9 + bit_size: 1 + - name: HSI48RDYF + description: HSI48 ready interrupt flag + bit_offset: 10 + bit_size: 1 +fieldset/CR: + description: Clock control register + fields: + - name: HSION + description: HSI clock enable + bit_offset: 8 + bit_size: 1 + - name: HSIKERON + description: HSI always enable for peripheral kernels + bit_offset: 9 + bit_size: 1 + - name: HSIRDY + description: HSI clock ready flag + bit_offset: 10 + bit_size: 1 + - name: HSEON + description: HSE clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: HSE clock ready flag + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: HSE crystal oscillator bypass + bit_offset: 18 + bit_size: 1 + - name: CSSON + description: Clock security system enable + bit_offset: 19 + bit_size: 1 + - name: PLLON + description: Main PLL enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: Main PLL clock ready flag + bit_offset: 25 + bit_size: 1 +fieldset/CRRCR: + description: Clock recovery RC register + fields: + - name: HSI48ON + description: HSI48 clock enable + bit_offset: 0 + bit_size: 1 + - name: HSI48RDY + description: HSI48 clock ready flag + bit_offset: 1 + bit_size: 1 + - name: HSI48CAL + description: HSI48 clock calibration + bit_offset: 7 + bit_size: 9 +fieldset/CSR: + description: CSR + fields: + - name: LSION + description: LSI oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: LSI oscillator ready + bit_offset: 1 + bit_size: 1 + - name: RMVF + description: Remove reset flag + bit_offset: 23 + bit_size: 1 + - name: OBLRSTF + description: Option byte loader reset flag + bit_offset: 25 + bit_size: 1 + - name: PINRSTF + description: Pad reset flag + bit_offset: 26 + bit_size: 1 + - name: BORRSTF + description: BOR flag + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: Independent window watchdog reset flag + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + - name: LPWRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 +fieldset/ICSCR: + description: Internal clock sources calibration register + fields: + - name: HSICAL0 + description: Internal High Speed clock Calibration + bit_offset: 16 + bit_size: 8 + - name: HSITRIM + description: Internal High Speed clock trimming + bit_offset: 24 + bit_size: 7 +fieldset/PLLCFGR: + description: PLL configuration register + fields: + - name: PLLSRC + description: "Main PLL, PLLSAI1 and PLLSAI2 entry clock source" + bit_offset: 0 + bit_size: 2 + - name: PLLM + description: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock + bit_offset: 4 + bit_size: 4 + - name: PLLN + description: Main PLL multiplication factor for VCO + bit_offset: 8 + bit_size: 7 + - name: PLLPEN + description: Main PLL PLLSAI3CLK output enable + bit_offset: 16 + bit_size: 1 + - name: PLLP + description: Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) + bit_offset: 17 + bit_size: 1 + - name: PLLQEN + description: Main PLL PLLUSB1CLK output enable + bit_offset: 20 + bit_size: 1 + - name: PLLQ + description: Main PLL division factor for PLLUSB1CLK(48 MHz clock) + bit_offset: 21 + bit_size: 2 + - name: PLLREN + description: Main PLL PLLCLK output enable + bit_offset: 24 + bit_size: 1 + - name: PLLR + description: Main PLL division factor for PLLCLK (system clock) + bit_offset: 25 + bit_size: 2 + - name: PLLPDIV + description: Main PLL division factor for PLLSAI2CLK + bit_offset: 27 + bit_size: 5 diff --git a/data/registers/rcc_l1.yaml b/data/registers/rcc_l1.yaml new file mode 100644 index 0000000..31fe080 --- /dev/null +++ b/data/registers/rcc_l1.yaml @@ -0,0 +1,1271 @@ +--- +block/RCC: + description: Reset and clock control + items: + - name: CR + description: Clock control register + byte_offset: 0 + fieldset: CR + - name: ICSCR + description: Internal clock sources calibration register + byte_offset: 4 + fieldset: ICSCR + - name: CFGR + description: Clock configuration register + byte_offset: 8 + fieldset: CFGR + - name: CIR + description: Clock interrupt register + byte_offset: 12 + fieldset: CIR + - name: AHBRSTR + description: AHB peripheral reset register + byte_offset: 16 + fieldset: AHBRSTR + - name: APB2RSTR + description: APB2 peripheral reset register + byte_offset: 20 + fieldset: APB2RSTR + - name: APB1RSTR + description: APB1 peripheral reset register + byte_offset: 24 + fieldset: APB1RSTR + - name: AHBENR + description: AHB peripheral clock enable register + byte_offset: 28 + fieldset: AHBENR + - name: APB2ENR + description: APB2 peripheral clock enable register + byte_offset: 32 + fieldset: APB2ENR + - name: APB1ENR + description: APB1 peripheral clock enable register + byte_offset: 36 + fieldset: APB1ENR + - name: AHBLPENR + description: AHB peripheral clock enable in low power mode register + byte_offset: 40 + fieldset: AHBLPENR + - name: APB2LPENR + description: APB2 peripheral clock enable in low power mode register + byte_offset: 44 + fieldset: APB2LPENR + - name: APB1LPENR + description: APB1 peripheral clock enable in low power mode register + byte_offset: 48 + fieldset: APB1LPENR + - name: CSR + description: Control/status register + byte_offset: 52 + fieldset: CSR +fieldset/AHBENR: + description: AHB peripheral clock enable register + fields: + - name: GPIOPAEN + description: IO port A clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOPBEN + description: IO port B clock enable + bit_offset: 1 + bit_size: 1 + - name: GPIOPCEN + description: IO port C clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIOPDEN + description: IO port D clock enable + bit_offset: 3 + bit_size: 1 + - name: GPIOPEEN + description: IO port E clock enable + bit_offset: 4 + bit_size: 1 + - name: GPIOPHEN + description: IO port H clock enable + bit_offset: 5 + bit_size: 1 + - name: GPIOPFEN + description: IO port F clock enable + bit_offset: 6 + bit_size: 1 + - name: GPIOPGEN + description: IO port G clock enable + bit_offset: 7 + bit_size: 1 + - name: CRCEN + description: CRC clock enable + bit_offset: 12 + bit_size: 1 + - name: FLITFEN + description: FLITF clock enable + bit_offset: 15 + bit_size: 1 + - name: DMA1EN + description: DMA1 clock enable + bit_offset: 24 + bit_size: 1 + - name: DMA2EN + description: DMA2 clock enable + bit_offset: 25 + bit_size: 1 + - name: FSMCEN + description: FSMCEN + bit_offset: 30 + bit_size: 1 +fieldset/AHBLPENR: + description: AHB peripheral clock enable in low power mode register + fields: + - name: GPIOALPEN + description: IO port A clock enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: GPIOBLPEN + description: IO port B clock enable during Sleep mode + bit_offset: 1 + bit_size: 1 + - name: GPIOCLPEN + description: IO port C clock enable during Sleep mode + bit_offset: 2 + bit_size: 1 + - name: GPIODLPEN + description: IO port D clock enable during Sleep mode + bit_offset: 3 + bit_size: 1 + - name: GPIOELPEN + description: IO port E clock enable during Sleep mode + bit_offset: 4 + bit_size: 1 + - name: GPIOHLPEN + description: IO port H clock enable during Sleep mode + bit_offset: 5 + bit_size: 1 + - name: GPIOFLPEN + description: IO port F clock enable during Sleep mode + bit_offset: 6 + bit_size: 1 + - name: GPIOGLPEN + description: IO port G clock enable during Sleep mode + bit_offset: 7 + bit_size: 1 + - name: CRCLPEN + description: CRC clock enable during Sleep mode + bit_offset: 12 + bit_size: 1 + - name: FLITFLPEN + description: FLITF clock enable during Sleep mode + bit_offset: 15 + bit_size: 1 + - name: SRAMLPEN + description: SRAM clock enable during Sleep mode + bit_offset: 16 + bit_size: 1 + - name: DMA1LPEN + description: DMA1 clock enable during Sleep mode + bit_offset: 24 + bit_size: 1 + - name: DMA2LPEN + description: DMA2 clock enable during Sleep mode + bit_offset: 25 + bit_size: 1 + - name: AESLPEN + description: AES clock enable during Sleep mode + bit_offset: 27 + bit_size: 1 + - name: FSMCLPEN + description: FSMC clock enable during Sleep mode + bit_offset: 30 + bit_size: 1 +fieldset/AHBRSTR: + description: AHB peripheral reset register + fields: + - name: GPIOARST + description: IO port A reset + bit_offset: 0 + bit_size: 1 + enum_write: FSMCRSTW + - name: GPIOBRST + description: IO port B reset + bit_offset: 1 + bit_size: 1 + enum_write: FSMCRSTW + - name: GPIOCRST + description: IO port C reset + bit_offset: 2 + bit_size: 1 + enum_write: FSMCRSTW + - name: GPIODRST + description: IO port D reset + bit_offset: 3 + bit_size: 1 + enum_write: FSMCRSTW + - name: GPIOERST + description: IO port E reset + bit_offset: 4 + bit_size: 1 + enum_write: FSMCRSTW + - name: GPIOHRST + description: IO port H reset + bit_offset: 5 + bit_size: 1 + enum_write: FSMCRSTW + - name: GPIOFRST + description: IO port F reset + bit_offset: 6 + bit_size: 1 + enum_write: FSMCRSTW + - name: GPIOGRST + description: IO port G reset + bit_offset: 7 + bit_size: 1 + enum_write: FSMCRSTW + - name: CRCRST + description: CRC reset + bit_offset: 12 + bit_size: 1 + enum_write: FSMCRSTW + - name: FLITFRST + description: FLITF reset + bit_offset: 15 + bit_size: 1 + enum_write: FSMCRSTW + - name: DMA1RST + description: DMA1 reset + bit_offset: 24 + bit_size: 1 + enum_write: FSMCRSTW + - name: DMA2RST + description: DMA2 reset + bit_offset: 25 + bit_size: 1 + enum_write: FSMCRSTW + - name: FSMCRST + description: FSMC reset + bit_offset: 30 + bit_size: 1 + enum_write: FSMCRSTW +fieldset/APB1ENR: + description: APB1 peripheral clock enable register + fields: + - name: TIM2EN + description: Timer 2 clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: Timer 3 clock enable + bit_offset: 1 + bit_size: 1 + - name: TIM4EN + description: Timer 4 clock enable + bit_offset: 2 + bit_size: 1 + - name: TIM5EN + description: Timer 5 clock enable + bit_offset: 3 + bit_size: 1 + - name: TIM6EN + description: Timer 6 clock enable + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: Timer 7 clock enable + bit_offset: 5 + bit_size: 1 + - name: LCDEN + description: LCD clock enable + bit_offset: 9 + bit_size: 1 + - name: WWDGEN + description: Window watchdog clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI 2 clock enable + bit_offset: 14 + bit_size: 1 + - name: SPI3EN + description: SPI 3 clock enable + bit_offset: 15 + bit_size: 1 + - name: USART2EN + description: USART 2 clock enable + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: USART 3 clock enable + bit_offset: 18 + bit_size: 1 + - name: USART4EN + description: UART 4 clock enable + bit_offset: 19 + bit_size: 1 + - name: USART5EN + description: UART 5 clock enable + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: I2C 1 clock enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C 2 clock enable + bit_offset: 22 + bit_size: 1 + - name: USBEN + description: USB clock enable + bit_offset: 23 + bit_size: 1 + - name: PWREN + description: Power interface clock enable + bit_offset: 28 + bit_size: 1 + - name: DACEN + description: DAC interface clock enable + bit_offset: 29 + bit_size: 1 + - name: COMPEN + description: COMP interface clock enable + bit_offset: 31 + bit_size: 1 +fieldset/APB1LPENR: + description: APB1 peripheral clock enable in low power mode register + fields: + - name: TIM2LPEN + description: Timer 2 clock enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: TIM3LPEN + description: Timer 3 clock enable during Sleep mode + bit_offset: 1 + bit_size: 1 + - name: TIM4LPEN + description: Timer 4 clock enable during Sleep mode + bit_offset: 2 + bit_size: 1 + - name: TIM5LPEN + description: Timer 5 clock enable during Sleep mode + bit_offset: 3 + bit_size: 1 + - name: TIM6LPEN + description: Timer 6 clock enable during Sleep mode + bit_offset: 4 + bit_size: 1 + - name: TIM7LPEN + description: Timer 7 clock enable during Sleep mode + bit_offset: 5 + bit_size: 1 + - name: LCDLPEN + description: LCD clock enable during Sleep mode + bit_offset: 9 + bit_size: 1 + - name: WWDGLPEN + description: Window watchdog clock enable during Sleep mode + bit_offset: 11 + bit_size: 1 + - name: SPI2LPEN + description: SPI 2 clock enable during Sleep mode + bit_offset: 14 + bit_size: 1 + - name: SPI3LPEN + description: SPI 3 clock enable during Sleep mode + bit_offset: 15 + bit_size: 1 + - name: USART2LPEN + description: USART 2 clock enable during Sleep mode + bit_offset: 17 + bit_size: 1 + - name: USART3LPEN + description: USART 3 clock enable during Sleep mode + bit_offset: 18 + bit_size: 1 + - name: UART4LPEN + description: USART 4 clock enable during Sleep mode + bit_offset: 19 + bit_size: 1 + - name: UART5LPEN + description: USART 5 clock enable during Sleep mode + bit_offset: 20 + bit_size: 1 + - name: I2C1LPEN + description: I2C 1 clock enable during Sleep mode + bit_offset: 21 + bit_size: 1 + - name: I2C2LPEN + description: I2C 2 clock enable during Sleep mode + bit_offset: 22 + bit_size: 1 + - name: USBLPEN + description: USB clock enable during Sleep mode + bit_offset: 23 + bit_size: 1 + - name: PWRLPEN + description: Power interface clock enable during Sleep mode + bit_offset: 28 + bit_size: 1 + - name: DACLPEN + description: DAC interface clock enable during Sleep mode + bit_offset: 29 + bit_size: 1 + - name: COMPLPEN + description: COMP interface clock enable during Sleep mode + bit_offset: 31 + bit_size: 1 +fieldset/APB1RSTR: + description: APB1 peripheral reset register + fields: + - name: TIM2RST + description: Timer 2 reset + bit_offset: 0 + bit_size: 1 + enum_write: COMPRSTW + - name: TIM3RST + description: Timer 3 reset + bit_offset: 1 + bit_size: 1 + enum_write: COMPRSTW + - name: TIM4RST + description: Timer 4 reset + bit_offset: 2 + bit_size: 1 + enum_write: COMPRSTW + - name: TIM5RST + description: Timer 5 reset + bit_offset: 3 + bit_size: 1 + enum_write: COMPRSTW + - name: TIM6RST + description: Timer 6reset + bit_offset: 4 + bit_size: 1 + enum_write: COMPRSTW + - name: TIM7RST + description: Timer 7 reset + bit_offset: 5 + bit_size: 1 + enum_write: COMPRSTW + - name: LCDRST + description: LCD reset + bit_offset: 9 + bit_size: 1 + enum_write: COMPRSTW + - name: WWDRST + description: Window watchdog reset + bit_offset: 11 + bit_size: 1 + enum_write: COMPRSTW + - name: SPI2RST + description: SPI 2 reset + bit_offset: 14 + bit_size: 1 + enum_write: COMPRSTW + - name: SPI3RST + description: SPI 3 reset + bit_offset: 15 + bit_size: 1 + enum_write: COMPRSTW + - name: USART2RST + description: USART 2 reset + bit_offset: 17 + bit_size: 1 + enum_write: COMPRSTW + - name: USART3RST + description: USART 3 reset + bit_offset: 18 + bit_size: 1 + enum_write: COMPRSTW + - name: UART4RST + description: UART 4 reset + bit_offset: 19 + bit_size: 1 + enum_write: COMPRSTW + - name: UART5RST + description: UART 5 reset + bit_offset: 20 + bit_size: 1 + enum_write: COMPRSTW + - name: I2C1RST + description: I2C 1 reset + bit_offset: 21 + bit_size: 1 + enum_write: COMPRSTW + - name: I2C2RST + description: I2C 2 reset + bit_offset: 22 + bit_size: 1 + enum_write: COMPRSTW + - name: USBRST + description: USB reset + bit_offset: 23 + bit_size: 1 + enum_write: COMPRSTW + - name: PWRRST + description: Power interface reset + bit_offset: 28 + bit_size: 1 + enum_write: COMPRSTW + - name: DACRST + description: DAC interface reset + bit_offset: 29 + bit_size: 1 + enum_write: COMPRSTW + - name: COMPRST + description: COMP interface reset + bit_offset: 31 + bit_size: 1 + enum_write: COMPRSTW +fieldset/APB2ENR: + description: APB2 peripheral clock enable register + fields: + - name: SYSCFGEN + description: System configuration controller clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM9EN + description: TIM9 timer clock enable + bit_offset: 2 + bit_size: 1 + - name: TIM10EN + description: TIM10 timer clock enable + bit_offset: 3 + bit_size: 1 + - name: TIM11EN + description: TIM11 timer clock enable + bit_offset: 4 + bit_size: 1 + - name: ADC1EN + description: ADC1 interface clock enable + bit_offset: 9 + bit_size: 1 + - name: SDIOEN + description: SDIO clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: SPI 1 clock enable + bit_offset: 12 + bit_size: 1 + - name: USART1EN + description: USART1 clock enable + bit_offset: 14 + bit_size: 1 +fieldset/APB2LPENR: + description: APB2 peripheral clock enable in low power mode register + fields: + - name: SYSCFGLPEN + description: System configuration controller clock enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: TIM9LPEN + description: TIM9 timer clock enable during Sleep mode + bit_offset: 2 + bit_size: 1 + - name: TIM10LPEN + description: TIM10 timer clock enable during Sleep mode + bit_offset: 3 + bit_size: 1 + - name: TIM11LPEN + description: TIM11 timer clock enable during Sleep mode + bit_offset: 4 + bit_size: 1 + - name: ADC1LPEN + description: ADC1 interface clock enable during Sleep mode + bit_offset: 9 + bit_size: 1 + - name: SDIOLPEN + description: SDIO clock enable during Sleep mode + bit_offset: 11 + bit_size: 1 + - name: SPI1LPEN + description: SPI 1 clock enable during Sleep mode + bit_offset: 12 + bit_size: 1 + - name: USART1LPEN + description: USART1 clock enable during Sleep mode + bit_offset: 14 + bit_size: 1 +fieldset/APB2RSTR: + description: APB2 peripheral reset register + fields: + - name: SYSCFGRST + description: SYSCFGRST + bit_offset: 0 + bit_size: 1 + enum_write: USARTRSTW + - name: TIM9RST + description: TIM9RST + bit_offset: 2 + bit_size: 1 + enum_write: USARTRSTW + - name: TM10RST + description: TM10RST + bit_offset: 3 + bit_size: 1 + enum_write: USARTRSTW + - name: TM11RST + description: TM11RST + bit_offset: 4 + bit_size: 1 + enum_write: USARTRSTW + - name: ADC1RST + description: ADC1RST + bit_offset: 9 + bit_size: 1 + enum_write: USARTRSTW + - name: SDIORST + description: SDIORST + bit_offset: 11 + bit_size: 1 + enum_write: USARTRSTW + - name: SPI1RST + description: SPI1RST + bit_offset: 12 + bit_size: 1 + enum_write: USARTRSTW + - name: USART1RST + description: USART1RST + bit_offset: 14 + bit_size: 1 + enum_write: USARTRSTW +fieldset/CFGR: + description: Clock configuration register + fields: + - name: SW + description: System clock switch + bit_offset: 0 + bit_size: 2 + enum: SW + - name: SWS + description: System clock switch status + bit_offset: 2 + bit_size: 2 + enum_read: SWSR + - name: HPRE + description: AHB prescaler + bit_offset: 4 + bit_size: 4 + enum: HPRE + - name: PPRE1 + description: APB low-speed prescaler (APB1) + bit_offset: 8 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: APB high-speed prescaler (APB2) + bit_offset: 11 + bit_size: 3 + enum: PPRE + - name: PLLSRC + description: PLL entry clock source + bit_offset: 16 + bit_size: 1 + enum: PLLSRC + - name: PLLMUL + description: PLL multiplication factor + bit_offset: 18 + bit_size: 4 + enum: PLLMUL + - name: PLLDIV + description: PLL output division + bit_offset: 22 + bit_size: 2 + enum: PLLDIV + - name: MCOSEL + description: Microcontroller clock output selection + bit_offset: 24 + bit_size: 3 + enum: MCOSEL + - name: MCOPRE + description: Microcontroller clock output prescaler + bit_offset: 28 + bit_size: 3 + enum: MCOPRE +fieldset/CIR: + description: Clock interrupt register + fields: + - name: LSIRDYF + description: LSI ready interrupt flag + bit_offset: 0 + bit_size: 1 + enum_read: MSIRDYFR + - name: LSERDYF + description: LSE ready interrupt flag + bit_offset: 1 + bit_size: 1 + enum_read: MSIRDYFR + - name: HSIRDYF + description: HSI ready interrupt flag + bit_offset: 2 + bit_size: 1 + enum_read: MSIRDYFR + - name: HSERDYF + description: HSE ready interrupt flag + bit_offset: 3 + bit_size: 1 + enum_read: MSIRDYFR + - name: PLLRDYF + description: PLL ready interrupt flag + bit_offset: 4 + bit_size: 1 + enum_read: MSIRDYFR + - name: MSIRDYF + description: MSI ready interrupt flag + bit_offset: 5 + bit_size: 1 + enum_read: MSIRDYFR + - name: LSECSSF + description: LSE Clock security system interrupt flag + bit_offset: 6 + bit_size: 1 + enum_read: LSECSSFR + - name: CSSF + description: Clock security system interrupt flag + bit_offset: 7 + bit_size: 1 + enum_read: CSSFR + - name: LSIRDYIE + description: LSI ready interrupt enable + bit_offset: 8 + bit_size: 1 + enum: MSIRDYIE + - name: LSERDYIE + description: LSE ready interrupt enable + bit_offset: 9 + bit_size: 1 + enum: MSIRDYIE + - name: HSIRDYIE + description: HSI ready interrupt enable + bit_offset: 10 + bit_size: 1 + enum: MSIRDYIE + - name: HSERDYIE + description: HSE ready interrupt enable + bit_offset: 11 + bit_size: 1 + enum: MSIRDYIE + - name: PLLRDYIE + description: PLL ready interrupt enable + bit_offset: 12 + bit_size: 1 + enum: MSIRDYIE + - name: MSIRDYIE + description: MSI ready interrupt enable + bit_offset: 13 + bit_size: 1 + enum: MSIRDYIE + - name: LSECSSIE + description: LSE clock security system interrupt enable + bit_offset: 14 + bit_size: 1 + enum: LSECSSIE + - name: LSIRDYC + description: LSI ready interrupt clear + bit_offset: 16 + bit_size: 1 + enum_write: MSIRDYCW + - name: LSERDYC + description: LSE ready interrupt clear + bit_offset: 17 + bit_size: 1 + enum_write: MSIRDYCW + - name: HSIRDYC + description: HSI ready interrupt clear + bit_offset: 18 + bit_size: 1 + enum_write: MSIRDYCW + - name: HSERDYC + description: HSE ready interrupt clear + bit_offset: 19 + bit_size: 1 + enum_write: MSIRDYCW + - name: PLLRDYC + description: PLL ready interrupt clear + bit_offset: 20 + bit_size: 1 + enum_write: MSIRDYCW + - name: MSIRDYC + description: MSI ready interrupt clear + bit_offset: 21 + bit_size: 1 + enum_write: MSIRDYCW + - name: LSECSSC + description: LSE Clock security system interrupt clear + bit_offset: 22 + bit_size: 1 + enum_write: CSSCW + - name: CSSC + description: Clock security system interrupt clear + bit_offset: 23 + bit_size: 1 + enum_write: CSSCW +fieldset/CR: + description: Clock control register + fields: + - name: HSION + description: Internal high-speed clock enable + bit_offset: 0 + bit_size: 1 + - name: HSIRDY + description: Internal high-speed clock ready flag + bit_offset: 1 + bit_size: 1 + enum_read: HSERDYR + - name: MSION + description: MSI clock enable + bit_offset: 8 + bit_size: 1 + - name: MSIRDY + description: MSI clock ready flag + bit_offset: 9 + bit_size: 1 + enum_read: HSERDYR + - name: HSEON + description: HSE clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: HSE clock ready flag + bit_offset: 17 + bit_size: 1 + enum_read: HSERDYR + - name: HSEBYP + description: HSE clock bypass + bit_offset: 18 + bit_size: 1 + enum: HSEBYP + - name: PLLON + description: PLL enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: PLL clock ready flag + bit_offset: 25 + bit_size: 1 + enum_read: PLLRDYR + - name: CSSON + description: Clock security system enable + bit_offset: 28 + bit_size: 1 + - name: RTCPRE + description: TC/LCD prescaler + bit_offset: 29 + bit_size: 2 + enum: RTCPRE +fieldset/CSR: + description: Control/status register + fields: + - name: LSION + description: Internal low-speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: Internal low-speed oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSEON + description: External low-speed oscillator enable + bit_offset: 8 + bit_size: 1 + - name: LSERDY + description: External low-speed oscillator ready + bit_offset: 9 + bit_size: 1 + - name: LSEBYP + description: External low-speed oscillator bypass + bit_offset: 10 + bit_size: 1 + - name: LSECSSON + description: CSS on LSE enable + bit_offset: 11 + bit_size: 1 + - name: LSECSSD + description: CSS on LSE failure Detection + bit_offset: 12 + bit_size: 1 + - name: RTCSEL + description: RTC and LCD clock source selection + bit_offset: 16 + bit_size: 2 + - name: RTCEN + description: RTC clock enable + bit_offset: 22 + bit_size: 1 + - name: RTCRST + description: RTC software reset + bit_offset: 23 + bit_size: 1 + enum_write: RTCRSTW + - name: RMVF + description: Remove reset flag + bit_offset: 24 + bit_size: 1 + enum_write: RMVFW + - name: OBLRSTF + description: Options bytes loading reset flag + bit_offset: 25 + bit_size: 1 + enum_read: LPWRSTFR + - name: PINRSTF + description: PIN reset flag + bit_offset: 26 + bit_size: 1 + enum_read: LPWRSTFR + - name: PORRSTF + description: POR/PDR reset flag + bit_offset: 27 + bit_size: 1 + enum_read: LPWRSTFR + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + enum_read: LPWRSTFR + - name: IWDGRSTF + description: Independent watchdog reset flag + bit_offset: 29 + bit_size: 1 + enum_read: LPWRSTFR + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + enum_read: LPWRSTFR + - name: LPWRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 + enum_read: LPWRSTFR +fieldset/ICSCR: + description: Internal clock sources calibration register + fields: + - name: HSICAL + description: nternal high speed clock calibration + bit_offset: 0 + bit_size: 8 + - name: HSITRIM + description: High speed internal clock trimming + bit_offset: 8 + bit_size: 5 + - name: MSIRANGE + description: MSI clock ranges + bit_offset: 13 + bit_size: 3 + - name: MSICAL + description: MSI clock calibration + bit_offset: 16 + bit_size: 8 + - name: MSITRIM + description: MSI clock trimming + bit_offset: 24 + bit_size: 8 +enum/COMPRSTW: + bit_size: 1 + variants: + - name: Reset + description: Reset the module + value: 1 +enum/CSSCW: + bit_size: 1 + variants: + - name: Clear + description: Clear interrupt + value: 1 +enum/CSSFR: + bit_size: 1 + variants: + - name: NotInterupted + description: No clock security interrupt caused by HSE clock failure + value: 0 + - name: Interupted + description: Clock security interrupt caused by HSE clock failure + value: 1 +enum/FSMCRSTW: + bit_size: 1 + variants: + - name: Reset + description: Reset the module + value: 1 +enum/HPRE: + bit_size: 4 + variants: + - name: Div1 + description: system clock not divided + value: 0 + - name: Div2 + description: system clock divided by 2 + value: 8 + - name: Div4 + description: system clock divided by 4 + value: 9 + - name: Div8 + description: system clock divided by 8 + value: 10 + - name: Div16 + description: system clock divided by 16 + value: 11 + - name: Div64 + description: system clock divided by 64 + value: 12 + - name: Div128 + description: system clock divided by 128 + value: 13 + - name: Div256 + description: system clock divided by 256 + value: 14 + - name: Div512 + description: system clock divided by 512 + value: 15 +enum/HSEBYP: + bit_size: 1 + variants: + - name: NotBypassed + description: HSE oscillator not bypassed + value: 0 + - name: Bypassed + description: HSE oscillator bypassed + value: 1 +enum/HSERDYR: + bit_size: 1 + variants: + - name: NotReady + description: Oscillator is not stable + value: 0 + - name: Ready + description: Oscillator is stable + value: 1 +enum/LPWRSTFR: + bit_size: 1 + variants: + - name: NoReset + description: No reset has occured + value: 0 + - name: Reset + description: A reset has occured + value: 1 +enum/LSECSSFR: + bit_size: 1 + variants: + - name: NoFailure + description: No failure detected on the external 32 KHz oscillator + value: 0 + - name: Failure + description: A failure is detected on the external 32 kHz oscillator + value: 1 +enum/LSECSSIE: + bit_size: 1 + variants: + - name: Disabled + description: LSE CSS interrupt disabled + value: 0 + - name: Enabled + description: LSE CSS interrupt enabled + value: 1 +enum/MCOPRE: + bit_size: 3 + variants: + - name: Div1 + description: No division + value: 0 + - name: Div2 + description: Division by 2 + value: 1 + - name: Div4 + description: Division by 4 + value: 2 + - name: Div8 + description: Division by 8 + value: 3 + - name: Div16 + description: Division by 16 + value: 4 +enum/MCOSEL: + bit_size: 3 + variants: + - name: NoClock + description: No clock + value: 0 + - name: SYSCLK + description: SYSCLK clock selected + value: 1 + - name: HSI + description: HSI oscillator clock selected + value: 2 + - name: MSI + description: MSI oscillator clock selected + value: 3 + - name: HSE + description: HSE oscillator clock selected + value: 4 + - name: PLL + description: PLL clock selected + value: 5 + - name: LSI + description: LSI oscillator clock selected + value: 6 + - name: LSE + description: LSE oscillator clock selected + value: 7 +enum/MSIRDYCW: + bit_size: 1 + variants: + - name: Clear + description: Clear interrupt + value: 1 +enum/MSIRDYFR: + bit_size: 1 + variants: + - name: NotStable + description: Clock is not stable + value: 0 + - name: Stable + description: Clock is stable + value: 1 +enum/MSIRDYIE: + bit_size: 1 + variants: + - name: Disabled + description: Interrupt disabled + value: 0 + - name: Enabled + description: Interrupt enabled + value: 1 +enum/PLLDIV: + bit_size: 2 + variants: + - name: Div2 + description: PLLVCO / 2 + value: 1 + - name: Div3 + description: PLLVCO / 3 + value: 2 + - name: Div4 + description: PLLVCO / 4 + value: 3 +enum/PLLMUL: + bit_size: 4 + variants: + - name: Mul3 + description: PLL clock entry x 3 + value: 0 + - name: Mul4 + description: PLL clock entry x 4 + value: 1 + - name: Mul6 + description: PLL clock entry x 6 + value: 2 + - name: Mul8 + description: PLL clock entry x 8 + value: 3 + - name: Mul12 + description: PLL clock entry x 12 + value: 4 + - name: Mul16 + description: PLL clock entry x 16 + value: 5 + - name: Mul24 + description: PLL clock entry x 24 + value: 6 + - name: Mul32 + description: PLL clock entry x 32 + value: 7 + - name: Mul48 + description: PLL clock entry x 48 + value: 8 +enum/PLLRDYR: + bit_size: 1 + variants: + - name: Unlocked + description: PLL unlocked + value: 0 + - name: Locked + description: PLL locked + value: 1 +enum/PLLSRC: + bit_size: 1 + variants: + - name: HSI + description: HSI selected as PLL input clock + value: 0 + - name: HSE + description: HSE selected as PLL input clock + value: 1 +enum/PPRE: + bit_size: 3 + variants: + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 +enum/RMVFW: + bit_size: 1 + variants: + - name: Clear + description: Clears the reset flag + value: 1 +enum/RTCPRE: + bit_size: 2 + variants: + - name: Div2 + description: HSE divided by 2 + value: 0 + - name: Div4 + description: HSE divided by 4 + value: 1 + - name: Div8 + description: HSE divided by 8 + value: 2 + - name: Div16 + description: HSE divided by 16 + value: 3 +enum/RTCRSTW: + bit_size: 1 + variants: + - name: Reset + description: Resets the RTC peripheral + value: 1 +enum/SW: + bit_size: 2 + variants: + - name: HSI + description: MSI oscillator used as system clock + value: 0 + - name: MSI + description: HSI oscillator used as system clock + value: 1 + - name: HSE + description: HSE oscillator used as system clock + value: 2 + - name: PLL + description: PLL used as system clock + value: 3 +enum/SWSR: + bit_size: 2 + variants: + - name: HSI + description: MSI oscillator used as system clock + value: 0 + - name: MSI + description: HSI oscillator used as system clock + value: 1 + - name: HSE + description: HSE oscillator used as system clock + value: 2 + - name: PLL + description: PLL used as system clock + value: 3 +enum/USARTRSTW: + bit_size: 1 + variants: + - name: Reset + description: Reset the module + value: 1 diff --git a/data/registers/rcc_l5.yaml b/data/registers/rcc_l5.yaml new file mode 100644 index 0000000..b8404c1 --- /dev/null +++ b/data/registers/rcc_l5.yaml @@ -0,0 +1,2259 @@ +--- +block/RCC: + description: Reset and clock control + items: + - name: CR + description: Clock control register + byte_offset: 0 + fieldset: CR + - name: ICSCR + description: " Internal clock sources calibration register " + byte_offset: 4 + fieldset: ICSCR + - name: CFGR + description: Clock configuration register + byte_offset: 8 + fieldset: CFGR + - name: PLLCFGR + description: PLL configuration register + byte_offset: 12 + fieldset: PLLCFGR + - name: PLLSAI1CFGR + description: PLLSAI1 configuration register + byte_offset: 16 + fieldset: PLLSAI1CFGR + - name: PLLSAI2CFGR + description: PLLSAI2 configuration register + byte_offset: 20 + fieldset: PLLSAI2CFGR + - name: CIER + description: " Clock interrupt enable register " + byte_offset: 24 + fieldset: CIER + - name: CIFR + description: Clock interrupt flag register + byte_offset: 28 + access: Read + fieldset: CIFR + - name: CICR + description: Clock interrupt clear register + byte_offset: 32 + access: Write + fieldset: CICR + - name: AHB1RSTR + description: AHB1 peripheral reset register + byte_offset: 40 + fieldset: AHB1RSTR + - name: AHB2RSTR + description: AHB2 peripheral reset register + byte_offset: 44 + fieldset: AHB2RSTR + - name: AHB3RSTR + description: AHB3 peripheral reset register + byte_offset: 48 + fieldset: AHB3RSTR + - name: APB1RSTR1 + description: " APB1 peripheral reset register 1 " + byte_offset: 56 + fieldset: APB1RSTR1 + - name: APB1RSTR2 + description: " APB1 peripheral reset register 2 " + byte_offset: 60 + fieldset: APB1RSTR2 + - name: APB2RSTR + description: APB2 peripheral reset register + byte_offset: 64 + fieldset: APB2RSTR + - name: AHB1ENR + description: " AHB1 peripheral clock enable register " + byte_offset: 72 + fieldset: AHB1ENR + - name: AHB2ENR + description: " AHB2 peripheral clock enable register " + byte_offset: 76 + fieldset: AHB2ENR + - name: AHB3ENR + description: " AHB3 peripheral clock enable register " + byte_offset: 80 + fieldset: AHB3ENR + - name: APB1ENR1 + description: APB1ENR1 + byte_offset: 88 + fieldset: APB1ENR1 + - name: APB1ENR2 + description: " APB1 peripheral clock enable register 2 " + byte_offset: 92 + fieldset: APB1ENR2 + - name: APB2ENR + description: APB2ENR + byte_offset: 96 + fieldset: APB2ENR + - name: AHB1SMENR + description: " AHB1 peripheral clocks enable in Sleep and Stop modes register " + byte_offset: 104 + fieldset: AHB1SMENR + - name: AHB2SMENR + description: " AHB2 peripheral clocks enable in Sleep and Stop modes register " + byte_offset: 108 + fieldset: AHB2SMENR + - name: AHB3SMENR + description: " AHB3 peripheral clocks enable in Sleep and Stop modes register " + byte_offset: 112 + fieldset: AHB3SMENR + - name: APB1SMENR1 + description: APB1SMENR1 + byte_offset: 120 + fieldset: APB1SMENR1 + - name: APB1SMENR2 + description: " APB1 peripheral clocks enable in Sleep and Stop modes register 2 " + byte_offset: 124 + fieldset: APB1SMENR2 + - name: APB2SMENR + description: APB2SMENR + byte_offset: 128 + fieldset: APB2SMENR + - name: CCIPR1 + description: CCIPR1 + byte_offset: 136 + fieldset: CCIPR1 + - name: BDCR + description: BDCR + byte_offset: 144 + fieldset: BDCR + - name: CSR + description: CSR + byte_offset: 148 + fieldset: CSR + - name: CRRCR + description: Clock recovery RC register + byte_offset: 152 + fieldset: CRRCR + - name: CCIPR2 + description: " Peripherals independent clock configuration register " + byte_offset: 156 + fieldset: CCIPR2 + - name: SECCFGR + description: " RCC secure configuration register " + byte_offset: 184 + fieldset: SECCFGR + - name: SECSR + description: RCC secure status register + byte_offset: 188 + fieldset: SECSR + - name: AHB1SECSR + description: " RCC AHB1 security status register " + byte_offset: 232 + access: Read + fieldset: AHB1SECSR + - name: AHB2SECSR + description: " RCC AHB2 security status register " + byte_offset: 236 + access: Read + fieldset: AHB2SECSR + - name: AHB3SECSR + description: " RCC AHB3 security status register " + byte_offset: 240 + access: Read + fieldset: AHB3SECSR + - name: APB1SECSR1 + description: " RCC APB1 security status register 1 " + byte_offset: 248 + access: Read + fieldset: APB1SECSR1 + - name: APB1SECSR2 + description: " RCC APB1 security status register 2 " + byte_offset: 252 + access: Read + fieldset: APB1SECSR2 + - name: APB2SECSR + description: " RCC APB2 security status register " + byte_offset: 256 + access: Read + fieldset: APB2SECSR +fieldset/AHB1ENR: + description: " AHB1 peripheral clock enable register " + fields: + - name: DMA1EN + description: DMA1 clock enable + bit_offset: 0 + bit_size: 1 + - name: DMA2EN + description: DMA2 clock enable + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1EN + description: DMAMUX clock enable + bit_offset: 2 + bit_size: 1 + - name: FLASHEN + description: " Flash memory interface clock enable " + bit_offset: 8 + bit_size: 1 + - name: CRCEN + description: CRC clock enable + bit_offset: 12 + bit_size: 1 + - name: TSCEN + description: " Touch Sensing Controller clock enable " + bit_offset: 16 + bit_size: 1 + - name: GTZCEN + description: GTZCEN + bit_offset: 22 + bit_size: 1 +fieldset/AHB1RSTR: + description: AHB1 peripheral reset register + fields: + - name: DMA1RST + description: DMA1 reset + bit_offset: 0 + bit_size: 1 + - name: DMA2RST + description: DMA2 reset + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1RST + description: DMAMUXRST + bit_offset: 2 + bit_size: 1 + - name: FLASHRST + description: " Flash memory interface reset " + bit_offset: 8 + bit_size: 1 + - name: CRCRST + description: CRC reset + bit_offset: 12 + bit_size: 1 + - name: TSCRST + description: " Touch Sensing Controller reset " + bit_offset: 16 + bit_size: 1 + - name: GTZCRST + description: GTZC reset + bit_offset: 22 + bit_size: 1 +fieldset/AHB1SECSR: + description: " RCC AHB1 security status register " + fields: + - name: DMA1SECF + description: DMA1SECF + bit_offset: 0 + bit_size: 1 + - name: DMA2SECF + description: DMA2SECF + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1SECF + description: DMAMUX1SECF + bit_offset: 2 + bit_size: 1 + - name: FLASHSECF + description: FLASHSECF + bit_offset: 8 + bit_size: 1 + - name: SRAM1SECF + description: SRAM1SECF + bit_offset: 9 + bit_size: 1 + - name: CRCSECF + description: CRCSECF + bit_offset: 12 + bit_size: 1 + - name: TSCSECF + description: TSCSECF + bit_offset: 16 + bit_size: 1 + - name: GTZCSECF + description: GTZCSECF + bit_offset: 22 + bit_size: 1 + - name: ICACHESECF + description: ICACHESECF + bit_offset: 23 + bit_size: 1 +fieldset/AHB1SMENR: + description: " AHB1 peripheral clocks enable in Sleep and Stop modes register " + fields: + - name: DMA1SMEN + description: " DMA1 clocks enable during Sleep and Stop modes " + bit_offset: 0 + bit_size: 1 + - name: DMA2SMEN + description: " DMA2 clocks enable during Sleep and Stop modes " + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1SMEN + description: " DMAMUX clock enable during Sleep and Stop modes " + bit_offset: 2 + bit_size: 1 + - name: FLASHSMEN + description: " Flash memory interface clocks enable during Sleep and Stop modes " + bit_offset: 8 + bit_size: 1 + - name: SRAM1SMEN + description: " SRAM1 interface clocks enable during Sleep and Stop modes " + bit_offset: 9 + bit_size: 1 + - name: CRCSMEN + description: CRCSMEN + bit_offset: 12 + bit_size: 1 + - name: TSCSMEN + description: " Touch Sensing Controller clocks enable during Sleep and Stop modes " + bit_offset: 16 + bit_size: 1 + - name: GTZCSMEN + description: GTZCSMEN + bit_offset: 22 + bit_size: 1 + - name: ICACHESMEN + description: ICACHESMEN + bit_offset: 23 + bit_size: 1 +fieldset/AHB2ENR: + description: " AHB2 peripheral clock enable register " + fields: + - name: GPIOAEN + description: IO port A clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: IO port B clock enable + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: IO port C clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIODEN + description: IO port D clock enable + bit_offset: 3 + bit_size: 1 + - name: GPIOEEN + description: IO port E clock enable + bit_offset: 4 + bit_size: 1 + - name: GPIOFEN + description: IO port F clock enable + bit_offset: 5 + bit_size: 1 + - name: GPIOGEN + description: IO port G clock enable + bit_offset: 6 + bit_size: 1 + - name: GPIOHEN + description: IO port H clock enable + bit_offset: 7 + bit_size: 1 + - name: ADCEN + description: ADC clock enable + bit_offset: 13 + bit_size: 1 + - name: AESEN + description: " AES accelerator clock enable " + bit_offset: 16 + bit_size: 1 + - name: HASHEN + description: HASH clock enable + bit_offset: 17 + bit_size: 1 + - name: RNGEN + description: " Random Number Generator clock enable " + bit_offset: 18 + bit_size: 1 + - name: PKAEN + description: PKAEN + bit_offset: 19 + bit_size: 1 + - name: OTFDEC1EN + description: OTFDEC1EN + bit_offset: 21 + bit_size: 1 + - name: SDMMC1EN + description: SDMMC1 clock enable + bit_offset: 22 + bit_size: 1 +fieldset/AHB2RSTR: + description: AHB2 peripheral reset register + fields: + - name: GPIOARST + description: IO port A reset + bit_offset: 0 + bit_size: 1 + - name: GPIOBRST + description: IO port B reset + bit_offset: 1 + bit_size: 1 + - name: GPIOCRST + description: IO port C reset + bit_offset: 2 + bit_size: 1 + - name: GPIODRST + description: IO port D reset + bit_offset: 3 + bit_size: 1 + - name: GPIOERST + description: IO port E reset + bit_offset: 4 + bit_size: 1 + - name: GPIOFRST + description: IO port F reset + bit_offset: 5 + bit_size: 1 + - name: GPIOGRST + description: IO port G reset + bit_offset: 6 + bit_size: 1 + - name: GPIOHRST + description: IO port H reset + bit_offset: 7 + bit_size: 1 + - name: ADCRST + description: ADC reset + bit_offset: 13 + bit_size: 1 + - name: AESRST + description: " AES hardware accelerator reset " + bit_offset: 16 + bit_size: 1 + - name: HASHRST + description: Hash reset + bit_offset: 17 + bit_size: 1 + - name: RNGRST + description: " Random number generator reset " + bit_offset: 18 + bit_size: 1 + - name: PKARST + description: PKARST + bit_offset: 19 + bit_size: 1 + - name: OTFDEC1RST + description: OTFDEC1RST + bit_offset: 21 + bit_size: 1 + - name: SDMMC1RST + description: SDMMC1 reset + bit_offset: 22 + bit_size: 1 +fieldset/AHB2SECSR: + description: " RCC AHB2 security status register " + fields: + - name: GPIOASECF + description: GPIOASECF + bit_offset: 0 + bit_size: 1 + - name: GPIOBSECF + description: GPIOBSECF + bit_offset: 1 + bit_size: 1 + - name: GPIOCSECF + description: GPIOCSECF + bit_offset: 2 + bit_size: 1 + - name: GPIODSECF + description: GPIODSECF + bit_offset: 3 + bit_size: 1 + - name: GPIOESECF + description: GPIOESECF + bit_offset: 4 + bit_size: 1 + - name: GPIOFSECF + description: GPIOFSECF + bit_offset: 5 + bit_size: 1 + - name: GPIOGSECF + description: GPIOGSECF + bit_offset: 6 + bit_size: 1 + - name: GPIOHSECF + description: GPIOHSECF + bit_offset: 7 + bit_size: 1 + - name: SRAM2SECF + description: SRAM2SECF + bit_offset: 9 + bit_size: 1 + - name: OTFDEC1SECF + description: OTFDEC1SECF + bit_offset: 21 + bit_size: 1 + - name: SDMMC1SECF + description: SDMMC1SECF + bit_offset: 22 + bit_size: 1 +fieldset/AHB2SMENR: + description: " AHB2 peripheral clocks enable in Sleep and Stop modes register " + fields: + - name: GPIOASMEN + description: " IO port A clocks enable during Sleep and Stop modes " + bit_offset: 0 + bit_size: 1 + - name: GPIOBSMEN + description: " IO port B clocks enable during Sleep and Stop modes " + bit_offset: 1 + bit_size: 1 + - name: GPIOCSMEN + description: " IO port C clocks enable during Sleep and Stop modes " + bit_offset: 2 + bit_size: 1 + - name: GPIODSMEN + description: " IO port D clocks enable during Sleep and Stop modes " + bit_offset: 3 + bit_size: 1 + - name: GPIOESMEN + description: " IO port E clocks enable during Sleep and Stop modes " + bit_offset: 4 + bit_size: 1 + - name: GPIOFSMEN + description: " IO port F clocks enable during Sleep and Stop modes " + bit_offset: 5 + bit_size: 1 + - name: GPIOGSMEN + description: " IO port G clocks enable during Sleep and Stop modes " + bit_offset: 6 + bit_size: 1 + - name: GPIOHSMEN + description: " IO port H clocks enable during Sleep and Stop modes " + bit_offset: 7 + bit_size: 1 + - name: SRAM2SMEN + description: " SRAM2 interface clocks enable during Sleep and Stop modes " + bit_offset: 9 + bit_size: 1 + - name: ADCFSSMEN + description: " ADC clocks enable during Sleep and Stop modes " + bit_offset: 13 + bit_size: 1 + - name: AESSMEN + description: " AES accelerator clocks enable during Sleep and Stop modes " + bit_offset: 16 + bit_size: 1 + - name: HASHSMEN + description: " HASH clock enable during Sleep and Stop modes " + bit_offset: 17 + bit_size: 1 + - name: RNGSMEN + description: " Random Number Generator clocks enable during Sleep and Stop modes " + bit_offset: 18 + bit_size: 1 + - name: PKASMEN + description: PKASMEN + bit_offset: 19 + bit_size: 1 + - name: OTFDEC1SMEN + description: OTFDEC1SMEN + bit_offset: 21 + bit_size: 1 + - name: SDMMC1SMEN + description: " SDMMC1 clocks enable during Sleep and Stop modes " + bit_offset: 22 + bit_size: 1 +fieldset/AHB3ENR: + description: " AHB3 peripheral clock enable register " + fields: + - name: FMCEN + description: " Flexible memory controller clock enable " + bit_offset: 0 + bit_size: 1 + - name: OSPI1EN + description: OSPI1EN + bit_offset: 8 + bit_size: 1 +fieldset/AHB3RSTR: + description: AHB3 peripheral reset register + fields: + - name: FMCRST + description: " Flexible memory controller reset " + bit_offset: 0 + bit_size: 1 + - name: OSPI1RST + description: OSPI1RST + bit_offset: 8 + bit_size: 1 +fieldset/AHB3SECSR: + description: " RCC AHB3 security status register " + fields: + - name: FSMCSECF + description: FSMCSECF + bit_offset: 0 + bit_size: 1 + - name: OSPI1SECF + description: OSPI1SECF + bit_offset: 8 + bit_size: 1 +fieldset/AHB3SMENR: + description: " AHB3 peripheral clocks enable in Sleep and Stop modes register " + fields: + - name: FMCSMEN + description: " Flexible memory controller clocks enable during Sleep and Stop modes " + bit_offset: 0 + bit_size: 1 + - name: OSPI1SMEN + description: OSPI1SMEN + bit_offset: 8 + bit_size: 1 +fieldset/APB1ENR1: + description: APB1ENR1 + fields: + - name: TIM2EN + description: TIM2 timer clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: TIM3 timer clock enable + bit_offset: 1 + bit_size: 1 + - name: TIM4EN + description: TIM4 timer clock enable + bit_offset: 2 + bit_size: 1 + - name: TIM5EN + description: TIM5 timer clock enable + bit_offset: 3 + bit_size: 1 + - name: TIM6EN + description: TIM6 timer clock enable + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: TIM7 timer clock enable + bit_offset: 5 + bit_size: 1 + - name: RTCAPBEN + description: RTC APB clock enable + bit_offset: 10 + bit_size: 1 + - name: WWDGEN + description: " Window watchdog clock enable " + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI2 clock enable + bit_offset: 14 + bit_size: 1 + - name: SP3EN + description: SPI3 clock enable + bit_offset: 15 + bit_size: 1 + - name: USART2EN + description: USART2 clock enable + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: USART3 clock enable + bit_offset: 18 + bit_size: 1 + - name: UART4EN + description: UART4 clock enable + bit_offset: 19 + bit_size: 1 + - name: UART5EN + description: UART5 clock enable + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: I2C1 clock enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C2 clock enable + bit_offset: 22 + bit_size: 1 + - name: I2C3EN + description: I2C3 clock enable + bit_offset: 23 + bit_size: 1 + - name: CRSEN + description: " Clock Recovery System clock enable " + bit_offset: 24 + bit_size: 1 + - name: PWREN + description: " Power interface clock enable " + bit_offset: 28 + bit_size: 1 + - name: DAC1EN + description: " DAC1 interface clock enable " + bit_offset: 29 + bit_size: 1 + - name: OPAMPEN + description: " OPAMP interface clock enable " + bit_offset: 30 + bit_size: 1 + - name: LPTIM1EN + description: " Low power timer 1 clock enable " + bit_offset: 31 + bit_size: 1 +fieldset/APB1ENR2: + description: " APB1 peripheral clock enable register 2 " + fields: + - name: LPUART1EN + description: " Low power UART 1 clock enable " + bit_offset: 0 + bit_size: 1 + - name: I2C4EN + description: I2C4 clock enable + bit_offset: 1 + bit_size: 1 + - name: LPTIM2EN + description: LPTIM2EN + bit_offset: 5 + bit_size: 1 + - name: LPTIM3EN + description: LPTIM3EN + bit_offset: 6 + bit_size: 1 + - name: FDCAN1EN + description: FDCAN1EN + bit_offset: 9 + bit_size: 1 + - name: USBFSEN + description: USBFSEN + bit_offset: 21 + bit_size: 1 + - name: UCPD1EN + description: UCPD1EN + bit_offset: 23 + bit_size: 1 +fieldset/APB1RSTR1: + description: " APB1 peripheral reset register 1 " + fields: + - name: TIM2RST + description: TIM2 timer reset + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: TIM3 timer reset + bit_offset: 1 + bit_size: 1 + - name: TIM4RST + description: TIM3 timer reset + bit_offset: 2 + bit_size: 1 + - name: TIM5RST + description: TIM5 timer reset + bit_offset: 3 + bit_size: 1 + - name: TIM6RST + description: TIM6 timer reset + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: TIM7 timer reset + bit_offset: 5 + bit_size: 1 + - name: SPI2RST + description: SPI2 reset + bit_offset: 14 + bit_size: 1 + - name: SPI3RST + description: SPI3 reset + bit_offset: 15 + bit_size: 1 + - name: USART2RST + description: USART2 reset + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: USART3 reset + bit_offset: 18 + bit_size: 1 + - name: UART4RST + description: UART4 reset + bit_offset: 19 + bit_size: 1 + - name: UART5RST + description: UART5 reset + bit_offset: 20 + bit_size: 1 + - name: I2C1RST + description: I2C1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C2 reset + bit_offset: 22 + bit_size: 1 + - name: I2C3RST + description: I2C3 reset + bit_offset: 23 + bit_size: 1 + - name: CRSRST + description: CRS reset + bit_offset: 24 + bit_size: 1 + - name: PWRRST + description: Power interface reset + bit_offset: 28 + bit_size: 1 + - name: DAC1RST + description: DAC1 interface reset + bit_offset: 29 + bit_size: 1 + - name: OPAMPRST + description: OPAMP interface reset + bit_offset: 30 + bit_size: 1 + - name: LPTIM1RST + description: Low Power Timer 1 reset + bit_offset: 31 + bit_size: 1 +fieldset/APB1RSTR2: + description: " APB1 peripheral reset register 2 " + fields: + - name: LPUART1RST + description: Low-power UART 1 reset + bit_offset: 0 + bit_size: 1 + - name: I2C4RST + description: I2C4 reset + bit_offset: 1 + bit_size: 1 + - name: LPTIM2RST + description: Low-power timer 2 reset + bit_offset: 5 + bit_size: 1 + - name: LPTIM3RST + description: LPTIM3RST + bit_offset: 6 + bit_size: 1 + - name: FDCAN1RST + description: FDCAN1RST + bit_offset: 9 + bit_size: 1 + - name: USBFSRST + description: USBFSRST + bit_offset: 21 + bit_size: 1 + - name: UCPD1RST + description: UCPD1RST + bit_offset: 23 + bit_size: 1 +fieldset/APB1SECSR1: + description: " RCC APB1 security status register 1 " + fields: + - name: TIM2SECF + description: TIM2SECF + bit_offset: 0 + bit_size: 1 + - name: TIM3SECF + description: TIM3SECF + bit_offset: 1 + bit_size: 1 + - name: TIM4SECF + description: TIM4SECF + bit_offset: 2 + bit_size: 1 + - name: TIM5SECF + description: TIM5SECF + bit_offset: 3 + bit_size: 1 + - name: TIM6SECF + description: TIM6SECF + bit_offset: 4 + bit_size: 1 + - name: TIM7SECF + description: TIM7SECF + bit_offset: 5 + bit_size: 1 + - name: RTCAPBSECF + description: RTCAPBSECF + bit_offset: 10 + bit_size: 1 + - name: WWDGSECF + description: WWDGSECF + bit_offset: 11 + bit_size: 1 + - name: SPI2SECF + description: SPI2SECF + bit_offset: 14 + bit_size: 1 + - name: SPI3SECF + description: SPI3SECF + bit_offset: 15 + bit_size: 1 + - name: UART2SECF + description: UART2SECF + bit_offset: 17 + bit_size: 1 + - name: UART3SECF + description: UART3SECF + bit_offset: 18 + bit_size: 1 + - name: UART4SECF + description: UART4SECF + bit_offset: 19 + bit_size: 1 + - name: UART5SECF + description: UART5SECF + bit_offset: 20 + bit_size: 1 + - name: I2C1SECF + description: I2C1SECF + bit_offset: 21 + bit_size: 1 + - name: I2C2SECF + description: I2C2SECF + bit_offset: 22 + bit_size: 1 + - name: I2C3SECF + description: I2C3SECF + bit_offset: 23 + bit_size: 1 + - name: CRSSECF + description: CRSSECF + bit_offset: 24 + bit_size: 1 + - name: PWRSECF + description: PWRSECF + bit_offset: 28 + bit_size: 1 + - name: DACSECF + description: DACSECF + bit_offset: 29 + bit_size: 1 + - name: OPAMPSECF + description: OPAMPSECF + bit_offset: 30 + bit_size: 1 + - name: LPTIM1SECF + description: LPTIM1SECF + bit_offset: 31 + bit_size: 1 +fieldset/APB1SECSR2: + description: " RCC APB1 security status register 2 " + fields: + - name: LPUART1SECF + description: LPUART1SECF + bit_offset: 0 + bit_size: 1 + - name: I2C4SECF + description: I2C4SECF + bit_offset: 1 + bit_size: 1 + - name: LPTIM2SECF + description: LPTIM2SECF + bit_offset: 5 + bit_size: 1 + - name: LPTIM3SECF + description: LPTIM3SECF + bit_offset: 6 + bit_size: 1 + - name: FDCAN1SECF + description: FDCAN1SECF + bit_offset: 9 + bit_size: 1 + - name: USBFSSECF + description: USBFSSECF + bit_offset: 21 + bit_size: 1 + - name: UCPD1SECF + description: UCPD1SECF + bit_offset: 23 + bit_size: 1 +fieldset/APB1SMENR1: + description: APB1SMENR1 + fields: + - name: TIM2SMEN + description: " TIM2 timer clocks enable during Sleep and Stop modes " + bit_offset: 0 + bit_size: 1 + - name: TIM3SMEN + description: " TIM3 timer clocks enable during Sleep and Stop modes " + bit_offset: 1 + bit_size: 1 + - name: TIM4SMEN + description: " TIM4 timer clocks enable during Sleep and Stop modes " + bit_offset: 2 + bit_size: 1 + - name: TIM5SMEN + description: " TIM5 timer clocks enable during Sleep and Stop modes " + bit_offset: 3 + bit_size: 1 + - name: TIM6SMEN + description: " TIM6 timer clocks enable during Sleep and Stop modes " + bit_offset: 4 + bit_size: 1 + - name: TIM7SMEN + description: " TIM7 timer clocks enable during Sleep and Stop modes " + bit_offset: 5 + bit_size: 1 + - name: RTCAPBSMEN + description: " RTC APB clock enable during Sleep and Stop modes " + bit_offset: 10 + bit_size: 1 + - name: WWDGSMEN + description: " Window watchdog clocks enable during Sleep and Stop modes " + bit_offset: 11 + bit_size: 1 + - name: SPI2SMEN + description: " SPI2 clocks enable during Sleep and Stop modes " + bit_offset: 14 + bit_size: 1 + - name: SP3SMEN + description: " SPI3 clocks enable during Sleep and Stop modes " + bit_offset: 15 + bit_size: 1 + - name: USART2SMEN + description: " USART2 clocks enable during Sleep and Stop modes " + bit_offset: 17 + bit_size: 1 + - name: USART3SMEN + description: " USART3 clocks enable during Sleep and Stop modes " + bit_offset: 18 + bit_size: 1 + - name: UART4SMEN + description: " UART4 clocks enable during Sleep and Stop modes " + bit_offset: 19 + bit_size: 1 + - name: UART5SMEN + description: " UART5 clocks enable during Sleep and Stop modes " + bit_offset: 20 + bit_size: 1 + - name: I2C1SMEN + description: " I2C1 clocks enable during Sleep and Stop modes " + bit_offset: 21 + bit_size: 1 + - name: I2C2SMEN + description: " I2C2 clocks enable during Sleep and Stop modes " + bit_offset: 22 + bit_size: 1 + - name: I2C3SMEN + description: " I2C3 clocks enable during Sleep and Stop modes " + bit_offset: 23 + bit_size: 1 + - name: CRSSMEN + description: " CRS clock enable during Sleep and Stop modes " + bit_offset: 24 + bit_size: 1 + - name: PWRSMEN + description: " Power interface clocks enable during Sleep and Stop modes " + bit_offset: 28 + bit_size: 1 + - name: DAC1SMEN + description: " DAC1 interface clocks enable during Sleep and Stop modes " + bit_offset: 29 + bit_size: 1 + - name: OPAMPSMEN + description: " OPAMP interface clocks enable during Sleep and Stop modes " + bit_offset: 30 + bit_size: 1 + - name: LPTIM1SMEN + description: " Low power timer 1 clocks enable during Sleep and Stop modes " + bit_offset: 31 + bit_size: 1 +fieldset/APB1SMENR2: + description: " APB1 peripheral clocks enable in Sleep and Stop modes register 2 " + fields: + - name: LPUART1SMEN + description: " Low power UART 1 clocks enable during Sleep and Stop modes " + bit_offset: 0 + bit_size: 1 + - name: I2C4SMEN + description: " I2C4 clocks enable during Sleep and Stop modes " + bit_offset: 1 + bit_size: 1 + - name: LPTIM2SMEN + description: LPTIM2SMEN + bit_offset: 5 + bit_size: 1 + - name: LPTIM3SMEN + description: LPTIM3SMEN + bit_offset: 6 + bit_size: 1 + - name: FDCAN1SMEN + description: FDCAN1SMEN + bit_offset: 9 + bit_size: 1 + - name: USBFSSMEN + description: USBFSSMEN + bit_offset: 21 + bit_size: 1 + - name: UCPD1SMEN + description: UCPD1SMEN + bit_offset: 23 + bit_size: 1 +fieldset/APB2ENR: + description: APB2ENR + fields: + - name: SYSCFGEN + description: SYSCFG clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM1EN + description: TIM1 timer clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: SPI1 clock enable + bit_offset: 12 + bit_size: 1 + - name: TIM8EN + description: TIM8 timer clock enable + bit_offset: 13 + bit_size: 1 + - name: USART1EN + description: USART1clock enable + bit_offset: 14 + bit_size: 1 + - name: TIM15EN + description: TIM15 timer clock enable + bit_offset: 16 + bit_size: 1 + - name: TIM16EN + description: TIM16 timer clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: TIM17 timer clock enable + bit_offset: 18 + bit_size: 1 + - name: SAI1EN + description: SAI1 clock enable + bit_offset: 21 + bit_size: 1 + - name: SAI2EN + description: SAI2 clock enable + bit_offset: 22 + bit_size: 1 + - name: DFSDM1EN + description: DFSDM timer clock enable + bit_offset: 24 + bit_size: 1 +fieldset/APB2RSTR: + description: APB2 peripheral reset register + fields: + - name: SYSCFGRST + description: " System configuration (SYSCFG) reset " + bit_offset: 0 + bit_size: 1 + - name: TIM1RST + description: TIM1 timer reset + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: SPI1 reset + bit_offset: 12 + bit_size: 1 + - name: TIM8RST + description: TIM8 timer reset + bit_offset: 13 + bit_size: 1 + - name: USART1RST + description: USART1 reset + bit_offset: 14 + bit_size: 1 + - name: TIM15RST + description: TIM15 timer reset + bit_offset: 16 + bit_size: 1 + - name: TIM16RST + description: TIM16 timer reset + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: TIM17 timer reset + bit_offset: 18 + bit_size: 1 + - name: SAI1RST + description: " Serial audio interface 1 (SAI1) reset " + bit_offset: 21 + bit_size: 1 + - name: SAI2RST + description: " Serial audio interface 2 (SAI2) reset " + bit_offset: 22 + bit_size: 1 + - name: DFSDM1RST + description: " Digital filters for sigma-delata modulators (DFSDM) reset " + bit_offset: 24 + bit_size: 1 +fieldset/APB2SECSR: + description: " RCC APB2 security status register " + fields: + - name: SYSCFGSECF + description: SYSCFGSECF + bit_offset: 0 + bit_size: 1 + - name: TIM1SECF + description: TIM1SECF + bit_offset: 11 + bit_size: 1 + - name: SPI1SECF + description: SPI1SECF + bit_offset: 12 + bit_size: 1 + - name: TIM8SECF + description: TIM8SECF + bit_offset: 13 + bit_size: 1 + - name: USART1SECF + description: USART1SECF + bit_offset: 14 + bit_size: 1 + - name: TIM15SECF + description: TIM15SECF + bit_offset: 16 + bit_size: 1 + - name: TIM16SECF + description: TIM16SECF + bit_offset: 17 + bit_size: 1 + - name: TIM17SECF + description: TIM17SECF + bit_offset: 18 + bit_size: 1 + - name: SAI1SECF + description: SAI1SECF + bit_offset: 21 + bit_size: 1 + - name: SAI2SECF + description: SAI2SECF + bit_offset: 22 + bit_size: 1 + - name: DFSDM1SECF + description: DFSDM1SECF + bit_offset: 24 + bit_size: 1 +fieldset/APB2SMENR: + description: APB2SMENR + fields: + - name: SYSCFGSMEN + description: " SYSCFG clocks enable during Sleep and Stop modes " + bit_offset: 0 + bit_size: 1 + - name: TIM1SMEN + description: " TIM1 timer clocks enable during Sleep and Stop modes " + bit_offset: 11 + bit_size: 1 + - name: SPI1SMEN + description: " SPI1 clocks enable during Sleep and Stop modes " + bit_offset: 12 + bit_size: 1 + - name: TIM8SMEN + description: " TIM8 timer clocks enable during Sleep and Stop modes " + bit_offset: 13 + bit_size: 1 + - name: USART1SMEN + description: " USART1clocks enable during Sleep and Stop modes " + bit_offset: 14 + bit_size: 1 + - name: TIM15SMEN + description: " TIM15 timer clocks enable during Sleep and Stop modes " + bit_offset: 16 + bit_size: 1 + - name: TIM16SMEN + description: " TIM16 timer clocks enable during Sleep and Stop modes " + bit_offset: 17 + bit_size: 1 + - name: TIM17SMEN + description: " TIM17 timer clocks enable during Sleep and Stop modes " + bit_offset: 18 + bit_size: 1 + - name: SAI1SMEN + description: " SAI1 clocks enable during Sleep and Stop modes " + bit_offset: 21 + bit_size: 1 + - name: SAI2SMEN + description: " SAI2 clocks enable during Sleep and Stop modes " + bit_offset: 22 + bit_size: 1 + - name: DFSDM1SMEN + description: " DFSDM timer clocks enable during Sleep and Stop modes " + bit_offset: 24 + bit_size: 1 +fieldset/BDCR: + description: BDCR + fields: + - name: LSEON + description: LSE oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: LSE oscillator ready + bit_offset: 1 + bit_size: 1 + enum_read: LSERDYR + - name: LSEBYP + description: LSE oscillator bypass + bit_offset: 2 + bit_size: 1 + enum: LSEBYP + - name: LSEDRV + description: " SE oscillator drive capability " + bit_offset: 3 + bit_size: 2 + enum: LSEDRV + - name: LSECSSON + description: LSECSSON + bit_offset: 5 + bit_size: 1 + - name: LSECSSD + description: LSECSSD + bit_offset: 6 + bit_size: 1 + enum_read: LSECSSDR + - name: LSESYSEN + description: LSESYSEN + bit_offset: 7 + bit_size: 1 + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: LSESYSRDY + description: LSESYSRDY + bit_offset: 11 + bit_size: 1 + enum_read: LSESYSRDYR + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: " Backup domain software reset " + bit_offset: 16 + bit_size: 1 + - name: LSCOEN + description: " Low speed clock output enable " + bit_offset: 24 + bit_size: 1 + - name: LSCOSEL + description: " Low speed clock output selection " + bit_offset: 25 + bit_size: 1 + enum: LSCOSEL +fieldset/CCIPR1: + description: CCIPR1 + fields: + - name: USART1SEL + description: " USART1 clock source selection " + bit_offset: 0 + bit_size: 2 + - name: USART2SEL + description: " USART2 clock source selection " + bit_offset: 2 + bit_size: 2 + - name: USART3SEL + description: " USART3 clock source selection " + bit_offset: 4 + bit_size: 2 + - name: UART4SEL + description: " UART4 clock source selection " + bit_offset: 6 + bit_size: 2 + - name: UART5SEL + description: " UART5 clock source selection " + bit_offset: 8 + bit_size: 2 + - name: LPUART1SEL + description: " LPUART1 clock source selection " + bit_offset: 10 + bit_size: 2 + - name: I2C1SEL + description: " I2C1 clock source selection " + bit_offset: 12 + bit_size: 2 + - name: I2C2SEL + description: " I2C2 clock source selection " + bit_offset: 14 + bit_size: 2 + - name: I2C3SEL + description: " I2C3 clock source selection " + bit_offset: 16 + bit_size: 2 + - name: LPTIM1SEL + description: " Low power timer 1 clock source selection " + bit_offset: 18 + bit_size: 2 + - name: LPTIM2SEL + description: " Low power timer 2 clock source selection " + bit_offset: 20 + bit_size: 2 + - name: LPTIM3SEL + description: " Low-power timer 3 clock source selection " + bit_offset: 22 + bit_size: 2 + - name: FDCANSEL + description: " FDCAN clock source selection " + bit_offset: 24 + bit_size: 2 + - name: CLK48MSEL + description: " 48 MHz clock source selection " + bit_offset: 26 + bit_size: 2 + - name: ADCSEL + description: " ADCs clock source selection " + bit_offset: 28 + bit_size: 2 +fieldset/CCIPR2: + description: " Peripherals independent clock configuration register " + fields: + - name: I2C4SEL + description: " I2C4 clock source selection " + bit_offset: 0 + bit_size: 2 + - name: DFSDMSEL + description: " Digital filter for sigma delta modulator kernel clock source selection " + bit_offset: 2 + bit_size: 1 + - name: ADFSDMSEL + description: " Digital filter for sigma delta modulator audio clock source selection " + bit_offset: 3 + bit_size: 2 + - name: SAI1SEL + description: " SAI1 clock source selection " + bit_offset: 5 + bit_size: 3 + - name: SAI2SEL + description: " SAI2 clock source selection " + bit_offset: 8 + bit_size: 3 + - name: SDMMCSEL + description: SDMMC clock selection + bit_offset: 14 + bit_size: 1 + - name: OSPISEL + description: " Octospi clock source selection " + bit_offset: 20 + bit_size: 2 +fieldset/CFGR: + description: Clock configuration register + fields: + - name: SW + description: System clock switch + bit_offset: 0 + bit_size: 2 + enum: SW + - name: SWS + description: System clock switch status + bit_offset: 2 + bit_size: 2 + enum_read: SWSR + - name: HPRE + description: AHB prescaler + bit_offset: 4 + bit_size: 4 + enum: HPRE + - name: PPRE1 + description: " PB low-speed prescaler (APB1) " + bit_offset: 8 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: " APB high-speed prescaler (APB2) " + bit_offset: 11 + bit_size: 3 + enum: PPRE + - name: STOPWUCK + description: " Wakeup from Stop and CSS backup clock selection " + bit_offset: 15 + bit_size: 1 + enum: STOPWUCK + - name: MCOSEL + description: " Microcontroller clock output " + bit_offset: 24 + bit_size: 4 + enum: MCOSEL + - name: MCOPRE + description: " Microcontroller clock output prescaler " + bit_offset: 28 + bit_size: 3 + enum: MCOPRE +fieldset/CICR: + description: Clock interrupt clear register + fields: + - name: LSIRDYC + description: LSI ready interrupt clear + bit_offset: 0 + bit_size: 1 + - name: LSERDYC + description: LSE ready interrupt clear + bit_offset: 1 + bit_size: 1 + - name: MSIRDYC + description: MSI ready interrupt clear + bit_offset: 2 + bit_size: 1 + - name: HSIRDYC + description: HSI ready interrupt clear + bit_offset: 3 + bit_size: 1 + - name: HSERDYC + description: HSE ready interrupt clear + bit_offset: 4 + bit_size: 1 + - name: PLLRDYC + description: PLL ready interrupt clear + bit_offset: 5 + bit_size: 1 + - name: PLLSAI1RDYC + description: " PLLSAI1 ready interrupt clear " + bit_offset: 6 + bit_size: 1 + - name: PLLSAI2RDYC + description: " PLLSAI2 ready interrupt clear " + bit_offset: 7 + bit_size: 1 + - name: CSSC + description: " Clock security system interrupt clear " + bit_offset: 8 + bit_size: 1 + - name: LSECSSC + description: " LSE Clock security system interrupt clear " + bit_offset: 9 + bit_size: 1 + - name: HSI48RDYC + description: " HSI48 oscillator ready interrupt clear " + bit_offset: 10 + bit_size: 1 +fieldset/CIER: + description: " Clock interrupt enable register " + fields: + - name: LSIRDYIE + description: LSI ready interrupt enable + bit_offset: 0 + bit_size: 1 + - name: LSERDYIE + description: LSE ready interrupt enable + bit_offset: 1 + bit_size: 1 + - name: MSIRDYIE + description: MSI ready interrupt enable + bit_offset: 2 + bit_size: 1 + - name: HSIRDYIE + description: HSI ready interrupt enable + bit_offset: 3 + bit_size: 1 + - name: HSERDYIE + description: HSE ready interrupt enable + bit_offset: 4 + bit_size: 1 + - name: PLLRDYIE + description: PLL ready interrupt enable + bit_offset: 5 + bit_size: 1 + - name: PLLSAI1RDYIE + description: " PLLSAI1 ready interrupt enable " + bit_offset: 6 + bit_size: 1 + - name: PLLSAI2RDYIE + description: " PLLSAI2 ready interrupt enable " + bit_offset: 7 + bit_size: 1 + - name: LSECSSIE + description: " LSE clock security system interrupt enable " + bit_offset: 9 + bit_size: 1 + - name: HSI48RDYIE + description: " HSI48 ready interrupt enable " + bit_offset: 10 + bit_size: 1 +fieldset/CIFR: + description: Clock interrupt flag register + fields: + - name: LSIRDYF + description: LSI ready interrupt flag + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE ready interrupt flag + bit_offset: 1 + bit_size: 1 + - name: MSIRDYF + description: MSI ready interrupt flag + bit_offset: 2 + bit_size: 1 + - name: HSIRDYF + description: HSI ready interrupt flag + bit_offset: 3 + bit_size: 1 + - name: HSERDYF + description: HSE ready interrupt flag + bit_offset: 4 + bit_size: 1 + - name: PLLRDYF + description: PLL ready interrupt flag + bit_offset: 5 + bit_size: 1 + - name: PLLSAI1RDYF + description: " PLLSAI1 ready interrupt flag " + bit_offset: 6 + bit_size: 1 + - name: PLLSAI2RDYF + description: " PLLSAI2 ready interrupt flag " + bit_offset: 7 + bit_size: 1 + - name: CSSF + description: " Clock security system interrupt flag " + bit_offset: 8 + bit_size: 1 + - name: LSECSSF + description: " LSE Clock security system interrupt flag " + bit_offset: 9 + bit_size: 1 + - name: HSI48RDYF + description: HSI48 ready interrupt flag + bit_offset: 10 + bit_size: 1 +fieldset/CR: + description: Clock control register + fields: + - name: MSION + description: MSI clock enable + bit_offset: 0 + bit_size: 1 + - name: MSIRDY + description: MSI clock ready flag + bit_offset: 1 + bit_size: 1 + enum_read: PLLSAIRDYR + - name: MSIPLLEN + description: MSI clock PLL enable + bit_offset: 2 + bit_size: 1 + - name: MSIRGSEL + description: MSI clock range selection + bit_offset: 3 + bit_size: 1 + - name: MSIRANGE + description: MSI clock ranges + bit_offset: 4 + bit_size: 4 + - name: HSION + description: HSI clock enable + bit_offset: 8 + bit_size: 1 + - name: HSIKERON + description: " HSI always enable for peripheral kernels " + bit_offset: 9 + bit_size: 1 + - name: HSIRDY + description: HSI clock ready flag + bit_offset: 10 + bit_size: 1 + enum_read: PLLSAIRDYR + - name: HSIASFS + description: " HSI automatic start from Stop " + bit_offset: 11 + bit_size: 1 + - name: HSEON + description: HSE clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: HSE clock ready flag + bit_offset: 17 + bit_size: 1 + enum_read: PLLSAIRDYR + - name: HSEBYP + description: " HSE crystal oscillator bypass " + bit_offset: 18 + bit_size: 1 + enum: HSEBYP + - name: CSSON + description: " Clock security system enable " + bit_offset: 19 + bit_size: 1 + - name: PLLON + description: Main PLL enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: Main PLL clock ready flag + bit_offset: 25 + bit_size: 1 + enum_read: PLLSAIRDYR + - name: PLLSAI1ON + description: SAI1 PLL enable + bit_offset: 26 + bit_size: 1 + - name: PLLSAI1RDY + description: SAI1 PLL clock ready flag + bit_offset: 27 + bit_size: 1 + enum_read: PLLSAIRDYR + - name: PLLSAI2ON + description: SAI2 PLL enable + bit_offset: 28 + bit_size: 1 + - name: PLLSAI2RDY + description: SAI2 PLL clock ready flag + bit_offset: 29 + bit_size: 1 + enum_read: PLLSAIRDYR + - name: PRIV + description: PRIV + bit_offset: 31 + bit_size: 1 +fieldset/CRRCR: + description: Clock recovery RC register + fields: + - name: HSI48ON + description: HSI48 clock enable + bit_offset: 0 + bit_size: 1 + - name: HSI48RDY + description: HSI48 clock ready flag + bit_offset: 1 + bit_size: 1 + - name: HSI48CAL + description: HSI48 clock calibration + bit_offset: 7 + bit_size: 9 +fieldset/CSR: + description: CSR + fields: + - name: LSION + description: LSI oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: LSI oscillator ready + bit_offset: 1 + bit_size: 1 + enum_read: LSIRDYR + - name: LSIPREDIV + description: LSIPREDIV + bit_offset: 4 + bit_size: 1 + - name: MSISRANGE + description: " SI range after Standby mode " + bit_offset: 8 + bit_size: 4 + - name: RMVF + description: Remove reset flag + bit_offset: 23 + bit_size: 1 + enum_write: RMVFW + - name: OBLRSTF + description: " Option byte loader reset flag " + bit_offset: 25 + bit_size: 1 + enum_read: LPWRSTFR + - name: PINRSTF + description: Pin reset flag + bit_offset: 26 + bit_size: 1 + enum_read: LPWRSTFR + - name: BORRSTF + description: BOR flag + bit_offset: 27 + bit_size: 1 + enum_read: LPWRSTFR + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + enum_read: LPWRSTFR + - name: IWWDGRSTF + description: " Independent window watchdog reset flag " + bit_offset: 29 + bit_size: 1 + enum_read: LPWRSTFR + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + enum_read: LPWRSTFR + - name: LPWRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 + enum_read: LPWRSTFR +fieldset/ICSCR: + description: " Internal clock sources calibration register " + fields: + - name: MSICAL + description: MSI clock calibration + bit_offset: 0 + bit_size: 8 + - name: MSITRIM + description: MSI clock trimming + bit_offset: 8 + bit_size: 8 + - name: HSICAL + description: HSI clock calibration + bit_offset: 16 + bit_size: 8 + - name: HSITRIM + description: HSI clock trimming + bit_offset: 24 + bit_size: 7 +fieldset/PLLCFGR: + description: PLL configuration register + fields: + - name: PLLSRC + description: " Main PLL, PLLSAI1 and PLLSAI2 entry clock source " + bit_offset: 0 + bit_size: 2 + - name: PLLM + description: " Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock " + bit_offset: 4 + bit_size: 4 + - name: PLLN + description: " Main PLL multiplication factor for VCO " + bit_offset: 8 + bit_size: 7 + - name: PLLPEN + description: " Main PLL PLLSAI3CLK output enable " + bit_offset: 16 + bit_size: 1 + - name: PLLP + description: " Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) " + bit_offset: 17 + bit_size: 1 + - name: PLLQEN + description: " Main PLL PLLUSB1CLK output enable " + bit_offset: 20 + bit_size: 1 + - name: PLLQ + description: " Main PLL division factor for PLLUSB1CLK(48 MHz clock) " + bit_offset: 21 + bit_size: 2 + - name: PLLREN + description: " Main PLL PLLCLK output enable " + bit_offset: 24 + bit_size: 1 + - name: PLLR + description: " Main PLL division factor for PLLCLK (system clock) " + bit_offset: 25 + bit_size: 2 + - name: PLLPDIV + description: " Main PLL division factor for PLLSAI2CLK " + bit_offset: 27 + bit_size: 5 +fieldset/PLLSAI1CFGR: + description: PLLSAI1 configuration register + fields: + - name: PLLSAI1SRC + description: PLLSAI1SRC + bit_offset: 0 + bit_size: 2 + - name: PLLSAI1M + description: " Division factor for PLLSAI1 input clock " + bit_offset: 4 + bit_size: 4 + - name: PLLSAI1N + description: " SAI1PLL multiplication factor for VCO " + bit_offset: 8 + bit_size: 7 + - name: PLLSAI1PEN + description: " SAI1PLL PLLSAI1CLK output enable " + bit_offset: 16 + bit_size: 1 + - name: PLLSAI1P + description: " SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock) " + bit_offset: 17 + bit_size: 1 + - name: PLLSAI1QEN + description: " SAI1PLL PLLUSB2CLK output enable " + bit_offset: 20 + bit_size: 1 + - name: PLLSAI1Q + description: " SAI1PLL division factor for PLLUSB2CLK (48 MHz clock) " + bit_offset: 21 + bit_size: 2 + - name: PLLSAI1REN + description: " PLLSAI1 PLLADC1CLK output enable " + bit_offset: 24 + bit_size: 1 + - name: PLLSAI1R + description: " PLLSAI1 division factor for PLLADC1CLK (ADC clock) " + bit_offset: 25 + bit_size: 2 + - name: PLLSAI1PDIV + description: " PLLSAI1 division factor for PLLSAI1CLK " + bit_offset: 27 + bit_size: 5 +fieldset/PLLSAI2CFGR: + description: PLLSAI2 configuration register + fields: + - name: PLLSAI2SRC + description: PLLSAI2SRC + bit_offset: 0 + bit_size: 2 + - name: PLLSAI2M + description: " Division factor for PLLSAI2 input clock " + bit_offset: 4 + bit_size: 4 + - name: PLLSAI2N + description: " SAI2PLL multiplication factor for VCO " + bit_offset: 8 + bit_size: 7 + - name: PLLSAI2PEN + description: " SAI2PLL PLLSAI2CLK output enable " + bit_offset: 16 + bit_size: 1 + - name: PLLSAI2P + description: " SAI1PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock) " + bit_offset: 17 + bit_size: 1 + - name: PLLSAI2PDIV + description: " PLLSAI2 division factor for PLLSAI2CLK " + bit_offset: 27 + bit_size: 5 +fieldset/SECCFGR: + description: " RCC secure configuration register " + fields: + - name: HSISEC + description: HSISEC + bit_offset: 0 + bit_size: 1 + - name: HSESEC + description: HSESEC + bit_offset: 1 + bit_size: 1 + - name: MSISEC + description: MSISEC + bit_offset: 2 + bit_size: 1 + - name: LSISEC + description: LSISEC + bit_offset: 3 + bit_size: 1 + - name: LSESEC + description: LSESEC + bit_offset: 4 + bit_size: 1 + - name: SYSCLKSEC + description: SYSCLKSEC + bit_offset: 5 + bit_size: 1 + - name: PRESCSEC + description: PRESCSEC + bit_offset: 6 + bit_size: 1 + - name: PLLSEC + description: PLLSEC + bit_offset: 7 + bit_size: 1 + - name: PLLSAI1SEC + description: PLLSAI1SEC + bit_offset: 8 + bit_size: 1 + - name: PLLSAI2SEC + description: PLLSAI2SEC + bit_offset: 9 + bit_size: 1 + - name: CLK48MSEC + description: CLK48MSEC + bit_offset: 10 + bit_size: 1 + - name: HSI48SEC + description: HSI48SEC + bit_offset: 11 + bit_size: 1 + - name: RMVFSEC + description: RMVFSEC + bit_offset: 12 + bit_size: 1 +fieldset/SECSR: + description: RCC secure status register + fields: + - name: HSISECF + description: HSISECF + bit_offset: 0 + bit_size: 1 + - name: HSESECF + description: HSESECF + bit_offset: 1 + bit_size: 1 + - name: MSISECF + description: MSISECF + bit_offset: 2 + bit_size: 1 + - name: LSISECF + description: LSISECF + bit_offset: 3 + bit_size: 1 + - name: LSESECF + description: LSESECF + bit_offset: 4 + bit_size: 1 + - name: SYSCLKSECF + description: SYSCLKSECF + bit_offset: 5 + bit_size: 1 + - name: PRESCSECF + description: PRESCSECF + bit_offset: 6 + bit_size: 1 + - name: PLLSECF + description: PLLSECF + bit_offset: 7 + bit_size: 1 + - name: PLLSAI1SECF + description: PLLSAI1SECF + bit_offset: 8 + bit_size: 1 + - name: PLLSAI2SECF + description: PLLSAI2SECF + bit_offset: 9 + bit_size: 1 + - name: CLK48MSECF + description: CLK48MSECF + bit_offset: 10 + bit_size: 1 + - name: HSI48SECF + description: HSI48SECF + bit_offset: 11 + bit_size: 1 + - name: RMVFSECF + description: RMVFSECF + bit_offset: 12 + bit_size: 1 +enum/HPRE: + bit_size: 4 + variants: + - name: Div1 + description: SYSCLK not divided + value: 0 + - name: Div2 + description: SYSCLK divided by 2 + value: 8 + - name: Div4 + description: SYSCLK divided by 4 + value: 9 + - name: Div8 + description: SYSCLK divided by 8 + value: 10 + - name: Div16 + description: SYSCLK divided by 16 + value: 11 + - name: Div64 + description: SYSCLK divided by 64 + value: 12 + - name: Div128 + description: SYSCLK divided by 128 + value: 13 + - name: Div256 + description: SYSCLK divided by 256 + value: 14 + - name: Div512 + description: SYSCLK divided by 512 + value: 15 +enum/HSEBYP: + bit_size: 1 + variants: + - name: NotBypassed + description: HSE crystal oscillator not bypassed + value: 0 + - name: Bypassed + description: HSE crystal oscillator bypassed with external clock + value: 1 +enum/LPWRSTFR: + bit_size: 1 + variants: + - name: NoReset + description: No reset has occured + value: 0 + - name: Reset + description: A reset has occured + value: 1 +enum/LSCOSEL: + bit_size: 1 + variants: + - name: LSI + description: "LSI clock selected\"" + value: 0 + - name: LSE + description: LSE clock selected + value: 1 +enum/LSEBYP: + bit_size: 1 + variants: + - name: NotBypassed + description: LSE crystal oscillator not bypassed + value: 0 + - name: Bypassed + description: LSE crystal oscillator bypassed with external clock + value: 1 +enum/LSECSSDR: + bit_size: 1 + variants: + - name: NoFailure + description: No failure detected on LSE (32 kHz oscillator) + value: 0 + - name: Failure + description: Failure detected on LSE (32 kHz oscillator) + value: 1 +enum/LSEDRV: + bit_size: 2 + variants: + - name: Lower + description: "'Xtal mode' lower driving capability" + value: 0 + - name: MediumLow + description: "'Xtal mode' medium low driving capability" + value: 1 + - name: MediumHigh + description: "'Xtal mode' medium high driving capability" + value: 2 + - name: Higher + description: "'Xtal mode' higher driving capability" + value: 3 +enum/LSERDYR: + bit_size: 1 + variants: + - name: NotReady + description: LSE oscillator not ready + value: 0 + - name: Ready + description: LSE oscillator ready + value: 1 +enum/LSESYSRDYR: + bit_size: 1 + variants: + - name: NotReady + description: LSESYS clock not ready + value: 0 + - name: Ready + description: LSESYS clock ready + value: 1 +enum/LSIRDYR: + bit_size: 1 + variants: + - name: NotReady + description: LSI oscillator not ready + value: 0 + - name: Ready + description: LSI oscillator ready + value: 1 +enum/MCOPRE: + bit_size: 3 + variants: + - name: Div1 + description: MCO divided by 1 + value: 0 + - name: Div2 + description: MCO divided by 2 + value: 1 + - name: Div4 + description: MCO divided by 4 + value: 2 + - name: Div8 + description: MCO divided by 8 + value: 3 + - name: Div16 + description: MCO divided by 16 + value: 4 +enum/MCOSEL: + bit_size: 4 + variants: + - name: None + description: "MCO output disabled, no clock on MCO" + value: 0 + - name: SYSCLK + description: SYSCLK system clock selected + value: 1 + - name: MSI + description: MSI clock selected + value: 2 + - name: HSI + description: HSI clock selected + value: 3 + - name: HSE + description: HSE clock selected + value: 4 + - name: PLL + description: Main PLL clock selected + value: 5 + - name: LSI + description: LSI clock selected + value: 6 + - name: LSE + description: LSE clock selected + value: 7 + - name: HSI48 + description: Internal HSI48 clock selected + value: 8 +enum/PLLSAIRDYR: + bit_size: 1 + variants: + - name: NotReady + description: Clock not ready + value: 0 + - name: Ready + description: Clock ready + value: 1 +enum/PPRE: + bit_size: 3 + variants: + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 +enum/RMVFW: + bit_size: 1 + variants: + - name: Clear + description: Clears the reset flag + value: 1 +enum/RTCSEL: + bit_size: 2 + variants: + - name: NoClock + description: No clock + value: 0 + - name: LSE + description: LSE oscillator clock used as RTC clock + value: 1 + - name: LSI + description: LSI oscillator clock used as RTC clock + value: 2 + - name: HSE + description: HSE oscillator clock divided by a prescaler used as RTC clock + value: 3 +enum/STOPWUCK: + bit_size: 1 + variants: + - name: MSI + description: MSI oscillator selected as wakeup from stop clock and CSS backup clock + value: 0 + - name: HSI + description: HSI oscillator selected as wakeup from stop clock and CSS backup clock + value: 1 +enum/SW: + bit_size: 2 + variants: + - name: MSI + description: MSI selected as system clock + value: 0 + - name: HSI + description: HSI selected as system clock + value: 1 + - name: HSE + description: HSE selected as system clock + value: 2 + - name: PLL + description: PLL selected as system clock + value: 3 +enum/SWSR: + bit_size: 2 + variants: + - name: MSI + description: MSI oscillator used as system clock + value: 0 + - name: HSI + description: HSI oscillator used as system clock + value: 1 + - name: HSE + description: HSE used as system clock + value: 2 + - name: PLL + description: PLL used as system clock + value: 3 diff --git a/data/registers/rcc_wb55.yaml b/data/registers/rcc_wb.yaml similarity index 100% rename from data/registers/rcc_wb55.yaml rename to data/registers/rcc_wb.yaml diff --git a/data/registers/rcc_wl5x.yaml b/data/registers/rcc_wl5.yaml similarity index 100% rename from data/registers/rcc_wl5x.yaml rename to data/registers/rcc_wl5.yaml diff --git a/data/registers/rcc_wle.yaml b/data/registers/rcc_wle.yaml new file mode 100644 index 0000000..ce21b21 --- /dev/null +++ b/data/registers/rcc_wle.yaml @@ -0,0 +1,1046 @@ +--- +block/RCC: + description: Reset and clock control + items: + - name: CR + description: Clock control register + byte_offset: 0 + fieldset: CR + - name: ICSCR + description: Internal clock sources calibration register + byte_offset: 4 + fieldset: ICSCR + - name: CFGR + description: Clock configuration register + byte_offset: 8 + fieldset: CFGR + - name: PLLCFGR + description: PLL configuration register + byte_offset: 12 + fieldset: PLLCFGR + - name: CIER + description: Clock interrupt enable register + byte_offset: 24 + fieldset: CIER + - name: CIFR + description: Clock interrupt flag register + byte_offset: 28 + access: Read + fieldset: CIFR + - name: CICR + description: Clock interrupt clear register + byte_offset: 32 + access: Write + fieldset: CICR + - name: AHB1RSTR + description: AHB1 peripheral reset register + byte_offset: 40 + fieldset: AHB1RSTR + - name: AHB2RSTR + description: AHB2 peripheral reset register + byte_offset: 44 + fieldset: AHB2RSTR + - name: AHB3RSTR + description: AHB3 peripheral reset register + byte_offset: 48 + fieldset: AHB3RSTR + - name: APB1RSTR1 + description: APB1 peripheral reset register 1 + byte_offset: 56 + fieldset: APB1RSTR1 + - name: APB1RSTR2 + description: APB1 peripheral reset register 2 + byte_offset: 60 + fieldset: APB1RSTR2 + - name: APB2RSTR + description: APB2 peripheral reset register + byte_offset: 64 + fieldset: APB2RSTR + - name: APB3RSTR + description: APB3 peripheral reset register + byte_offset: 68 + fieldset: APB3RSTR + - name: AHB1ENR + description: AHB1 peripheral clock enable register + byte_offset: 72 + fieldset: AHB1ENR + - name: AHB2ENR + description: AHB2 peripheral clock enable register + byte_offset: 76 + fieldset: AHB2ENR + - name: AHB3ENR + description: AHB3 peripheral clock enable register + byte_offset: 80 + fieldset: AHB3ENR + - name: APB1ENR1 + description: APB1 peripheral clock enable register 1 + byte_offset: 88 + fieldset: APB1ENR1 + - name: APB1ENR2 + description: APB1 peripheral clock enable register 2 + byte_offset: 92 + fieldset: APB1ENR2 + - name: APB2ENR + description: APB2 peripheral clock enable register + byte_offset: 96 + fieldset: APB2ENR + - name: APB3ENR + description: APB3 peripheral clock enable register + byte_offset: 100 + fieldset: APB3ENR + - name: AHB1SMENR + description: AHB1 peripheral clocks enable in Sleep modes register + byte_offset: 104 + fieldset: AHB1SMENR + - name: AHB2SMENR + description: AHB2 peripheral clocks enable in Sleep modes register + byte_offset: 108 + fieldset: AHB2SMENR + - name: AHB3SMENR + description: AHB3 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 112 + fieldset: AHB3SMENR + - name: APB1SMENR1 + description: APB1 peripheral clocks enable in Sleep mode register 1 + byte_offset: 120 + fieldset: APB1SMENR1 + - name: APB1SMENR2 + description: APB1 peripheral clocks enable in Sleep mode register 2 + byte_offset: 124 + fieldset: APB1SMENR2 + - name: APB2SMENR + description: APB2 peripheral clocks enable in Sleep mode register + byte_offset: 128 + fieldset: APB2SMENR + - name: APB3SMENR + description: APB3 peripheral clock enable in Sleep mode register + byte_offset: 132 + fieldset: APB3SMENR + - name: CCIPR + description: Peripherals independent clock configuration register + byte_offset: 136 + fieldset: CCIPR + - name: BDCR + description: Backup domain control register + byte_offset: 144 + fieldset: BDCR + - name: CSR + description: Control/status register + byte_offset: 148 + fieldset: CSR + - name: EXTCFGR + description: Extended clock recovery register + byte_offset: 264 + fieldset: EXTCFGR +fieldset/AHB1ENR: + description: AHB1 peripheral clock enable register + fields: + - name: DMA1EN + description: CPU1 DMA1 clock enable + bit_offset: 0 + bit_size: 1 + - name: DMA2EN + description: CPU1 DMA2 clock enable + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1EN + description: CPU1 DMAMUX1 clock enable + bit_offset: 2 + bit_size: 1 + - name: CRCEN + description: CPU1 CRC clock enable + bit_offset: 12 + bit_size: 1 +fieldset/AHB1RSTR: + description: AHB1 peripheral reset register + fields: + - name: DMA1RST + description: DMA1 reset + bit_offset: 0 + bit_size: 1 + - name: DMA2RST + description: DMA2 reset + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1RST + description: DMAMUX1 reset + bit_offset: 2 + bit_size: 1 + - name: CRCRST + description: CRC reset + bit_offset: 12 + bit_size: 1 +fieldset/AHB1SMENR: + description: AHB1 peripheral clocks enable in Sleep modes register + fields: + - name: DMA1SMEN + description: DMA1 clock enable during CPU1 CSleep mode. + bit_offset: 0 + bit_size: 1 + - name: DMA2SMEN + description: DMA2 clock enable during CPU1 CSleep mode + bit_offset: 1 + bit_size: 1 + - name: DMAMUX1SMEN + description: DMAMUX1 clock enable during CPU1 CSleep mode. + bit_offset: 2 + bit_size: 1 + - name: CRCSMEN + description: CRC clock enable during CPU1 CSleep mode. + bit_offset: 12 + bit_size: 1 +fieldset/AHB2ENR: + description: AHB2 peripheral clock enable register + fields: + - name: GPIOAEN + description: CPU1 IO port A clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: CPU1 IO port B clock enable + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: CPU1 IO port C clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIOHEN + description: CPU1 IO port H clock enable + bit_offset: 7 + bit_size: 1 +fieldset/AHB2RSTR: + description: AHB2 peripheral reset register + fields: + - name: GPIOARST + description: IO port A reset + bit_offset: 0 + bit_size: 1 + - name: GPIOBRST + description: IO port B reset + bit_offset: 1 + bit_size: 1 + - name: GPIOCRST + description: IO port C reset + bit_offset: 2 + bit_size: 1 + - name: GPIOHRST + description: IO port H reset + bit_offset: 7 + bit_size: 1 +fieldset/AHB2SMENR: + description: AHB2 peripheral clocks enable in Sleep modes register + fields: + - name: GPIOASMEN + description: IO port A clock enable during CPU1 CSleep mode. + bit_offset: 0 + bit_size: 1 + - name: GPIOBSMEN + description: IO port B clock enable during CPU1 CSleep mode. + bit_offset: 1 + bit_size: 1 + - name: GPIOCSMEN + description: IO port C clock enable during CPU1 CSleep mode. + bit_offset: 2 + bit_size: 1 + - name: GPIOHSMEN + description: IO port H clock enable during CPU1 CSleep mode. + bit_offset: 7 + bit_size: 1 +fieldset/AHB3ENR: + description: AHB3 peripheral clock enable register + fields: + - name: PKAEN + description: PKAEN + bit_offset: 16 + bit_size: 1 + - name: AESEN + description: AESEN + bit_offset: 17 + bit_size: 1 + - name: RNGEN + description: RNGEN + bit_offset: 18 + bit_size: 1 + - name: HSEMEN + description: HSEMEN + bit_offset: 19 + bit_size: 1 + - name: FLASHEN + description: CPU1 Flash interface clock enable + bit_offset: 25 + bit_size: 1 +fieldset/AHB3RSTR: + description: AHB3 peripheral reset register + fields: + - name: PKARST + description: PKARST + bit_offset: 16 + bit_size: 1 + - name: AESRST + description: AESRST + bit_offset: 17 + bit_size: 1 + - name: RNGRST + description: RNGRST + bit_offset: 18 + bit_size: 1 + - name: HSEMRST + description: HSEMRST + bit_offset: 19 + bit_size: 1 + - name: FLASHRST + description: Flash interface reset + bit_offset: 25 + bit_size: 1 +fieldset/AHB3SMENR: + description: AHB3 peripheral clocks enable in Sleep and Stop modes register + fields: + - name: PKASMEN + description: PKA accelerator clock enable during CPU1 CSleep mode. + bit_offset: 16 + bit_size: 1 + - name: AESSMEN + description: AES accelerator clock enable during CPU1 CSleep mode. + bit_offset: 17 + bit_size: 1 + - name: RNGSMEN + description: True RNG clocks enable during CPU1 Csleep and CStop modes + bit_offset: 18 + bit_size: 1 + - name: SRAM1SMEN + description: SRAM1 interface clock enable during CPU1 CSleep mode. + bit_offset: 23 + bit_size: 1 + - name: SRAM2SMEN + description: SRAM2 memory interface clock enable during CPU1 CSleep mode + bit_offset: 24 + bit_size: 1 + - name: FLASHSMEN + description: Flash interface clock enable during CPU1 CSleep mode. + bit_offset: 25 + bit_size: 1 +fieldset/APB1ENR1: + description: APB1 peripheral clock enable register 1 + fields: + - name: TIM2EN + description: CPU1 TIM2 timer clock enable + bit_offset: 0 + bit_size: 1 + - name: RTCAPBEN + description: CPU1 RTC APB clock enable + bit_offset: 10 + bit_size: 1 + - name: WWDGEN + description: CPU1 Window watchdog clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2S2EN + description: CPU1 SPI2S2 clock enable + bit_offset: 14 + bit_size: 1 + - name: USART2EN + description: CPU1 USART2 clock enable + bit_offset: 17 + bit_size: 1 + - name: I2C1EN + description: CPU1 I2C1 clocks enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: CPU1 I2C2 clocks enable + bit_offset: 22 + bit_size: 1 + - name: I2C3EN + description: CPU1 I2C3 clocks enable + bit_offset: 23 + bit_size: 1 + - name: DAC1EN + description: CPU1 DAC1 clock enable + bit_offset: 29 + bit_size: 1 + - name: LPTIM1EN + description: CPU1 Low power timer 1 clocks enable + bit_offset: 31 + bit_size: 1 +fieldset/APB1ENR2: + description: APB1 peripheral clock enable register 2 + fields: + - name: LPUART1EN + description: CPU1 Low power UART 1 clocks enable + bit_offset: 0 + bit_size: 1 + - name: LPTIM2EN + description: CPU1 Low power timer 2 clocks enable + bit_offset: 5 + bit_size: 1 + - name: LPTIM3EN + description: CPU1 Low power timer 3 clocks enable + bit_offset: 6 + bit_size: 1 +fieldset/APB1RSTR1: + description: APB1 peripheral reset register 1 + fields: + - name: TIM2RST + description: TIM2 timer reset + bit_offset: 0 + bit_size: 1 + - name: SPI2S2RST + description: SPI2S2 reset + bit_offset: 14 + bit_size: 1 + - name: USART2RST + description: USART2 reset + bit_offset: 17 + bit_size: 1 + - name: I2C1RST + description: I2C1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C2 reset + bit_offset: 22 + bit_size: 1 + - name: I2C3RST + description: I2C3 reset + bit_offset: 23 + bit_size: 1 + - name: DACRST + description: DAC reset + bit_offset: 29 + bit_size: 1 + - name: LPTIM1RST + description: Low Power Timer 1 reset + bit_offset: 31 + bit_size: 1 +fieldset/APB1RSTR2: + description: APB1 peripheral reset register 2 + fields: + - name: LPUART1RST + description: Low-power UART 1 reset + bit_offset: 0 + bit_size: 1 + - name: LPTIM2RST + description: Low-power timer 2 reset + bit_offset: 5 + bit_size: 1 + - name: LPTIM3RST + description: Low-power timer 3 reset + bit_offset: 6 + bit_size: 1 +fieldset/APB1SMENR1: + description: APB1 peripheral clocks enable in Sleep mode register 1 + fields: + - name: TIM2SMEN + description: TIM2 timer clock enable during CPU1 CSleep mode. + bit_offset: 0 + bit_size: 1 + - name: RTCAPBSMEN + description: RTC bus clock enable during CPU1 CSleep mode. + bit_offset: 10 + bit_size: 1 + - name: WWDGSMEN + description: Window watchdog clocks enable during CPU1 CSleep mode. + bit_offset: 11 + bit_size: 1 + - name: SPI2S2SMEN + description: SPI2S2 clock enable during CPU1 CSleep mode. + bit_offset: 14 + bit_size: 1 + - name: USART2SMEN + description: USART2 clock enable during CPU1 CSleep mode. + bit_offset: 17 + bit_size: 1 + - name: I2C1SMEN + description: I2C1 clock enable during CPU1 Csleep and CStop modes + bit_offset: 21 + bit_size: 1 + - name: I2C2SMEN + description: I2C2 clock enable during CPU1 Csleep and CStop modes + bit_offset: 22 + bit_size: 1 + - name: I2C3SMEN + description: I2C3 clock enable during CPU1 Csleep and CStop modes + bit_offset: 23 + bit_size: 1 + - name: DACSMEN + description: DAC clock enable during CPU1 CSleep mode. + bit_offset: 29 + bit_size: 1 + - name: LPTIM1SMEN + description: Low power timer 1 clock enable during CPU1 Csleep and CStop mode + bit_offset: 31 + bit_size: 1 +fieldset/APB1SMENR2: + description: APB1 peripheral clocks enable in Sleep mode register 2 + fields: + - name: LPUART1SMEN + description: Low power UART 1 clock enable during CPU1 Csleep and CStop modes. + bit_offset: 0 + bit_size: 1 + - name: LPTIM2SMEN + description: Low power timer 2 clock enable during CPU1 Csleep and CStop modes + bit_offset: 5 + bit_size: 1 + - name: LPTIM3SMEN + description: Low power timer 3 clock enable during CPU1 Csleep and CStop modes + bit_offset: 6 + bit_size: 1 +fieldset/APB2ENR: + description: APB2 peripheral clock enable register + fields: + - name: ADCEN + description: CPU1 ADC clocks enable + bit_offset: 9 + bit_size: 1 + - name: TIM1EN + description: CPU1 TIM1 timer clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: CPU1 SPI1 clock enable + bit_offset: 12 + bit_size: 1 + - name: USART1EN + description: CPU1 USART1clocks enable + bit_offset: 14 + bit_size: 1 + - name: TIM16EN + description: CPU1 TIM16 timer clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: CPU1 TIM17 timer clock enable + bit_offset: 18 + bit_size: 1 +fieldset/APB2RSTR: + description: APB2 peripheral reset register + fields: + - name: ADCRST + description: ADC reset + bit_offset: 9 + bit_size: 1 + - name: TIM1RST + description: TIM1 timer reset + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: SPI1 reset + bit_offset: 12 + bit_size: 1 + - name: USART1RST + description: USART1 reset + bit_offset: 14 + bit_size: 1 + - name: TIM16RST + description: TIM16 timer reset + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: TIM17 timer reset + bit_offset: 18 + bit_size: 1 +fieldset/APB2SMENR: + description: APB2 peripheral clocks enable in Sleep mode register + fields: + - name: ADCSMEN + description: ADC clocks enable during CPU1 Csleep and CStop modes + bit_offset: 9 + bit_size: 1 + - name: TIM1SMEN + description: TIM1 timer clock enable during CPU1 CSleep mode. + bit_offset: 11 + bit_size: 1 + - name: SPI1SMEN + description: SPI1 clock enable during CPU1 CSleep mode. + bit_offset: 12 + bit_size: 1 + - name: USART1SMEN + description: USART1 clock enable during CPU1 Csleep and CStop modes. + bit_offset: 14 + bit_size: 1 + - name: TIM16SMEN + description: TIM16 timer clock enable during CPU1 CSleep mode. + bit_offset: 17 + bit_size: 1 + - name: TIM17SMEN + description: TIM17 timer clock enable during CPU1 CSleep mode. + bit_offset: 18 + bit_size: 1 +fieldset/APB3ENR: + description: APB3 peripheral clock enable register + fields: + - name: SUBGHZSPIEN + description: sub-GHz radio SPI clock enable + bit_offset: 0 + bit_size: 1 +fieldset/APB3RSTR: + description: APB3 peripheral reset register + fields: + - name: SUBGHZSPIRST + description: Sub-GHz radio SPI reset + bit_offset: 0 + bit_size: 1 +fieldset/APB3SMENR: + description: APB3 peripheral clock enable in Sleep mode register + fields: + - name: SUBGHZSPISMEN + description: Sub-GHz radio SPI clock enable during Sleep and Stop modes + bit_offset: 0 + bit_size: 1 +fieldset/BDCR: + description: Backup domain control register + fields: + - name: LSEON + description: LSE oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: LSE oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: LSE oscillator bypass + bit_offset: 2 + bit_size: 1 + - name: LSEDRV + description: LSE oscillator drive capability + bit_offset: 3 + bit_size: 2 + - name: LSECSSON + description: CSS on LSE enable + bit_offset: 5 + bit_size: 1 + - name: LSECSSD + description: CSS on LSE failure Detection + bit_offset: 6 + bit_size: 1 + - name: LSESYSEN + description: LSE system clock enable + bit_offset: 7 + bit_size: 1 + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + - name: LSESYSRDY + description: LSE system clock ready + bit_offset: 11 + bit_size: 1 + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: Backup domain software reset + bit_offset: 16 + bit_size: 1 + - name: LSCOEN + description: Low speed clock output enable + bit_offset: 24 + bit_size: 1 + - name: LSCOSEL + description: Low speed clock output selection + bit_offset: 25 + bit_size: 1 +fieldset/CCIPR: + description: Peripherals independent clock configuration register + fields: + - name: USART1SEL + description: USART1 clock source selection + bit_offset: 0 + bit_size: 2 + - name: USART2SEL + description: USART2 clock source selection + bit_offset: 2 + bit_size: 2 + - name: SPI2S2SEL + description: SPI2S2 I2S clock source selection + bit_offset: 8 + bit_size: 2 + - name: LPUART1SEL + description: LPUART1 clock source selection + bit_offset: 10 + bit_size: 2 + - name: I2C1SEL + description: I2C1 clock source selection + bit_offset: 12 + bit_size: 2 + - name: I2C2SEL + description: I2C2 clock source selection + bit_offset: 14 + bit_size: 2 + - name: I2C3SEL + description: I2C3 clock source selection + bit_offset: 16 + bit_size: 2 + - name: LPTIM1SEL + description: Low power timer 1 clock source selection + bit_offset: 18 + bit_size: 2 + - name: LPTIM2SEL + description: Low power timer 2 clock source selection + bit_offset: 20 + bit_size: 2 + - name: LPTIM3SEL + description: Low power timer 3 clock source selection + bit_offset: 22 + bit_size: 2 + - name: ADCSEL + description: ADC clock source selection + bit_offset: 28 + bit_size: 2 + - name: RNGSEL + description: RNG clock source selection + bit_offset: 30 + bit_size: 2 +fieldset/CFGR: + description: Clock configuration register + fields: + - name: SW + description: System clock switch + bit_offset: 0 + bit_size: 2 + - name: SWS + description: System clock switch status + bit_offset: 2 + bit_size: 2 + - name: HPRE + description: "HCLK1 prescaler (CPU1, AHB1, AHB2, and SRAM1.)" + bit_offset: 4 + bit_size: 4 + - name: PPRE1 + description: PCLK1 low-speed prescaler (APB1) + bit_offset: 8 + bit_size: 3 + - name: PPRE2 + description: PCLK2 high-speed prescaler (APB2) + bit_offset: 11 + bit_size: 3 + - name: STOPWUCK + description: Wakeup from Stop and CSS backup clock selection + bit_offset: 15 + bit_size: 1 + - name: HPREF + description: "HCLK1 prescaler flag (CPU1, AHB1, AHB2, and SRAM1)" + bit_offset: 16 + bit_size: 1 + - name: PPRE1F + description: PCLK1 prescaler flag (APB1) + bit_offset: 17 + bit_size: 1 + - name: PPRE2F + description: PCLK2 prescaler flag (APB2) + bit_offset: 18 + bit_size: 1 + - name: MCOSEL + description: Microcontroller clock output + bit_offset: 24 + bit_size: 4 + - name: MCOPRE + description: Microcontroller clock output prescaler + bit_offset: 28 + bit_size: 3 +fieldset/CICR: + description: Clock interrupt clear register + fields: + - name: LSIRDYC + description: LSI ready interrupt clear + bit_offset: 0 + bit_size: 1 + - name: LSERDYC + description: LSE ready interrupt clear + bit_offset: 1 + bit_size: 1 + - name: MSIRDYC + description: MSI ready interrupt clear + bit_offset: 2 + bit_size: 1 + - name: HSIRDYC + description: HSI16 ready interrupt clear + bit_offset: 3 + bit_size: 1 + - name: HSERDYC + description: HSE32 ready interrupt clear + bit_offset: 4 + bit_size: 1 + - name: PLLRDYC + description: PLL ready interrupt clear + bit_offset: 5 + bit_size: 1 + - name: CSSC + description: HSE32 Clock security system interrupt clear + bit_offset: 8 + bit_size: 1 + - name: LSECSSC + description: LSE Clock security system interrupt clear + bit_offset: 9 + bit_size: 1 +fieldset/CIER: + description: Clock interrupt enable register + fields: + - name: LSIRDYIE + description: LSI ready interrupt enable + bit_offset: 0 + bit_size: 1 + - name: LSERDYIE + description: LSE ready interrupt enable + bit_offset: 1 + bit_size: 1 + - name: MSIRDYIE + description: MSI ready interrupt enable + bit_offset: 2 + bit_size: 1 + - name: HSIRDYIE + description: HSI16 ready interrupt enable + bit_offset: 3 + bit_size: 1 + - name: HSERDYIE + description: HSE32 ready interrupt enable + bit_offset: 4 + bit_size: 1 + - name: PLLRDYIE + description: PLL ready interrupt enable + bit_offset: 5 + bit_size: 1 + - name: LSECSSIE + description: LSE clock security system interrupt enable + bit_offset: 9 + bit_size: 1 +fieldset/CIFR: + description: Clock interrupt flag register + fields: + - name: LSIRDYF + description: LSI ready interrupt flag + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE ready interrupt flag + bit_offset: 1 + bit_size: 1 + - name: MSIRDYF + description: MSI ready interrupt flag + bit_offset: 2 + bit_size: 1 + - name: HSIRDYF + description: HSI16 ready interrupt flag + bit_offset: 3 + bit_size: 1 + - name: HSERDYF + description: HSE32 ready interrupt flag + bit_offset: 4 + bit_size: 1 + - name: PLLRDYF + description: PLL ready interrupt flag + bit_offset: 5 + bit_size: 1 + - name: CSSF + description: HSE32 Clock security system interrupt flag + bit_offset: 8 + bit_size: 1 + - name: LSECSSF + description: LSE Clock security system interrupt flag + bit_offset: 9 + bit_size: 1 +fieldset/CR: + description: Clock control register + fields: + - name: MSION + description: MSI clock enable + bit_offset: 0 + bit_size: 1 + - name: MSIRDY + description: MSI clock ready flag (After reset this bit will be read 1 once the MSI is ready) + bit_offset: 1 + bit_size: 1 + - name: MSIPLLEN + description: MSI clock PLL enable + bit_offset: 2 + bit_size: 1 + - name: MSIRGSEL + description: MSI range control selection + bit_offset: 3 + bit_size: 1 + - name: MSIRANGE + description: MSI clock ranges + bit_offset: 4 + bit_size: 4 + - name: HSION + description: HSI16 clock enable + bit_offset: 8 + bit_size: 1 + - name: HSIKERON + description: HSI16 always enable for peripheral kernel clocks. + bit_offset: 9 + bit_size: 1 + - name: HSIRDY + description: HSI16 clock ready flag. (After wakeup from Stop this bit will be read 1 once the HSI16 is ready) + bit_offset: 10 + bit_size: 1 + - name: HSIASFS + description: HSI16 automatic start from Stop + bit_offset: 11 + bit_size: 1 + - name: HSIKERDY + description: HSI16 kernel clock ready flag for peripherals requests. + bit_offset: 12 + bit_size: 1 + - name: HSEON + description: HSE32 clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: HSE32 clock ready flag + bit_offset: 17 + bit_size: 1 + - name: CSSON + description: HSE32 Clock security system enable + bit_offset: 19 + bit_size: 1 + - name: HSEPRE + description: HSE32 sysclk prescaler + bit_offset: 20 + bit_size: 1 + - name: HSEBYPPWR + description: Enable HSE32 VDDTCXO output on package pin PB0-VDDTCXO. + bit_offset: 21 + bit_size: 1 + - name: PLLON + description: Main PLL enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: Main PLL clock ready flag + bit_offset: 25 + bit_size: 1 +fieldset/CSR: + description: Control/status register + fields: + - name: LSION + description: LSI oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: LSI oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSIPRE + description: LSI frequency prescaler + bit_offset: 4 + bit_size: 1 + - name: MSISRANGE + description: MSI clock ranges + bit_offset: 8 + bit_size: 4 + - name: RFRSTF + description: Radio in reset status flag + bit_offset: 14 + bit_size: 1 + - name: RFRST + description: Radio reset + bit_offset: 15 + bit_size: 1 + - name: RMVF + description: Remove reset flag + bit_offset: 23 + bit_size: 1 + - name: RFILARSTF + description: Radio illegal access flag + bit_offset: 24 + bit_size: 1 + - name: OBLRSTF + description: Option byte loader reset flag + bit_offset: 25 + bit_size: 1 + - name: PINRSTF + description: Pin reset flag + bit_offset: 26 + bit_size: 1 + - name: BORRSTF + description: BOR flag + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: Independent window watchdog reset flag + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 +fieldset/EXTCFGR: + description: Extended clock recovery register + fields: + - name: SHDHPRE + description: "HCLK3 shared prescaler (AHB3, Flash, and SRAM2)" + bit_offset: 0 + bit_size: 4 + - name: SHDHPREF + description: "HCLK3 shared prescaler flag (AHB3, Flash, and SRAM2)" + bit_offset: 16 + bit_size: 1 +fieldset/ICSCR: + description: Internal clock sources calibration register + fields: + - name: MSICAL + description: MSI clock calibration + bit_offset: 0 + bit_size: 8 + - name: MSITRIM + description: MSI clock trimming + bit_offset: 8 + bit_size: 8 + - name: HSICAL + description: HSI16 clock calibration + bit_offset: 16 + bit_size: 8 + - name: HSITRIM + description: HSI16 clock trimming + bit_offset: 24 + bit_size: 7 +fieldset/PLLCFGR: + description: PLL configuration register + fields: + - name: PLLSRC + description: Main PLL entry clock source + bit_offset: 0 + bit_size: 2 + - name: PLLM + description: Division factor for the main PLL input clock + bit_offset: 4 + bit_size: 3 + - name: PLLN + description: Main PLL multiplication factor for VCO + bit_offset: 8 + bit_size: 7 + - name: PLLPEN + description: Main PLL PLLPCLK output enable + bit_offset: 16 + bit_size: 1 + - name: PLLP + description: Main PLL division factor for PLLPCLK. + bit_offset: 17 + bit_size: 5 + - name: PLLQEN + description: Main PLL PLLQCLK output enable + bit_offset: 24 + bit_size: 1 + - name: PLLQ + description: Main PLL division factor for PLLQCLK + bit_offset: 25 + bit_size: 3 + - name: PLLREN + description: Main PLL PLLRCLK output enable + bit_offset: 28 + bit_size: 1 + - name: PLLR + description: Main PLL division factor for PLLRCLK + bit_offset: 29 + bit_size: 3 diff --git a/parse.py b/parse.py index d6adfda..d12dbb6 100755 --- a/parse.py +++ b/parse.py @@ -352,18 +352,26 @@ perimap = [ ('STM32G0.*:SYS:.*', 'syscfg_g0/SYSCFG'), ('STM32WB55.*:SYS:.*', 'syscfg_wb55/SYSCFG'), ('STM32WL.*:SYS:.*', 'syscfg_wl5x/SYSCFG'), - ('STM32L0.*:RCC:.*', 'rcc_l0/RCC'), - ('STM32L4.*:RCC:.*', 'rcc_l4/RCC'), - ('STM32F410.*:RCC:.*', 'rcc_f410/RCC'), - ('STM32F4.*:RCC:.*', 'rcc_f4/RCC'), - ('STM32WL.*:RCC:.*', 'rcc_wl5x/RCC'), + ('STM32F0.0.*:RCC:.*', 'rcc_f0x0/RCC'), ('STM32F0.*:RCC:.*', 'rcc_f0/RCC'), ('STM32F1.*:RCC:.*', 'rcc_f1/RCC'), + ('STM32F3.*:RCC:.*', 'rcc_f3/RCC'), + ('STM32F410.*:RCC:.*', 'rcc_f410/RCC'), + ('STM32F4.*:RCC:.*', 'rcc_f4/RCC'), + ('STM32F7.*:RCC:.*', 'rcc_f7/RCC'), ('STM32G0.*:RCC:.*', 'rcc_g0/RCC'), - ('.*:STM32H7AB_rcc_v1_0', ''), # rcc_h7ab/RCC - ('.*:STM32H7_rcc_v1_0', 'rcc_h7/RCC'), - ('.*:STM32W_rcc_v1_0', 'rcc_wb55/RCC'), + ('STM32G4.*:RCC:.*', 'rcc_g4/RCC'), + ('STM32H7[AB].*:RCC:.*', 'rcc_h7ab/RCC'), + ('STM32H7.*:RCC:.*', 'rcc_h7/RCC'), + ('STM32L0.*:RCC:.*', 'rcc_l0/RCC'), + ('STM32L1.*:RCC:.*', 'rcc_l1/RCC'), + ('STM32L4.*:RCC:.*', 'rcc_l4/RCC'), + ('STM32L5.*:RCC:.*', 'rcc_l5/RCC'), + ('STM32WB.*:RCC:.*', 'rcc_wb/RCC'), + ('STM32WL5.*:RCC:.*', 'rcc_wl5/RCC'), + ('STM32WLE.*:RCC:.*', 'rcc_wle/RCC'), + ('.*:STM32L0_crs_v1_0', 'crs_l0/CRS'), ('.*SDMMC:sdmmc2_v1_0', 'sdmmc_v2/SDMMC'), ('STM32H7(42|43|53|50).*:STM32H7_pwr_v1_0', 'pwr_h7/PWR'),