rcc: add more mux data

This commit is contained in:
xoviat 2023-10-14 11:41:21 -05:00
parent 76adedfbf2
commit 68d77f487b
3 changed files with 26 additions and 6 deletions

View File

@ -2431,7 +2431,7 @@ enum/NSPRIV:
enum/OCTOSPISEL: enum/OCTOSPISEL:
bit_size: 2 bit_size: 2
variants: variants:
- name: RCC_HCLK4 - name: AHB4
description: rcc_hclk4 selected as kernel clock (default after reset) description: rcc_hclk4 selected as kernel clock (default after reset)
value: 0 value: 0
- name: PLL1_Q - name: PLL1_Q
@ -3910,7 +3910,7 @@ enum/PPRE:
enum/RNGSEL: enum/RNGSEL:
bit_size: 2 bit_size: 2
variants: variants:
- name: HSI48_KER - name: HSI48
description: hsi48_ker_ck selected as kernel clock (default after reset) description: hsi48_ker_ck selected as kernel clock (default after reset)
value: 0 value: 0
- name: PLL1_Q - name: PLL1_Q

View File

@ -3078,7 +3078,7 @@ enum/PPRE:
enum/RNGSEL: enum/RNGSEL:
bit_size: 2 bit_size: 2
variants: variants:
- name: HSI48_KER - name: HSI48
description: hsi48_ker_ck selected as kernel clock (default after reset) description: hsi48_ker_ck selected as kernel clock (default after reset)
value: 0 value: 0
- name: PLL1_Q - name: PLL1_Q

View File

@ -2,6 +2,7 @@ use std::collections::{HashMap, HashSet};
use anyhow::{anyhow, Ok}; use anyhow::{anyhow, Ok};
use chiptool::ir::{BlockItemInner, Enum}; use chiptool::ir::{BlockItemInner, Enum};
use stm32_data_serde::chip::core::peripheral::rcc::Mux;
use crate::regex; use crate::regex;
use crate::registers::Registers; use crate::registers::Registers;
@ -17,16 +18,21 @@ impl PeripheralToClock {
for (rcc_name, ir) in &registers.registers { for (rcc_name, ir) in &registers.registers {
if let Some(rcc_name) = rcc_name.strip_prefix("rcc_") { if let Some(rcc_name) = rcc_name.strip_prefix("rcc_") {
let checked_rccs = HashSet::from(["h5", "h50", "h7"]); let checked_rccs = HashSet::from(["h5", "h50", "h7", "h7ab", "h7rm0433", "g4"]);
let prohibited_variants = HashSet::from([ let prohibited_variants = HashSet::from([
"RCC_PCLK1", "RCC_PCLK1",
"RCC_PCLK2", "RCC_PCLK2",
"RCC_PCLK3", "RCC_PCLK3",
"RCC_PCLK4", "RCC_PCLK4",
"HSI_KER", "HSI_KER",
"HSI48_KER",
"CSI_KER", "CSI_KER",
"LSI_KER", "LSI_KER",
"PER_CLK", "PER_CLK",
"RCC_HCLK1",
"RCC_HCLK2",
"RCC_HCLK3",
"RCC_HCLK4",
]); ]);
let rcc_enum_map: HashMap<&String, HashMap<&String, &Enum>> = { let rcc_enum_map: HashMap<&String, HashMap<&String, &Enum>> = {
@ -73,7 +79,7 @@ impl PeripheralToClock {
for v in &enumm.variants { for v in &enumm.variants {
if prohibited_variants.contains(v.name.as_str()) { if prohibited_variants.contains(v.name.as_str()) {
return Err(anyhow!( return Err(anyhow!(
"rcc: prohibited variant name {} for {}", "rcc: prohibited variant name {} for rcc_{}",
v.name.as_str(), v.name.as_str(),
rcc_name rcc_name
)); ));
@ -97,7 +103,21 @@ impl PeripheralToClock {
family_muxes.insert( family_muxes.insert(
peri.to_string(), peri.to_string(),
stm32_data_serde::chip::core::peripheral::rcc::Mux { Mux {
register: reg.to_ascii_lowercase(),
field: field.name.to_ascii_lowercase(),
},
);
}
}
} else if let Some(_) = regex!(r"^fieldset/CFGR\d?$").captures(&key) {
for field in &body.fields {
if let Some(peri) = field.name.strip_suffix("SW") {
check_mux(reg, &field.name)?;
family_muxes.insert(
peri.to_string(),
Mux {
register: reg.to_ascii_lowercase(), register: reg.to_ascii_lowercase(),
field: field.name.to_ascii_lowercase(), field: field.name.to_ascii_lowercase(),
}, },