From 68d77f487bb36ea61ffb9ad348ac319ea1544282 Mon Sep 17 00:00:00 2001
From: xoviat <xoviat@users.noreply.github.com>
Date: Sat, 14 Oct 2023 11:41:21 -0500
Subject: [PATCH] rcc: add more mux data

---
 data/registers/rcc_h5.yaml  |  4 ++--
 data/registers/rcc_h50.yaml |  2 +-
 stm32-data-gen/src/rcc.rs   | 26 +++++++++++++++++++++++---
 3 files changed, 26 insertions(+), 6 deletions(-)

diff --git a/data/registers/rcc_h5.yaml b/data/registers/rcc_h5.yaml
index 2bae245..32723b2 100644
--- a/data/registers/rcc_h5.yaml
+++ b/data/registers/rcc_h5.yaml
@@ -2431,7 +2431,7 @@ enum/NSPRIV:
 enum/OCTOSPISEL:
   bit_size: 2
   variants:
-  - name: RCC_HCLK4
+  - name: AHB4
     description: rcc_hclk4 selected as kernel clock (default after reset)
     value: 0
   - name: PLL1_Q
@@ -3910,7 +3910,7 @@ enum/PPRE:
 enum/RNGSEL:
   bit_size: 2
   variants:
-  - name: HSI48_KER
+  - name: HSI48
     description: hsi48_ker_ck selected as kernel clock (default after reset)
     value: 0
   - name: PLL1_Q
diff --git a/data/registers/rcc_h50.yaml b/data/registers/rcc_h50.yaml
index ed87a15..989303e 100644
--- a/data/registers/rcc_h50.yaml
+++ b/data/registers/rcc_h50.yaml
@@ -3078,7 +3078,7 @@ enum/PPRE:
 enum/RNGSEL:
   bit_size: 2
   variants:
-  - name: HSI48_KER
+  - name: HSI48
     description: hsi48_ker_ck selected as kernel clock (default after reset)
     value: 0
   - name: PLL1_Q
diff --git a/stm32-data-gen/src/rcc.rs b/stm32-data-gen/src/rcc.rs
index 86a6467..6b1d8f1 100644
--- a/stm32-data-gen/src/rcc.rs
+++ b/stm32-data-gen/src/rcc.rs
@@ -2,6 +2,7 @@ use std::collections::{HashMap, HashSet};
 
 use anyhow::{anyhow, Ok};
 use chiptool::ir::{BlockItemInner, Enum};
+use stm32_data_serde::chip::core::peripheral::rcc::Mux;
 
 use crate::regex;
 use crate::registers::Registers;
@@ -17,16 +18,21 @@ impl PeripheralToClock {
 
         for (rcc_name, ir) in &registers.registers {
             if let Some(rcc_name) = rcc_name.strip_prefix("rcc_") {
-                let checked_rccs = HashSet::from(["h5", "h50", "h7"]);
+                let checked_rccs = HashSet::from(["h5", "h50", "h7", "h7ab", "h7rm0433", "g4"]);
                 let prohibited_variants = HashSet::from([
                     "RCC_PCLK1",
                     "RCC_PCLK2",
                     "RCC_PCLK3",
                     "RCC_PCLK4",
                     "HSI_KER",
+                    "HSI48_KER",
                     "CSI_KER",
                     "LSI_KER",
                     "PER_CLK",
+                    "RCC_HCLK1",
+                    "RCC_HCLK2",
+                    "RCC_HCLK3",
+                    "RCC_HCLK4",
                 ]);
 
                 let rcc_enum_map: HashMap<&String, HashMap<&String, &Enum>> = {
@@ -73,7 +79,7 @@ impl PeripheralToClock {
                     for v in &enumm.variants {
                         if prohibited_variants.contains(v.name.as_str()) {
                             return Err(anyhow!(
-                                "rcc: prohibited variant name {} for {}",
+                                "rcc: prohibited variant name {} for rcc_{}",
                                 v.name.as_str(),
                                 rcc_name
                             ));
@@ -97,7 +103,21 @@ impl PeripheralToClock {
 
                                 family_muxes.insert(
                                     peri.to_string(),
-                                    stm32_data_serde::chip::core::peripheral::rcc::Mux {
+                                    Mux {
+                                        register: reg.to_ascii_lowercase(),
+                                        field: field.name.to_ascii_lowercase(),
+                                    },
+                                );
+                            }
+                        }
+                    } else if let Some(_) = regex!(r"^fieldset/CFGR\d?$").captures(&key) {
+                        for field in &body.fields {
+                            if let Some(peri) = field.name.strip_suffix("SW") {
+                                check_mux(reg, &field.name)?;
+
+                                family_muxes.insert(
+                                    peri.to_string(),
+                                    Mux {
                                         register: reg.to_ascii_lowercase(),
                                         field: field.name.to_ascii_lowercase(),
                                     },