Add F0 syscfg
This commit is contained in:
Thales Fragoso
Dario Nieuwenhuis
parent
26e4f541ba
commit
6656c5c059
457
data/registers/syscfg_f0.yaml
Normal file
457
data/registers/syscfg_f0.yaml
Normal file
@ -0,0 +1,457 @@
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---
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block/SYSCFG:
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description: System configuration controller
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items:
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- name: CFGR1
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description: configuration register 1
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byte_offset: 0
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fieldset: CFGR1
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- name: EXTICR
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description: external interrupt configuration register 1
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array:
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len: 4
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stride: 4
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byte_offset: 8
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fieldset: EXTICR
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- name: CFGR2
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description: configuration register 2
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byte_offset: 24
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fieldset: CFGR2
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fieldset/CFGR1:
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description: configuration register 1
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fields:
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- name: MEM_MODE
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description: Memory mapping selection bits
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bit_offset: 0
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bit_size: 2
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enum: MEM_MODE
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- name: PA11_PA12_RMP
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description: PA11 and PA12 remapping bit for small packages (28 and 20 pins)
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bit_offset: 4
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bit_size: 1
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enum: PA11_PA12_RMP
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- name: IR_MOD
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description: IR Modulation Envelope signal selection
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bit_offset: 6
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bit_size: 2
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enum: IR_MOD
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- name: ADC_DMA_RMP
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description: ADC DMA remapping bit
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bit_offset: 8
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bit_size: 1
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enum: ADC_DMA_RMP
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- name: USART1_TX_DMA_RMP
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description: USART1_TX DMA remapping bit
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bit_offset: 9
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bit_size: 1
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enum: USART1_TX_DMA_RMP
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- name: USART1_RX_DMA_RMP
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description: USART1_RX DMA request remapping bit
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bit_offset: 10
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bit_size: 1
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enum: USART1_RX_DMA_RMP
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- name: TIM16_DMA_RMP
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description: TIM16 DMA request remapping bit
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bit_offset: 11
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bit_size: 1
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enum: TIM16_DMA_RMP
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- name: TIM17_DMA_RMP
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description: TIM17 DMA request remapping bit
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bit_offset: 12
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bit_size: 1
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enum: TIM17_DMA_RMP
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- name: TIM16_DMA_RMP2
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description: TIM16 alternate DMA request remapping bit
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bit_offset: 13
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bit_size: 1
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enum: TIM16_DMA_RMP2
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- name: TIM17_DMA_RMP2
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description: TIM17 alternate DMA request remapping bit
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bit_offset: 14
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bit_size: 1
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enum: TIM17_DMA_RMP2
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- name: I2C_PB6_FMP
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description: Fast Mode Plus (FM plus) driving capability activation bits.
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bit_offset: 16
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bit_size: 1
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enum: I2C_PB6_FMP
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- name: I2C_PB7_FMP
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description: Fast Mode Plus (FM+) driving capability activation bits.
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bit_offset: 17
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bit_size: 1
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enum: I2C_PB7_FMP
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- name: I2C_PB8_FMP
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description: Fast Mode Plus (FM+) driving capability activation bits.
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bit_offset: 18
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bit_size: 1
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enum: I2C_PB8_FMP
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- name: I2C_PB9_FMP
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description: Fast Mode Plus (FM+) driving capability activation bits.
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bit_offset: 19
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bit_size: 1
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enum: I2C_PB9_FMP
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- name: I2C1_FMP
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description: FM+ driving capability activation for I2C1
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bit_offset: 20
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bit_size: 1
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enum: I2C1_FMP
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- name: I2C2_FMP
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description: FM+ driving capability activation for I2C2
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bit_offset: 21
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bit_size: 1
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enum: I2C2_FMP
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- name: I2C_PA9_FMP
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description: Fast Mode Plus (FM+) driving capability activation bits
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bit_offset: 22
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bit_size: 1
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enum: I2C_PA9_FMP
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- name: I2C_PA10_FMP
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description: Fast Mode Plus (FM+) driving capability activation bits
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bit_offset: 23
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bit_size: 1
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enum: I2C_PA10_FMP
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- name: SPI2_DMA_RMP
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description: SPI2 DMA request remapping bit
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bit_offset: 24
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bit_size: 1
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enum: SPI2_DMA_RMP
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- name: USART2_DMA_RMP
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description: USART2 DMA request remapping bit
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bit_offset: 25
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bit_size: 1
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enum: USART2_DMA_RMP
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- name: USART3_DMA_RMP
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description: USART3 DMA request remapping bit
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bit_offset: 26
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bit_size: 1
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enum: USART3_DMA_RMP
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- name: I2C1_DMA_RMP
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description: I2C1 DMA request remapping bit
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bit_offset: 27
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bit_size: 1
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enum: I2C1_DMA_RMP
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- name: TIM1_DMA_RMP
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description: TIM1 DMA request remapping bit
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bit_offset: 28
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bit_size: 1
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enum: TIM1_DMA_RMP
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- name: TIM2_DMA_RMP
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description: TIM2 DMA request remapping bit
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bit_offset: 29
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bit_size: 1
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enum: TIM2_DMA_RMP
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- name: TIM3_DMA_RMP
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description: TIM3 DMA request remapping bit
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bit_offset: 30
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bit_size: 1
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enum: TIM3_DMA_RMP
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fieldset/CFGR2:
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description: configuration register 2
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fields:
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- name: LOCKUP_LOCK
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description: Cortex-M0 LOCKUP bit enable bit
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bit_offset: 0
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bit_size: 1
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enum: LOCKUP_LOCK
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- name: SRAM_PARITY_LOCK
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description: SRAM parity lock bit
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bit_offset: 1
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bit_size: 1
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enum: SRAM_PARITY_LOCK
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- name: PVD_LOCK
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description: PVD lock enable bit
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bit_offset: 2
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bit_size: 1
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enum: PVD_LOCK
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- name: SRAM_PEF
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description: SRAM parity flag
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bit_offset: 8
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bit_size: 1
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enum_read: SRAM_PEFR
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enum_write: SRAM_PEFW
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fieldset/EXTICR:
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description: external interrupt configuration register 1
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fields:
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- name: EXTI
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description: EXTI configuration bits
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bit_offset: 0
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bit_size: 4
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array:
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len: 4
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stride: 4
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enum/ADC_DMA_RMP:
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bit_size: 1
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variants:
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- name: NotRemapped
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description: ADC DMA request mapped on DMA channel 1
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value: 0
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- name: Remapped
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description: ADC DMA request mapped on DMA channel 2
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value: 1
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enum/I2C1_DMA_RMP:
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bit_size: 1
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variants:
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- name: NotRemapped
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description: I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively
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value: 0
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- name: Remapped
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description: I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively
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value: 1
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enum/I2C1_FMP:
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bit_size: 1
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variants:
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- name: Standard
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description: FM+ mode is controlled by I2C_Pxx_FMP bits only
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value: 0
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- name: FMP
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description: FM+ mode is enabled on all I2C1 pins selected through selection bits in GPIOx_AFR registers
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value: 1
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enum/I2C2_FMP:
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bit_size: 1
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variants:
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- name: Standard
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description: FM+ mode is controlled by I2C_Pxx_FMP bits only
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value: 0
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- name: FMP
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description: FM+ mode is enabled on all I2C2 pins selected through selection bits in GPIOx_AFR registers
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value: 1
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enum/I2C_PA10_FMP:
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bit_size: 1
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variants:
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- name: Standard
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description: PA10 pin operate in standard mode
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value: 0
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- name: FMP
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description: I2C FM+ mode enabled on PA10 and the Speed control is bypassed
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value: 1
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enum/I2C_PA9_FMP:
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bit_size: 1
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variants:
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- name: Standard
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description: PA9 pin operate in standard mode
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value: 0
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- name: FMP
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description: I2C FM+ mode enabled on PA9 and the Speed control is bypassed
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value: 1
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enum/I2C_PB6_FMP:
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bit_size: 1
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variants:
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- name: Standard
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description: PB6 pin operate in standard mode
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value: 0
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- name: FMP
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description: I2C FM+ mode enabled on PB6 and the Speed control is bypassed
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value: 1
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enum/I2C_PB7_FMP:
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bit_size: 1
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variants:
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- name: Standard
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description: PB7 pin operate in standard mode
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value: 0
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- name: FMP
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description: I2C FM+ mode enabled on PB7 and the Speed control is bypassed
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value: 1
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enum/I2C_PB8_FMP:
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bit_size: 1
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variants:
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- name: Standard
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description: PB8 pin operate in standard mode
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value: 0
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- name: FMP
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description: I2C FM+ mode enabled on PB8 and the Speed control is bypassed
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value: 1
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enum/I2C_PB9_FMP:
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bit_size: 1
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variants:
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- name: Standard
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description: PB9 pin operate in standard mode
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value: 0
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- name: FMP
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description: I2C FM+ mode enabled on PB9 and the Speed control is bypassed
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value: 1
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enum/IR_MOD:
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bit_size: 2
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variants:
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- name: TIM16
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description: TIM16 selected
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value: 0
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- name: USART1
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description: USART1 selected
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value: 1
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- name: USART4
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description: USART4 selected
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value: 2
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enum/LOCKUP_LOCK:
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bit_size: 1
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variants:
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- name: Disconnected
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description: Cortex-M0 LOCKUP output disconnected from TIM1/15/16/17 Break input
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value: 0
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- name: Connected
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description: Cortex-M0 LOCKUP output connected to TIM1/15/16/17 Break input
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value: 1
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enum/MEM_MODE:
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bit_size: 2
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variants:
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- name: MainFlash
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description: Main Flash memory mapped at 0x0000_0000
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value: 0
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- name: SystemFlash
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description: System Flash memory mapped at 0x0000_0000
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value: 1
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- name: MainFlash2
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description: Main Flash memory mapped at 0x0000_0000
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value: 2
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- name: SRAM
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description: Embedded SRAM mapped at 0x0000_0000
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value: 3
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enum/PA11_PA12_RMP:
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bit_size: 1
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variants:
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- name: NotRemapped
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description: Pin pair PA9/PA10 mapped on the pins
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value: 0
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- name: Remapped
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description: Pin pair PA11/PA12 mapped instead of PA9/PA10
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value: 1
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enum/PVD_LOCK:
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bit_size: 1
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variants:
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- name: Disconnected
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description: PVD interrupt disconnected from TIM1/15/16/17 Break input
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value: 0
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- name: Connected
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description: PVD interrupt connected to TIM1/15/16/17 Break input
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value: 1
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enum/SPI2_DMA_RMP:
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bit_size: 1
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variants:
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- name: NotRemapped
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description: SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively
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value: 0
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- name: Remapped
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description: SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively
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value: 1
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enum/SRAM_PARITY_LOCK:
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bit_size: 1
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variants:
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- name: Disconnected
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description: SRAM parity error disconnected from TIM1/15/16/17 Break input
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value: 0
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- name: Connected
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description: SRAM parity error connected to TIM1/15/16/17 Break input
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value: 1
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enum/SRAM_PEFR:
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bit_size: 1
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variants:
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- name: NoParityError
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description: No SRAM parity error detected
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value: 0
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- name: ParityErrorDetected
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description: SRAM parity error detected
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value: 1
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enum/SRAM_PEFW:
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bit_size: 1
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variants:
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- name: Clear
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description: Clear SRAM parity error flag
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value: 1
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enum/TIM16_DMA_RMP:
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bit_size: 1
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variants:
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- name: NotRemapped
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description: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 3
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value: 0
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- name: Remapped
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description: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 4
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value: 1
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enum/TIM16_DMA_RMP2:
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bit_size: 1
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variants:
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- name: NotAlternateRemapped
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description: TIM16 DMA request mapped according to TIM16_DMA_RMP bit
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value: 0
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- name: AlternateRemapped
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description: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 6
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value: 1
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enum/TIM17_DMA_RMP:
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bit_size: 1
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variants:
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- name: NotRemapped
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description: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 1
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value: 0
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- name: Remapped
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description: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 2
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value: 1
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enum/TIM17_DMA_RMP2:
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bit_size: 1
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variants:
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- name: NotAlternateRemapped
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description: TIM17 DMA request mapped according to TIM16_DMA_RMP bit
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value: 0
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- name: AlternateRemapped
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description: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 7
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value: 1
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enum/TIM1_DMA_RMP:
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bit_size: 1
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variants:
|
||||||
|
- name: NotRemapped
|
||||||
|
description: "TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively"
|
||||||
|
value: 0
|
||||||
|
- name: Remapped
|
||||||
|
description: "TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6"
|
||||||
|
value: 1
|
||||||
|
enum/TIM2_DMA_RMP:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: NotRemapped
|
||||||
|
description: TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively
|
||||||
|
value: 0
|
||||||
|
- name: Remapped
|
||||||
|
description: TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7
|
||||||
|
value: 1
|
||||||
|
enum/TIM3_DMA_RMP:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: NotRemapped
|
||||||
|
description: TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4
|
||||||
|
value: 0
|
||||||
|
- name: Remapped
|
||||||
|
description: TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6
|
||||||
|
value: 1
|
||||||
|
enum/USART1_RX_DMA_RMP:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: NotRemapped
|
||||||
|
description: USART1_RX DMA request mapped on DMA channel 3
|
||||||
|
value: 0
|
||||||
|
- name: Remapped
|
||||||
|
description: USART1_RX DMA request mapped on DMA channel 5
|
||||||
|
value: 1
|
||||||
|
enum/USART1_TX_DMA_RMP:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: NotRemapped
|
||||||
|
description: USART1_TX DMA request mapped on DMA channel 2
|
||||||
|
value: 0
|
||||||
|
- name: Remapped
|
||||||
|
description: USART1_TX DMA request mapped on DMA channel 4
|
||||||
|
value: 1
|
||||||
|
enum/USART2_DMA_RMP:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: NotRemapped
|
||||||
|
description: USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively
|
||||||
|
value: 0
|
||||||
|
- name: Remapped
|
||||||
|
description: USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively
|
||||||
|
value: 1
|
||||||
|
enum/USART3_DMA_RMP:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: NotRemapped
|
||||||
|
description: USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively (or simply disabled on STM32F0x0)
|
||||||
|
value: 0
|
||||||
|
- name: Remapped
|
||||||
|
description: USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively
|
||||||
|
value: 1
|
||||||
1
parse.py
1
parse.py
@ -311,6 +311,7 @@ perimap = [
|
|||||||
('.*:ADC:aditf5_v2_0', 'adc_v3/ADC'),
|
('.*:ADC:aditf5_v2_0', 'adc_v3/ADC'),
|
||||||
('.*:ADC_COMMON:aditf5_v2_0', 'adccommon_v3/ADC_COMMON'),
|
('.*:ADC_COMMON:aditf5_v2_0', 'adccommon_v3/ADC_COMMON'),
|
||||||
('.*:ADC_COMMON:aditf4_v3_0_WL', 'adccommon_v3/ADC_COMMON'),
|
('.*:ADC_COMMON:aditf4_v3_0_WL', 'adccommon_v3/ADC_COMMON'),
|
||||||
|
('STM32F0.*:SYS:.*', 'syscfg_f0/SYSCFG'),
|
||||||
('STM32F4.*:SYS:.*', 'syscfg_f4/SYSCFG'),
|
('STM32F4.*:SYS:.*', 'syscfg_f4/SYSCFG'),
|
||||||
('STM32L4.*:SYS:.*', 'syscfg_l4/SYSCFG'),
|
('STM32L4.*:SYS:.*', 'syscfg_l4/SYSCFG'),
|
||||||
('STM32L0.*:SYS:.*', 'syscfg_l0/SYSCFG'),
|
('STM32L0.*:SYS:.*', 'syscfg_l0/SYSCFG'),
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user