From 6656c5c059dff0bb68d1c52adf2fcb6a8f5599ca Mon Sep 17 00:00:00 2001 From: Thales Fragoso Date: Tue, 22 Jun 2021 16:31:21 -0300 Subject: [PATCH] Add F0 syscfg --- data/registers/syscfg_f0.yaml | 457 ++++++++++++++++++++++++++++++++++ parse.py | 1 + 2 files changed, 458 insertions(+) create mode 100644 data/registers/syscfg_f0.yaml diff --git a/data/registers/syscfg_f0.yaml b/data/registers/syscfg_f0.yaml new file mode 100644 index 0000000..ec2b981 --- /dev/null +++ b/data/registers/syscfg_f0.yaml @@ -0,0 +1,457 @@ +--- +block/SYSCFG: + description: System configuration controller + items: + - name: CFGR1 + description: configuration register 1 + byte_offset: 0 + fieldset: CFGR1 + - name: EXTICR + description: external interrupt configuration register 1 + array: + len: 4 + stride: 4 + byte_offset: 8 + fieldset: EXTICR + - name: CFGR2 + description: configuration register 2 + byte_offset: 24 + fieldset: CFGR2 +fieldset/CFGR1: + description: configuration register 1 + fields: + - name: MEM_MODE + description: Memory mapping selection bits + bit_offset: 0 + bit_size: 2 + enum: MEM_MODE + - name: PA11_PA12_RMP + description: PA11 and PA12 remapping bit for small packages (28 and 20 pins) + bit_offset: 4 + bit_size: 1 + enum: PA11_PA12_RMP + - name: IR_MOD + description: IR Modulation Envelope signal selection + bit_offset: 6 + bit_size: 2 + enum: IR_MOD + - name: ADC_DMA_RMP + description: ADC DMA remapping bit + bit_offset: 8 + bit_size: 1 + enum: ADC_DMA_RMP + - name: USART1_TX_DMA_RMP + description: USART1_TX DMA remapping bit + bit_offset: 9 + bit_size: 1 + enum: USART1_TX_DMA_RMP + - name: USART1_RX_DMA_RMP + description: USART1_RX DMA request remapping bit + bit_offset: 10 + bit_size: 1 + enum: USART1_RX_DMA_RMP + - name: TIM16_DMA_RMP + description: TIM16 DMA request remapping bit + bit_offset: 11 + bit_size: 1 + enum: TIM16_DMA_RMP + - name: TIM17_DMA_RMP + description: TIM17 DMA request remapping bit + bit_offset: 12 + bit_size: 1 + enum: TIM17_DMA_RMP + - name: TIM16_DMA_RMP2 + description: TIM16 alternate DMA request remapping bit + bit_offset: 13 + bit_size: 1 + enum: TIM16_DMA_RMP2 + - name: TIM17_DMA_RMP2 + description: TIM17 alternate DMA request remapping bit + bit_offset: 14 + bit_size: 1 + enum: TIM17_DMA_RMP2 + - name: I2C_PB6_FMP + description: Fast Mode Plus (FM plus) driving capability activation bits. + bit_offset: 16 + bit_size: 1 + enum: I2C_PB6_FMP + - name: I2C_PB7_FMP + description: Fast Mode Plus (FM+) driving capability activation bits. + bit_offset: 17 + bit_size: 1 + enum: I2C_PB7_FMP + - name: I2C_PB8_FMP + description: Fast Mode Plus (FM+) driving capability activation bits. + bit_offset: 18 + bit_size: 1 + enum: I2C_PB8_FMP + - name: I2C_PB9_FMP + description: Fast Mode Plus (FM+) driving capability activation bits. + bit_offset: 19 + bit_size: 1 + enum: I2C_PB9_FMP + - name: I2C1_FMP + description: FM+ driving capability activation for I2C1 + bit_offset: 20 + bit_size: 1 + enum: I2C1_FMP + - name: I2C2_FMP + description: FM+ driving capability activation for I2C2 + bit_offset: 21 + bit_size: 1 + enum: I2C2_FMP + - name: I2C_PA9_FMP + description: Fast Mode Plus (FM+) driving capability activation bits + bit_offset: 22 + bit_size: 1 + enum: I2C_PA9_FMP + - name: I2C_PA10_FMP + description: Fast Mode Plus (FM+) driving capability activation bits + bit_offset: 23 + bit_size: 1 + enum: I2C_PA10_FMP + - name: SPI2_DMA_RMP + description: SPI2 DMA request remapping bit + bit_offset: 24 + bit_size: 1 + enum: SPI2_DMA_RMP + - name: USART2_DMA_RMP + description: USART2 DMA request remapping bit + bit_offset: 25 + bit_size: 1 + enum: USART2_DMA_RMP + - name: USART3_DMA_RMP + description: USART3 DMA request remapping bit + bit_offset: 26 + bit_size: 1 + enum: USART3_DMA_RMP + - name: I2C1_DMA_RMP + description: I2C1 DMA request remapping bit + bit_offset: 27 + bit_size: 1 + enum: I2C1_DMA_RMP + - name: TIM1_DMA_RMP + description: TIM1 DMA request remapping bit + bit_offset: 28 + bit_size: 1 + enum: TIM1_DMA_RMP + - name: TIM2_DMA_RMP + description: TIM2 DMA request remapping bit + bit_offset: 29 + bit_size: 1 + enum: TIM2_DMA_RMP + - name: TIM3_DMA_RMP + description: TIM3 DMA request remapping bit + bit_offset: 30 + bit_size: 1 + enum: TIM3_DMA_RMP +fieldset/CFGR2: + description: configuration register 2 + fields: + - name: LOCKUP_LOCK + description: Cortex-M0 LOCKUP bit enable bit + bit_offset: 0 + bit_size: 1 + enum: LOCKUP_LOCK + - name: SRAM_PARITY_LOCK + description: SRAM parity lock bit + bit_offset: 1 + bit_size: 1 + enum: SRAM_PARITY_LOCK + - name: PVD_LOCK + description: PVD lock enable bit + bit_offset: 2 + bit_size: 1 + enum: PVD_LOCK + - name: SRAM_PEF + description: SRAM parity flag + bit_offset: 8 + bit_size: 1 + enum_read: SRAM_PEFR + enum_write: SRAM_PEFW +fieldset/EXTICR: + description: external interrupt configuration register 1 + fields: + - name: EXTI + description: EXTI configuration bits + bit_offset: 0 + bit_size: 4 + array: + len: 4 + stride: 4 +enum/ADC_DMA_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: ADC DMA request mapped on DMA channel 1 + value: 0 + - name: Remapped + description: ADC DMA request mapped on DMA channel 2 + value: 1 +enum/I2C1_DMA_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively + value: 0 + - name: Remapped + description: I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively + value: 1 +enum/I2C1_FMP: + bit_size: 1 + variants: + - name: Standard + description: FM+ mode is controlled by I2C_Pxx_FMP bits only + value: 0 + - name: FMP + description: FM+ mode is enabled on all I2C1 pins selected through selection bits in GPIOx_AFR registers + value: 1 +enum/I2C2_FMP: + bit_size: 1 + variants: + - name: Standard + description: FM+ mode is controlled by I2C_Pxx_FMP bits only + value: 0 + - name: FMP + description: FM+ mode is enabled on all I2C2 pins selected through selection bits in GPIOx_AFR registers + value: 1 +enum/I2C_PA10_FMP: + bit_size: 1 + variants: + - name: Standard + description: PA10 pin operate in standard mode + value: 0 + - name: FMP + description: I2C FM+ mode enabled on PA10 and the Speed control is bypassed + value: 1 +enum/I2C_PA9_FMP: + bit_size: 1 + variants: + - name: Standard + description: PA9 pin operate in standard mode + value: 0 + - name: FMP + description: I2C FM+ mode enabled on PA9 and the Speed control is bypassed + value: 1 +enum/I2C_PB6_FMP: + bit_size: 1 + variants: + - name: Standard + description: PB6 pin operate in standard mode + value: 0 + - name: FMP + description: I2C FM+ mode enabled on PB6 and the Speed control is bypassed + value: 1 +enum/I2C_PB7_FMP: + bit_size: 1 + variants: + - name: Standard + description: PB7 pin operate in standard mode + value: 0 + - name: FMP + description: I2C FM+ mode enabled on PB7 and the Speed control is bypassed + value: 1 +enum/I2C_PB8_FMP: + bit_size: 1 + variants: + - name: Standard + description: PB8 pin operate in standard mode + value: 0 + - name: FMP + description: I2C FM+ mode enabled on PB8 and the Speed control is bypassed + value: 1 +enum/I2C_PB9_FMP: + bit_size: 1 + variants: + - name: Standard + description: PB9 pin operate in standard mode + value: 0 + - name: FMP + description: I2C FM+ mode enabled on PB9 and the Speed control is bypassed + value: 1 +enum/IR_MOD: + bit_size: 2 + variants: + - name: TIM16 + description: TIM16 selected + value: 0 + - name: USART1 + description: USART1 selected + value: 1 + - name: USART4 + description: USART4 selected + value: 2 +enum/LOCKUP_LOCK: + bit_size: 1 + variants: + - name: Disconnected + description: Cortex-M0 LOCKUP output disconnected from TIM1/15/16/17 Break input + value: 0 + - name: Connected + description: Cortex-M0 LOCKUP output connected to TIM1/15/16/17 Break input + value: 1 +enum/MEM_MODE: + bit_size: 2 + variants: + - name: MainFlash + description: Main Flash memory mapped at 0x0000_0000 + value: 0 + - name: SystemFlash + description: System Flash memory mapped at 0x0000_0000 + value: 1 + - name: MainFlash2 + description: Main Flash memory mapped at 0x0000_0000 + value: 2 + - name: SRAM + description: Embedded SRAM mapped at 0x0000_0000 + value: 3 +enum/PA11_PA12_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: Pin pair PA9/PA10 mapped on the pins + value: 0 + - name: Remapped + description: Pin pair PA11/PA12 mapped instead of PA9/PA10 + value: 1 +enum/PVD_LOCK: + bit_size: 1 + variants: + - name: Disconnected + description: PVD interrupt disconnected from TIM1/15/16/17 Break input + value: 0 + - name: Connected + description: PVD interrupt connected to TIM1/15/16/17 Break input + value: 1 +enum/SPI2_DMA_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively + value: 0 + - name: Remapped + description: SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively + value: 1 +enum/SRAM_PARITY_LOCK: + bit_size: 1 + variants: + - name: Disconnected + description: SRAM parity error disconnected from TIM1/15/16/17 Break input + value: 0 + - name: Connected + description: SRAM parity error connected to TIM1/15/16/17 Break input + value: 1 +enum/SRAM_PEFR: + bit_size: 1 + variants: + - name: NoParityError + description: No SRAM parity error detected + value: 0 + - name: ParityErrorDetected + description: SRAM parity error detected + value: 1 +enum/SRAM_PEFW: + bit_size: 1 + variants: + - name: Clear + description: Clear SRAM parity error flag + value: 1 +enum/TIM16_DMA_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 3 + value: 0 + - name: Remapped + description: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 4 + value: 1 +enum/TIM16_DMA_RMP2: + bit_size: 1 + variants: + - name: NotAlternateRemapped + description: TIM16 DMA request mapped according to TIM16_DMA_RMP bit + value: 0 + - name: AlternateRemapped + description: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 6 + value: 1 +enum/TIM17_DMA_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 1 + value: 0 + - name: Remapped + description: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 2 + value: 1 +enum/TIM17_DMA_RMP2: + bit_size: 1 + variants: + - name: NotAlternateRemapped + description: TIM17 DMA request mapped according to TIM16_DMA_RMP bit + value: 0 + - name: AlternateRemapped + description: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 7 + value: 1 +enum/TIM1_DMA_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: "TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively" + value: 0 + - name: Remapped + description: "TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6" + value: 1 +enum/TIM2_DMA_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively + value: 0 + - name: Remapped + description: TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 + value: 1 +enum/TIM3_DMA_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4 + value: 0 + - name: Remapped + description: TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6 + value: 1 +enum/USART1_RX_DMA_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: USART1_RX DMA request mapped on DMA channel 3 + value: 0 + - name: Remapped + description: USART1_RX DMA request mapped on DMA channel 5 + value: 1 +enum/USART1_TX_DMA_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: USART1_TX DMA request mapped on DMA channel 2 + value: 0 + - name: Remapped + description: USART1_TX DMA request mapped on DMA channel 4 + value: 1 +enum/USART2_DMA_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively + value: 0 + - name: Remapped + description: USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively + value: 1 +enum/USART3_DMA_RMP: + bit_size: 1 + variants: + - name: NotRemapped + description: USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively (or simply disabled on STM32F0x0) + value: 0 + - name: Remapped + description: USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively + value: 1 diff --git a/parse.py b/parse.py index 3815370..0991f64 100644 --- a/parse.py +++ b/parse.py @@ -311,6 +311,7 @@ perimap = [ ('.*:ADC:aditf5_v2_0', 'adc_v3/ADC'), ('.*:ADC_COMMON:aditf5_v2_0', 'adccommon_v3/ADC_COMMON'), ('.*:ADC_COMMON:aditf4_v3_0_WL', 'adccommon_v3/ADC_COMMON'), + ('STM32F0.*:SYS:.*', 'syscfg_f0/SYSCFG'), ('STM32F4.*:SYS:.*', 'syscfg_f4/SYSCFG'), ('STM32L4.*:SYS:.*', 'syscfg_l4/SYSCFG'), ('STM32L0.*:SYS:.*', 'syscfg_l0/SYSCFG'),