add to chips.rs

data/registers/lptim_v2h5.yaml

@@ -12,8 +12,8 @@ block/IC:
     description: LPTIM interrupt enable register.
     byte_offset: 8
     fieldset: DIER_IC
-block/LPTIM_Adv:
+block/LPTIM_ADV:
-  extends: LPTIM_Basic
+  extends: LPTIM_BASIC
   description: Low power timer with Output Compare
   items:
   - name: InputCapture
@@ -21,7 +21,7 @@ block/LPTIM_Adv:
     block: IC
   - name: OutputCompare
     byte_offset: 0
-    block: OC_Adv
+    block: OC_ADV
   - name: CCR
     description: LPTIM compare register 1.
     array:
@@ -29,12 +29,20 @@ block/LPTIM_Adv:
       stride: 32
     byte_offset: 20
     fieldset: CCR
-block/LPTIM_Basic:
+  - name: CCMR_IC
+    description: LPTIM capture/compare mode register 1.
+    byte_offset: 44
+    fieldset: CCMR_IC
+  - name: CCMR_OC
+    description: LPTIM capture/compare mode register 1.
+    byte_offset: 44
+    fieldset: CCMR_OC
+block/LPTIM_BASIC:
   description: Low power timer with Output Compare
   items:
   - name: OutputCompare
     byte_offset: 0
-    block: OC_Basic
+    block: OC_BASIC
   - name: CFGR
     description: LPTIM configuration register.
     byte_offset: 12
@@ -66,42 +74,34 @@ block/LPTIM_Basic:
     description: LPTIM repetition register.
     byte_offset: 40
     fieldset: RCR
-block/OC_Adv:
+block/OC_ADV:
   items:
   - name: ISR
     description: LPTIM interrupt and status register.
     byte_offset: 0
-    fieldset: ISR_OC_Adv
+    fieldset: ISR_OC_ADV
   - name: ICR
     description: LPTIM interrupt clear register.
     byte_offset: 4
-    fieldset: ICR_OC_Adv
+    fieldset: ICR_OC_ADV
   - name: DIER
     description: LPTIM interrupt enable register.
     byte_offset: 8
-    fieldset: DIER_OC_Adv
+    fieldset: DIER_OC_ADV
-  - name: CCMR_IC
+block/OC_BASIC:
-    description: LPTIM capture/compare mode register 1.
-    byte_offset: 44
-    fieldset: CCMR_IC
-  - name: CCMR_OC
-    description: LPTIM capture/compare mode register 1.
-    byte_offset: 44
-    fieldset: CCMR_OC
-block/OC_Basic:
   items:
   - name: ISR
     description: LPTIM interrupt and status register.
     byte_offset: 0
-    fieldset: ISR_OC_Basic
+    fieldset: ISR_OC_BASIC
   - name: ICR
     description: LPTIM interrupt clear register.
     byte_offset: 4
-    fieldset: ICR_OC_Basic
+    fieldset: ICR_OC_BASIC
   - name: DIER
     description: LPTIM interrupt enable register.
     byte_offset: 8
-    fieldset: DIER_OC_Basic
+    fieldset: DIER_OC_BASIC
 fieldset/ARR:
   description: LPTIM autoreload register.
   fields:
@@ -338,8 +338,8 @@ fieldset/DIER_IC:
     description: 'Update event DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.'
     bit_offset: 23
     bit_size: 1
-fieldset/DIER_OC_Adv:
+fieldset/DIER_OC_ADV:
-  extends: DIER_OC_Basic
+  extends: DIER_OC_BASIC
   description: LPTIM interrupt enable register.
   fields:
   - name: CCIE
@@ -356,7 +356,7 @@ fieldset/DIER_OC_Adv:
     array:
       len: 2
       stride: 16
-fieldset/DIER_OC_Basic:
+fieldset/DIER_OC_BASIC:
   description: LPTIM interrupt enable register.
   fields:
   - name: CCIE
@@ -450,8 +450,8 @@ fieldset/ICR_IC:
     description: Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register.
     bit_offset: 24
     bit_size: 1
-fieldset/ICR_OC_Adv:
+fieldset/ICR_OC_ADV:
-  extends: ICR_OC_Basic
+  extends: ICR_OC_BASIC
   description: LPTIM interrupt clear register.
   fields:
   - name: CCCF
@@ -468,7 +468,7 @@ fieldset/ICR_OC_Adv:
     array:
       len: 2
       stride: 16
-fieldset/ICR_OC_Basic:
+fieldset/ICR_OC_BASIC:
   description: LPTIM interrupt clear register.
   fields:
   - name: CCCF
@@ -566,8 +566,8 @@ fieldset/ISR_IC:
     description: Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register.
     bit_offset: 24
     bit_size: 1
-fieldset/ISR_OC_Adv:
+fieldset/ISR_OC_ADV:
-  extends: ISR_OC_Basic
+  extends: ISR_OC_BASIC
   description: LPTIM interrupt and status register.
   fields:
   - name: CCIF
@@ -584,7 +584,7 @@ fieldset/ISR_OC_Adv:
     array:
       len: 2
       stride: 16
-fieldset/ISR_OC_Basic:
+fieldset/ISR_OC_BASIC:
   description: LPTIM interrupt and status register.
   fields:
   - name: CCIF

stm32-data-gen/src/chips.rs

@@ -503,7 +503,11 @@ impl PeriMatcher {
             ("STM32(C|G0|H7|WB|WL).*:TIM12:.*", ("timer", "v1", "TIM_2CH")),
             ("STM32(C|G0|H7|WB|WL).*:TIM15:.*", ("timer", "v1", "TIM_2CH_CMP")),
             ("STM32(C|G0|H7|WB|WL).*:TIM(16|17):.*", ("timer", "v1", "TIM_1CH_CMP")),
-            ("STM32[CGHUW].*:LPTIM[1-6]:.*", ("lptim", "v1", "LPTIM")),
+            // LPTIM for STM32Gx/Hx/Ux/Wx (and Cx) serials
+            ("STM32H5.*:LPTIM[12356]:.*", ("lptim", "v2h5", "LPTIM_ADV")),
+            ("STM32H5.*:LPTIM4:.*", ("lptim", "v2h5", "LPTIM_BASIC")),
+            ("STM32(C|G|H7|U|W).*:LPTIM[1-6]:.*", ("lptim", "v1", "LPTIM")),
+            // HRTIM for STM32Gx/Hx/Ux/Wx (and Cx) serials
             ("STM32[CGHUW].*:HRTIM1?:.*", ("hrtim", "v1", "HRTIM")),
             //
             //// TIM mapping ends here ////