Merge pull request #71 from timokroeger/fix-f4-l4-rcc

Remove invalid bits from F4, L4 RCC

data/registers/rcc_f4.yaml

@@ -740,33 +740,6 @@ enum/PLLP:
   - description: PLLP=8
     name: Div8
     value: 3
-enum/PLLRDYFR:
-  bit_size: 1
-  variants:
-  - description: No clock ready interrupt
-    name: NotInterrupted
-    value: 0
-  - description: Clock ready interrupt
-    name: Interrupted
-    value: 1
-enum/PLLRDYIE:
-  bit_size: 1
-  variants:
-  - description: Interrupt disabled
-    name: Disabled
-    value: 0
-  - description: Interrupt enabled
-    name: Enabled
-    value: 1
-enum/PLLRDYR:
-  bit_size: 1
-  variants:
-  - description: Clock not ready
-    name: NotReady
-    value: 0
-  - description: Clock ready
-    name: Ready
-    value: 1
 enum/PLLSAIDIVQ:
   bit_size: 5
   variants:
@@ -1163,10 +1136,6 @@ fieldset/AHB1ENR:
     bit_size: 1
     description: USB OTG HSULPI clock enable
     name: OTGHSULPIEN
-  - bit_offset: 31
-    bit_size: 1
-    description: RNG clock enable
-    name: RNGEN
   - bit_offset: 9
     bit_size: 1
     description: IO port J clock enable
@@ -1353,10 +1322,6 @@ fieldset/AHB1RSTR:
     bit_size: 1
     description: USB OTG HS module reset
     name: OTGHSRST
-  - bit_offset: 31
-    bit_size: 1
-    description: RNGRST
-    name: RNGRST
   - bit_offset: 9
     bit_size: 1
     description: IO port J reset

data/registers/rcc_l4.yaml

@@ -616,10 +616,6 @@ fieldset/APB1ENR1:
     bit_size: 1
     description: USART3 clock enable
     name: USART3EN
-  - bit_offset: 18
-    bit_size: 1
-    description: USART1 clock enable
-    name: USART1EN
   - bit_offset: 19
     bit_size: 1
     description: UART4 clock enable

parse.py

@@ -319,6 +319,7 @@ perimap = [
     ('STM32WL.*:SYS:.*', 'syscfg_wl5x/SYSCFG'),
     ('STM32L0.*:RCC:.*', 'rcc_l0/RCC'),
     ('STM32L4.*:RCC:.*', 'rcc_l4/RCC'),
+    ('STM32F410.*:RCC:.*', 'rcc_f410/RCC'),
     ('STM32F4.*:RCC:.*', 'rcc_f4/RCC'),
     ('STM32WL.*:RCC:.*', 'rcc_wl5x/RCC'),
     ('STM32F0.0.*:RCC:.*', 'rcc_f0x0/RCC'),