From 074aad8a66b7c829d4c1588692751954aabe78c5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timo=20Kr=C3=B6ger?= Date: Fri, 30 Jul 2021 17:35:34 +0200 Subject: [PATCH 1/2] Remove invalid bits from F4, L4 RCC --- data/registers/rcc_f4.yaml | 8 -------- data/registers/rcc_l4.yaml | 4 ---- 2 files changed, 12 deletions(-) diff --git a/data/registers/rcc_f4.yaml b/data/registers/rcc_f4.yaml index 61a7a55..4929120 100644 --- a/data/registers/rcc_f4.yaml +++ b/data/registers/rcc_f4.yaml @@ -1163,10 +1163,6 @@ fieldset/AHB1ENR: bit_size: 1 description: USB OTG HSULPI clock enable name: OTGHSULPIEN - - bit_offset: 31 - bit_size: 1 - description: RNG clock enable - name: RNGEN - bit_offset: 9 bit_size: 1 description: IO port J clock enable @@ -1353,10 +1349,6 @@ fieldset/AHB1RSTR: bit_size: 1 description: USB OTG HS module reset name: OTGHSRST - - bit_offset: 31 - bit_size: 1 - description: RNGRST - name: RNGRST - bit_offset: 9 bit_size: 1 description: IO port J reset diff --git a/data/registers/rcc_l4.yaml b/data/registers/rcc_l4.yaml index 382b04b..9e498ea 100644 --- a/data/registers/rcc_l4.yaml +++ b/data/registers/rcc_l4.yaml @@ -616,10 +616,6 @@ fieldset/APB1ENR1: bit_size: 1 description: USART3 clock enable name: USART3EN - - bit_offset: 18 - bit_size: 1 - description: USART1 clock enable - name: USART1EN - bit_offset: 19 bit_size: 1 description: UART4 clock enable From c02e3dc9abf644666c425627e5b5bf7cbc4d896f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timo=20Kr=C3=B6ger?= Date: Sat, 31 Jul 2021 17:40:30 +0200 Subject: [PATCH 2/2] Split f410 and f4 RCC yamls f410 has the RNGEN at a different position --- data/registers/rcc_f4.yaml | 27 - data/registers/rcc_f410.yaml | 1138 ++++++++++++++++++++++++++++++++++ parse.py | 1 + 3 files changed, 1139 insertions(+), 27 deletions(-) create mode 100644 data/registers/rcc_f410.yaml diff --git a/data/registers/rcc_f4.yaml b/data/registers/rcc_f4.yaml index 4929120..e6e749a 100644 --- a/data/registers/rcc_f4.yaml +++ b/data/registers/rcc_f4.yaml @@ -740,33 +740,6 @@ enum/PLLP: - description: PLLP=8 name: Div8 value: 3 -enum/PLLRDYFR: - bit_size: 1 - variants: - - description: No clock ready interrupt - name: NotInterrupted - value: 0 - - description: Clock ready interrupt - name: Interrupted - value: 1 -enum/PLLRDYIE: - bit_size: 1 - variants: - - description: Interrupt disabled - name: Disabled - value: 0 - - description: Interrupt enabled - name: Enabled - value: 1 -enum/PLLRDYR: - bit_size: 1 - variants: - - description: Clock not ready - name: NotReady - value: 0 - - description: Clock ready - name: Ready - value: 1 enum/PLLSAIDIVQ: bit_size: 5 variants: diff --git a/data/registers/rcc_f410.yaml b/data/registers/rcc_f410.yaml new file mode 100644 index 0000000..ab16d39 --- /dev/null +++ b/data/registers/rcc_f410.yaml @@ -0,0 +1,1138 @@ +block/RCC: + description: Reset and clock control + items: + - name: CR + description: clock control register + byte_offset: 0 + fieldset: CR + - name: PLLCFGR + description: PLL configuration register + byte_offset: 4 + fieldset: PLLCFGR + - name: CFGR + description: clock configuration register + byte_offset: 8 + fieldset: CFGR + - name: CIR + description: clock interrupt register + byte_offset: 12 + fieldset: CIR + - name: AHB1RSTR + description: AHB1 peripheral reset register + byte_offset: 16 + fieldset: AHB1RSTR + - name: APB1RSTR + description: APB1 peripheral reset register + byte_offset: 32 + fieldset: APB1RSTR + - name: APB2RSTR + description: APB2 peripheral reset register + byte_offset: 36 + fieldset: APB2RSTR + - name: AHB1ENR + description: AHB1 peripheral clock register + byte_offset: 48 + fieldset: AHB1ENR + - name: APB1ENR + description: APB1 peripheral clock enable register + byte_offset: 64 + fieldset: APB1ENR + - name: APB2ENR + description: APB2 peripheral clock enable register + byte_offset: 68 + fieldset: APB2ENR + - name: AHB1LPENR + description: AHB1 peripheral clock enable in low power mode register + byte_offset: 80 + fieldset: AHB1LPENR + - name: APB1LPENR + description: APB1 peripheral clock enable in low power mode register + byte_offset: 96 + fieldset: APB1LPENR + - name: APB2LPENR + description: APB2 peripheral clock enabled in low power mode register + byte_offset: 100 + fieldset: APB2LPENR + - name: BDCR + description: Backup domain control register + byte_offset: 112 + fieldset: BDCR + - name: CSR + description: clock control & status register + byte_offset: 116 + fieldset: CSR + - name: SSCGR + description: spread spectrum clock generation register + byte_offset: 128 + fieldset: SSCGR + - name: DCKCFGR + description: DCKCFGR register + byte_offset: 140 + fieldset: DCKCFGR + - name: DCKCFGR2 + description: DCKCFGR2 register + byte_offset: 148 + fieldset: DCKCFGR2 +fieldset/AHB1ENR: + description: AHB1 peripheral clock register + fields: + - name: GPIOAEN + description: IO port A clock enable + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: IO port B clock enable + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: IO port C clock enable + bit_offset: 2 + bit_size: 1 + - name: GPIOHEN + description: IO port H clock enable + bit_offset: 7 + bit_size: 1 + - name: CRCEN + description: CRC clock enable + bit_offset: 12 + bit_size: 1 + - name: DMA1EN + description: DMA1 clock enable + bit_offset: 21 + bit_size: 1 + - name: DMA2EN + description: DMA2 clock enable + bit_offset: 22 + bit_size: 1 + - name: RNGEN + description: RNG clock enable + bit_offset: 31 + bit_size: 1 +fieldset/AHB1LPENR: + description: AHB1 peripheral clock enable in low power mode register + fields: + - name: GPIOALPEN + description: IO port A clock enable during sleep mode + bit_offset: 0 + bit_size: 1 + - name: GPIOBLPEN + description: IO port B clock enable during Sleep mode + bit_offset: 1 + bit_size: 1 + - name: GPIOCLPEN + description: IO port C clock enable during Sleep mode + bit_offset: 2 + bit_size: 1 + - name: GPIOHLPEN + description: IO port H clock enable during Sleep mode + bit_offset: 7 + bit_size: 1 + - name: CRCLPEN + description: CRC clock enable during Sleep mode + bit_offset: 12 + bit_size: 1 + - name: FLITFLPEN + description: Flash interface clock enable during Sleep mode + bit_offset: 15 + bit_size: 1 + - name: SRAM1LPEN + description: SRAM 1interface clock enable during Sleep mode + bit_offset: 16 + bit_size: 1 + - name: DMA1LPEN + description: DMA1 clock enable during Sleep mode + bit_offset: 21 + bit_size: 1 + - name: DMA2LPEN + description: DMA2 clock enable during Sleep mode + bit_offset: 22 + bit_size: 1 + - name: RNGLPEN + description: RNG clock enable during sleep mode + bit_offset: 31 + bit_size: 1 +fieldset/AHB1RSTR: + description: AHB1 peripheral reset register + fields: + - name: GPIOARST + description: IO port A reset + bit_offset: 0 + bit_size: 1 + - name: GPIOBRST + description: IO port B reset + bit_offset: 1 + bit_size: 1 + - name: GPIOCRST + description: IO port C reset + bit_offset: 2 + bit_size: 1 + - name: GPIOHRST + description: IO port H reset + bit_offset: 7 + bit_size: 1 + - name: CRCRST + description: CRC reset + bit_offset: 12 + bit_size: 1 + - name: DMA1RST + description: DMA2 reset + bit_offset: 21 + bit_size: 1 + - name: DMA2RST + description: DMA2 reset + bit_offset: 22 + bit_size: 1 + - name: RNGRST + description: RNGRST + bit_offset: 31 + bit_size: 1 +fieldset/APB1ENR: + description: APB1 peripheral clock enable register + fields: + - name: TIM5EN + description: TIM5 clock enable + bit_offset: 3 + bit_size: 1 + - name: TIM6EN + description: TIM6 clock enable + bit_offset: 4 + bit_size: 1 + - name: LPTIM1EN + description: LPTIM1 clock enable + bit_offset: 9 + bit_size: 1 + - name: RTCAPBEN + description: RTC APB clock enable + bit_offset: 10 + bit_size: 1 + - name: WWDGEN + description: Window watchdog clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI2 clock enable + bit_offset: 14 + bit_size: 1 + - name: USART2EN + description: USART 2 clock enable + bit_offset: 17 + bit_size: 1 + - name: I2C1EN + description: I2C1 clock enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C2 clock enable + bit_offset: 22 + bit_size: 1 + - name: FMPI2C1EN + description: FMPI2C1 clock enable + bit_offset: 24 + bit_size: 1 + - name: PWREN + description: Power interface clock enable + bit_offset: 28 + bit_size: 1 + - name: DACEN + description: DAC interface clock enable + bit_offset: 29 + bit_size: 1 +fieldset/APB1LPENR: + description: APB1 peripheral clock enable in low power mode register + fields: + - name: TIM5LPEN + description: TIM5 clock enable during Sleep mode + bit_offset: 3 + bit_size: 1 + - name: TIM6LPEN + description: TIM6 clock enable during Sleep mode + bit_offset: 4 + bit_size: 1 + - name: LPTIM1LPEN + description: LPTIM1 clock enable during sleep mode + bit_offset: 9 + bit_size: 1 + - name: RTCAPBLPEN + description: RTC APB clock enable during sleep mode + bit_offset: 10 + bit_size: 1 + - name: WWDGLPEN + description: Window watchdog clock enable during Sleep mode + bit_offset: 11 + bit_size: 1 + - name: SPI2LPEN + description: SPI2 clock enable during Sleep mode + bit_offset: 14 + bit_size: 1 + - name: USART2LPEN + description: USART2 clock enable during Sleep mode + bit_offset: 17 + bit_size: 1 + - name: I2C1LPEN + description: I2C1 clock enable during Sleep mode + bit_offset: 21 + bit_size: 1 + - name: I2C2LPEN + description: I2C2 clock enable during Sleep mode + bit_offset: 22 + bit_size: 1 + - name: FMPI2C1LPEN + description: FMPI2C1 clock enable during Sleep + bit_offset: 24 + bit_size: 1 + - name: PWRLPEN + description: Power interface clock enable during Sleep mode + bit_offset: 28 + bit_size: 1 + - name: DACLPEN + description: DAC interface clock enable during sleep mode + bit_offset: 29 + bit_size: 1 +fieldset/APB1RSTR: + description: APB1 peripheral reset register + fields: + - name: TIM5RST + description: TIM5 reset + bit_offset: 3 + bit_size: 1 + - name: TIM6RST + description: TIM6 reset + bit_offset: 4 + bit_size: 1 + - name: LPTIM1RST + description: LPTIM1 reset + bit_offset: 9 + bit_size: 1 + - name: WWDGRST + description: Window watchdog reset + bit_offset: 11 + bit_size: 1 + - name: SPI2RST + description: SPI 2 reset + bit_offset: 14 + bit_size: 1 + - name: USART2RST + description: USART 2 reset + bit_offset: 17 + bit_size: 1 + - name: I2C1RST + description: I2C 1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C 2 reset + bit_offset: 22 + bit_size: 1 + - name: FMPI2C1RST + description: FMPI2C1 reset + bit_offset: 24 + bit_size: 1 + - name: PWRRST + description: Power interface reset + bit_offset: 28 + bit_size: 1 + - name: DACRST + description: DAC reset + bit_offset: 29 + bit_size: 1 +fieldset/APB2ENR: + description: APB2 peripheral clock enable register + fields: + - name: TIM1EN + description: TIM1 clock enable + bit_offset: 0 + bit_size: 1 + - name: USART1EN + description: USART1 clock enable + bit_offset: 4 + bit_size: 1 + - name: USART6EN + description: USART6 clock enable + bit_offset: 5 + bit_size: 1 + - name: ADC1EN + description: ADC1 clock enable + bit_offset: 8 + bit_size: 1 + - name: SPI1EN + description: SPI1 clock enable + bit_offset: 12 + bit_size: 1 + - name: SYSCFGEN + description: System configuration controller clock enable + bit_offset: 14 + bit_size: 1 + - name: EXTITEN + description: EXTI ans external IT clock enable + bit_offset: 15 + bit_size: 1 + - name: TIM9EN + description: TIM9 clock enable + bit_offset: 16 + bit_size: 1 + - name: TIM11EN + description: TIM11 clock enable + bit_offset: 18 + bit_size: 1 + - name: SPI5EN + description: SPI5 clock enable + bit_offset: 20 + bit_size: 1 +fieldset/APB2LPENR: + description: APB2 peripheral clock enabled in low power mode register + fields: + - name: TIM1LPEN + description: TIM1 clock enable during Sleep mode + bit_offset: 0 + bit_size: 1 + - name: USART1LPEN + description: USART1 clock enable during Sleep mode + bit_offset: 4 + bit_size: 1 + - name: USART6LPEN + description: USART6 clock enable during Sleep mode + bit_offset: 5 + bit_size: 1 + - name: ADC1LPEN + description: ADC1 clock enable during Sleep mode + bit_offset: 8 + bit_size: 1 + - name: SDIOLPEN + description: SDIO clock enable during Sleep mode + bit_offset: 11 + bit_size: 1 + - name: SPI1LPEN + description: SPI 1 clock enable during Sleep mode + bit_offset: 12 + bit_size: 1 + - name: SYSCFGLPEN + description: System configuration controller clock enable during Sleep mode + bit_offset: 14 + bit_size: 1 + - name: EXTITLPEN + description: EXTI and External IT clock enable during sleep mode + bit_offset: 15 + bit_size: 1 + - name: TIM9LPEN + description: TIM9 clock enable during sleep mode + bit_offset: 16 + bit_size: 1 + - name: TIM11LPEN + description: TIM11 clock enable during Sleep mode + bit_offset: 18 + bit_size: 1 + - name: SPI5LPEN + description: SPI5 clock enable during Sleep mode + bit_offset: 20 + bit_size: 1 +fieldset/APB2RSTR: + description: APB2 peripheral reset register + fields: + - name: TIM1RST + description: TIM1 reset + bit_offset: 0 + bit_size: 1 + - name: USART1RST + description: USART1 reset + bit_offset: 4 + bit_size: 1 + - name: USART6RST + description: USART6 reset + bit_offset: 5 + bit_size: 1 + - name: ADCRST + description: ADC interface reset (common to all ADCs) + bit_offset: 8 + bit_size: 1 + - name: SPI1RST + description: SPI 1 reset + bit_offset: 12 + bit_size: 1 + - name: SYSCFGRST + description: System configuration controller reset + bit_offset: 14 + bit_size: 1 + - name: TIM9RST + description: TIM9 reset + bit_offset: 16 + bit_size: 1 + - name: TIM11RST + description: TIM11 reset + bit_offset: 18 + bit_size: 1 + - name: SPI5RST + description: SPI5 reset + bit_offset: 20 + bit_size: 1 +fieldset/BDCR: + description: Backup domain control register + fields: + - name: LSEON + description: External low-speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: External low-speed oscillator ready + bit_offset: 1 + bit_size: 1 + enum_read: LSERDYR + - name: LSEBYP + description: External low-speed oscillator bypass + bit_offset: 2 + bit_size: 1 + enum: LSEBYP + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: Backup domain software reset + bit_offset: 16 + bit_size: 1 +fieldset/CFGR: + description: clock configuration register + fields: + - name: SW + description: System clock switch + bit_offset: 0 + bit_size: 2 + enum: SW + - name: SWS + description: System clock switch status + bit_offset: 2 + bit_size: 2 + enum_read: SWSR + - name: HPRE + description: AHB prescaler + bit_offset: 4 + bit_size: 4 + enum: HPRE + - name: MCO1EN + description: MCO output enable + bit_offset: 8 + bit_size: 1 + - name: MCO2EN + description: MCO output enable + bit_offset: 9 + bit_size: 1 + - name: PPRE1 + description: APB Low speed prescaler (APB1) + bit_offset: 10 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: APB high-speed prescaler (APB2) + bit_offset: 13 + bit_size: 3 + enum: PPRE + - name: RTCPRE + description: HSE division factor for RTC clock + bit_offset: 16 + bit_size: 5 + - name: MCO1 + description: Microcontroller clock output 1 + bit_offset: 21 + bit_size: 2 + enum: MCO1 + - name: MCO1PRE + description: MCO1 prescaler + bit_offset: 24 + bit_size: 3 + enum: MCOPRE + - name: MCO2PRE + description: MCO2 prescaler + bit_offset: 27 + bit_size: 3 + enum: MCOPRE + - name: MCO2 + description: Microcontroller clock output 2 + bit_offset: 30 + bit_size: 2 + enum: MCO2 +fieldset/CIR: + description: clock interrupt register + fields: + - name: LSIRDYF + description: LSI ready interrupt flag + bit_offset: 0 + bit_size: 1 + enum_read: PLLRDYFR + - name: LSERDYF + description: LSE ready interrupt flag + bit_offset: 1 + bit_size: 1 + enum_read: PLLRDYFR + - name: HSIRDYF + description: HSI ready interrupt flag + bit_offset: 2 + bit_size: 1 + enum_read: PLLRDYFR + - name: HSERDYF + description: HSE ready interrupt flag + bit_offset: 3 + bit_size: 1 + enum_read: PLLRDYFR + - name: PLLRDYF + description: Main PLL (PLL) ready interrupt flag + bit_offset: 4 + bit_size: 1 + enum_read: PLLRDYFR + - name: CSSF + description: Clock security system interrupt flag + bit_offset: 7 + bit_size: 1 + enum_read: CSSFR + - name: LSIRDYIE + description: LSI ready interrupt enable + bit_offset: 8 + bit_size: 1 + enum: PLLRDYIE + - name: LSERDYIE + description: LSE ready interrupt enable + bit_offset: 9 + bit_size: 1 + enum: PLLRDYIE + - name: HSIRDYIE + description: HSI ready interrupt enable + bit_offset: 10 + bit_size: 1 + enum: PLLRDYIE + - name: HSERDYIE + description: HSE ready interrupt enable + bit_offset: 11 + bit_size: 1 + enum: PLLRDYIE + - name: PLLRDYIE + description: Main PLL (PLL) ready interrupt enable + bit_offset: 12 + bit_size: 1 + enum: PLLRDYIE + - name: LSIRDYC + description: LSI ready interrupt clear + bit_offset: 16 + bit_size: 1 + enum_write: PLLISRDYCW + - name: LSERDYC + description: LSE ready interrupt clear + bit_offset: 17 + bit_size: 1 + enum_write: PLLISRDYCW + - name: HSIRDYC + description: HSI ready interrupt clear + bit_offset: 18 + bit_size: 1 + enum_write: PLLISRDYCW + - name: HSERDYC + description: HSE ready interrupt clear + bit_offset: 19 + bit_size: 1 + enum_write: PLLISRDYCW + - name: PLLRDYC + description: Main PLL(PLL) ready interrupt clear + bit_offset: 20 + bit_size: 1 + enum_write: PLLISRDYCW + - name: PLLI2SRDYC + description: PLLI2S ready interrupt clear + bit_offset: 21 + bit_size: 1 + enum_write: PLLISRDYCW + - name: CSSC + description: Clock security system interrupt clear + bit_offset: 23 + bit_size: 1 + enum_write: CSSCW +fieldset/CR: + description: clock control register + fields: + - name: HSION + description: Internal high-speed clock enable + bit_offset: 0 + bit_size: 1 + - name: HSIRDY + description: Internal high-speed clock ready flag + bit_offset: 1 + bit_size: 1 + enum_read: PLLRDYR + - name: HSITRIM + description: Internal high-speed clock trimming + bit_offset: 3 + bit_size: 5 + - name: HSICAL + description: Internal high-speed clock calibration + bit_offset: 8 + bit_size: 8 + - name: HSEON + description: HSE clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: HSE clock ready flag + bit_offset: 17 + bit_size: 1 + enum_read: PLLRDYR + - name: HSEBYP + description: HSE clock bypass + bit_offset: 18 + bit_size: 1 + enum: HSEBYP + - name: CSSON + description: Clock security system enable + bit_offset: 19 + bit_size: 1 + - name: PLLON + description: Main PLL (PLL) enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: Main PLL (PLL) clock ready flag + bit_offset: 25 + bit_size: 1 + enum_read: PLLRDYR +fieldset/CSR: + description: clock control & status register + fields: + - name: LSION + description: Internal low-speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: Internal low-speed oscillator ready + bit_offset: 1 + bit_size: 1 + enum_read: LSIRDYR + - name: RMVF + description: Remove reset flag + bit_offset: 24 + bit_size: 1 + enum_write: RMVFW + - name: BORRSTF + description: BOR reset flag + bit_offset: 25 + bit_size: 1 + enum_read: LPWRRSTFR + - name: PADRSTF + description: PIN reset flag + bit_offset: 26 + bit_size: 1 + enum_read: LPWRRSTFR + - name: PORRSTF + description: POR/PDR reset flag + bit_offset: 27 + bit_size: 1 + enum_read: LPWRRSTFR + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + enum_read: LPWRRSTFR + - name: WDGRSTF + description: Independent watchdog reset flag + bit_offset: 29 + bit_size: 1 + enum_read: LPWRRSTFR + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + enum_read: LPWRRSTFR + - name: LPWRRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 + enum_read: LPWRRSTFR +fieldset/DCKCFGR: + description: DCKCFGR register + fields: + - name: TIMPRE + description: TIMPRE + bit_offset: 24 + bit_size: 1 + enum: TIMPRE + - name: I2SSRC + description: I2SSRC + bit_offset: 25 + bit_size: 2 + enum: ISSRC +fieldset/DCKCFGR2: + description: DCKCFGR2 register + fields: + - name: FMPI2C1SEL + description: FMPI2C1 kernel clock source selection + bit_offset: 22 + bit_size: 2 + enum: FMPICSEL + - name: LPTIM1SEL + description: LPTIM1SEL + bit_offset: 30 + bit_size: 2 + enum: LPTIMSEL +fieldset/PLLCFGR: + description: PLL configuration register + fields: + - name: PLLM + description: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock + bit_offset: 0 + bit_size: 6 + - name: PLLN + description: Main PLL (PLL) multiplication factor for VCO + bit_offset: 6 + bit_size: 9 + - name: PLLP + description: Main PLL (PLL) division factor for main system clock + bit_offset: 16 + bit_size: 2 + enum: PLLP + - name: PLLSRC + description: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source + bit_offset: 22 + bit_size: 1 + enum: PLLSRC + - name: PLLQ + description: "Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks" + bit_offset: 24 + bit_size: 4 + - name: PLLR + description: PLL division factor for I2S and System clocks + bit_offset: 28 + bit_size: 3 +fieldset/SSCGR: + description: spread spectrum clock generation register + fields: + - name: MODPER + description: Modulation period + bit_offset: 0 + bit_size: 13 + - name: INCSTEP + description: Incrementation step + bit_offset: 13 + bit_size: 15 + - name: SPREADSEL + description: Spread Select + bit_offset: 30 + bit_size: 1 + enum: SPREADSEL + - name: SSCGEN + description: Spread spectrum modulation enable + bit_offset: 31 + bit_size: 1 +enum/CSSCW: + bit_size: 1 + variants: + - name: Clear + description: Clear CSSF flag + value: 1 +enum/CSSFR: + bit_size: 1 + variants: + - name: NotInterrupted + description: No clock security interrupt caused by HSE clock failure + value: 0 + - name: Interrupted + description: Clock security interrupt caused by HSE clock failure + value: 1 +enum/FMPICSEL: + bit_size: 2 + variants: + - name: APB + description: APB clock selected as I2C clock + value: 0 + - name: SYSCLK + description: System clock selected as I2C clock + value: 1 + - name: HSI + description: HSI clock selected as I2C clock + value: 2 +enum/HPRE: + bit_size: 4 + variants: + - name: Div1 + description: SYSCLK not divided + value: 0 + - name: Div2 + description: SYSCLK divided by 2 + value: 8 + - name: Div4 + description: SYSCLK divided by 4 + value: 9 + - name: Div8 + description: SYSCLK divided by 8 + value: 10 + - name: Div16 + description: SYSCLK divided by 16 + value: 11 + - name: Div64 + description: SYSCLK divided by 64 + value: 12 + - name: Div128 + description: SYSCLK divided by 128 + value: 13 + - name: Div256 + description: SYSCLK divided by 256 + value: 14 + - name: Div512 + description: SYSCLK divided by 512 + value: 15 +enum/HSEBYP: + bit_size: 1 + variants: + - name: NotBypassed + description: HSE crystal oscillator not bypassed + value: 0 + - name: Bypassed + description: HSE crystal oscillator bypassed with external clock + value: 1 +enum/ISSRC: + bit_size: 2 + variants: + - name: PLLCLKR + description: I2Sx clock frequency = f(PLLCLK_R) + value: 0 + - name: I2S_CKIN + description: I2Sx clock frequency = I2S_CKIN Alternate function input frequency + value: 1 + - name: HSI_HSE + description: "I2Sx clock frequency = HSI/HSE depends on PLLSRC bit (PLLCFGR[22])" + value: 3 +enum/LPTIMSEL: + bit_size: 2 + variants: + - name: APB1 + description: APB1 clock (PCLK1) selected as LPTILM1 clock + value: 0 + - name: LSI + description: LSI clock is selected as LPTILM1 clock + value: 1 + - name: HSI + description: HSI clock is selected as LPTILM1 clock + value: 2 + - name: LSE + description: LSE clock is selected as LPTILM1 clock + value: 3 +enum/LPWRRSTFR: + bit_size: 1 + variants: + - name: NoReset + description: No reset has occured + value: 0 + - name: Reset + description: A reset has occured + value: 1 +enum/LSEBYP: + bit_size: 1 + variants: + - name: NotBypassed + description: LSE crystal oscillator not bypassed + value: 0 + - name: Bypassed + description: LSE crystal oscillator bypassed with external clock + value: 1 +enum/LSERDYR: + bit_size: 1 + variants: + - name: NotReady + description: LSE oscillator not ready + value: 0 + - name: Ready + description: LSE oscillator ready + value: 1 +enum/LSIRDYR: + bit_size: 1 + variants: + - name: NotReady + description: LSI oscillator not ready + value: 0 + - name: Ready + description: LSI oscillator ready + value: 1 +enum/MCO1: + bit_size: 2 + variants: + - name: HSI + description: HSI clock selected + value: 0 + - name: LSE + description: LSE oscillator selected + value: 1 + - name: HSE + description: HSE oscillator clock selected + value: 2 + - name: PLL + description: PLL clock selected + value: 3 +enum/MCO2: + bit_size: 2 + variants: + - name: SYSCLK + description: System clock (SYSCLK) selected + value: 0 + - name: PLLI2S + description: PLLI2S clock selected + value: 1 + - name: HSE + description: HSE oscillator clock selected + value: 2 + - name: PLL + description: PLL clock selected + value: 3 +enum/MCOPRE: + bit_size: 3 + variants: + - name: Div1 + description: No division + value: 0 + - name: Div2 + description: Division by 2 + value: 4 + - name: Div3 + description: Division by 3 + value: 5 + - name: Div4 + description: Division by 4 + value: 6 + - name: Div5 + description: Division by 5 + value: 7 +enum/PLLISRDYCW: + bit_size: 1 + variants: + - name: Clear + description: Clear interrupt flag + value: 1 +enum/PLLP: + bit_size: 2 + variants: + - name: Div2 + description: PLLP=2 + value: 0 + - name: Div4 + description: PLLP=4 + value: 1 + - name: Div6 + description: PLLP=6 + value: 2 + - name: Div8 + description: PLLP=8 + value: 3 +enum/PLLRDYFR: + bit_size: 1 + variants: + - name: NotInterrupted + description: No clock ready interrupt + value: 0 + - name: Interrupted + description: Clock ready interrupt + value: 1 +enum/PLLRDYIE: + bit_size: 1 + variants: + - name: Disabled + description: Interrupt disabled + value: 0 + - name: Enabled + description: Interrupt enabled + value: 1 +enum/PLLRDYR: + bit_size: 1 + variants: + - name: NotReady + description: Clock not ready + value: 0 + - name: Ready + description: Clock ready + value: 1 +enum/PLLSRC: + bit_size: 1 + variants: + - name: HSI + description: HSI clock selected as PLL and PLLI2S clock entry + value: 0 + - name: HSE + description: HSE oscillator clock selected as PLL and PLLI2S clock entry + value: 1 +enum/PPRE: + bit_size: 3 + variants: + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 +enum/RMVFW: + bit_size: 1 + variants: + - name: Clear + description: Clears the reset flag + value: 1 +enum/RTCSEL: + bit_size: 2 + variants: + - name: NoClock + description: No clock + value: 0 + - name: LSE + description: LSE oscillator clock used as RTC clock + value: 1 + - name: LSI + description: LSI oscillator clock used as RTC clock + value: 2 + - name: HSE + description: HSE oscillator clock divided by a prescaler used as RTC clock + value: 3 +enum/SPREADSEL: + bit_size: 1 + variants: + - name: Center + description: Center spread + value: 0 + - name: Down + description: Down spread + value: 1 +enum/SW: + bit_size: 2 + variants: + - name: HSI + description: HSI selected as system clock + value: 0 + - name: HSE + description: HSE selected as system clock + value: 1 + - name: PLL + description: PLL selected as system clock + value: 2 +enum/SWSR: + bit_size: 2 + variants: + - name: HSI + description: HSI oscillator used as system clock + value: 0 + - name: HSE + description: HSE oscillator used as system clock + value: 1 + - name: PLL + description: PLL used as system clock + value: 2 +enum/TIMPRE: + bit_size: 1 + variants: + - name: Mul2 + description: "If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx" + value: 0 + - name: Mul4 + description: "If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx" + value: 1 diff --git a/parse.py b/parse.py index 8239f27..0b21927 100755 --- a/parse.py +++ b/parse.py @@ -319,6 +319,7 @@ perimap = [ ('STM32WL.*:SYS:.*', 'syscfg_wl5x/SYSCFG'), ('STM32L0.*:RCC:.*', 'rcc_l0/RCC'), ('STM32L4.*:RCC:.*', 'rcc_l4/RCC'), + ('STM32F410.*:RCC:.*', 'rcc_f410/RCC'), ('STM32F4.*:RCC:.*', 'rcc_f4/RCC'), ('STM32WL.*:RCC:.*', 'rcc_wl5x/RCC'), ('STM32F0.0.*:RCC:.*', 'rcc_f0x0/RCC'),