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Add enum/ADCSET to rcc_l5.yaml

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shakencodes 2023-11-01 12:39:09 -07:00
parent bcc9b6bf9f
commit 445f314531
1 changed files with 13 additions and 0 deletions
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data/registers/rcc_l5.yaml
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@ -1383,6 +1383,7 @@ fieldset/CCIPR1:
description: ADCs clock source selection description: ADCs clock source selection
bit_offset: 28 bit_offset: 28
bit_size: 2 bit_size: 2
enum: ADCSEL
fieldset/CCIPR2: fieldset/CCIPR2:
description: Peripherals independent clock configuration register description: Peripherals independent clock configuration register
fields: fields:
@ -1924,6 +1925,18 @@ fieldset/SECSR:
description: RMVFSECF description: RMVFSECF
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
enum/ADCSEL:
bit_size: 2
variants:
- name: DISABLE
description: No clock selected
value: 0
- name: PLL1_Q
description: PLLADC1CLK clock selected
value: 1
- name: SYS
description: SYSCLK clock selected
value: 3
enum/CLK48SEL: enum/CLK48SEL:
bit_size: 2 bit_size: 2
variants: variants: