From 445f314531ff63721c1e055a449a9d9f5cc691d7 Mon Sep 17 00:00:00 2001
From: shakencodes <shakencodes@gmail.com>
Date: Wed, 1 Nov 2023 12:39:09 -0700
Subject: [PATCH] Add enum/ADCSET to rcc_l5.yaml

---
 data/registers/rcc_l5.yaml | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/data/registers/rcc_l5.yaml b/data/registers/rcc_l5.yaml
index 2933f71..77e857b 100644
--- a/data/registers/rcc_l5.yaml
+++ b/data/registers/rcc_l5.yaml
@@ -1383,6 +1383,7 @@ fieldset/CCIPR1:
     description: ADCs clock source selection
     bit_offset: 28
     bit_size: 2
+    enum: ADCSEL
 fieldset/CCIPR2:
   description: Peripherals independent clock configuration register
   fields:
@@ -1924,6 +1925,18 @@ fieldset/SECSR:
     description: RMVFSECF
     bit_offset: 12
     bit_size: 1
+enum/ADCSEL:
+  bit_size: 2
+  variants:
+  - name: DISABLE
+    description: No clock selected
+    value: 0
+  - name: PLL1_Q
+    description: PLLADC1CLK clock selected
+    value: 1
+  - name: SYS
+    description: SYSCLK clock selected
+    value: 3
 enum/CLK48SEL:
   bit_size: 2
   variants: