Add STM32WBA support.

data/dmamux/WBA_GPDMA1.yaml

@@ -0,0 +1,50 @@
+ADC4: 0
+SPI1_RX: 1
+SPI1_TX: 2
+SPI3_RX: 3
+SPI3_TX: 4
+I2C1_RX: 5
+I2C1_TX: 6
+I2C1_EVC: 7
+I2C3_RX: 8
+I2C3_TX: 9
+I2C3_EVC: 10
+USART1_RX: 11
+USART1_TX: 12
+USART2_RX: 13
+USART2_TX: 14
+LPUART1_RX: 15
+LPUART1_TX: 16
+TIM1_CC1: 19
+TIM1_CC2: 20
+TIM1_CC3: 21
+TIM1_CC4: 22
+TIM1_UPD: 23
+TIM1_TRG: 24
+TIM1_COM: 25
+TIM2_CC1: 26
+TIM2_CC2: 27
+TIM2_CC3: 28
+TIM2_CC4: 29
+TIM2_UPD: 30
+TIM3_CC1: 31
+TIM3_CC2: 32
+TIM3_CC3: 33
+TIM3_CC4: 34
+TIM3_UPD: 35
+TIM3_TRG: 36
+TIM16_CC1: 37
+TIM16_UPD: 38
+TIM17_CC1: 39
+TIM17_UPD: 40
+AES_IN: 41
+AES_OUT: 42
+HASH_IN: 43
+SAES_IN: 44
+SAES_OUT: 45
+LPTIM1_IC1: 46
+LPTIM1_IC2: 47
+LPTIM1_UE: 48
+LPTIM2_IC1: 49
+LPTIM2_IC2: 50
+LPTIM2_UE: 51

data/registers/dbgmcu_wba.yaml

@@ -0,0 +1,339 @@
+block/DBGMCU:
+  description: Microcontroller debug unit
+  items:
+  - name: IDCODE
+    description: identity code register
+    byte_offset: 0
+    fieldset: IDCODE
+  - name: CR
+    description: status and configuration register
+    byte_offset: 4
+    fieldset: CR
+  - name: APB1LFZR
+    description: APB1L peripheral freeze register
+    byte_offset: 8
+    fieldset: APB1LFZR
+  - name: APB1HFZR
+    description: APB1H peripheral freeze register
+    byte_offset: 12
+    fieldset: APB1HFZR
+  - name: APB2FZR
+    description: APB2 peripheral freeze register
+    byte_offset: 16
+    fieldset: APB2FZR
+  - name: APB7FZR
+    description: APB7 peripheral freeze register
+    byte_offset: 36
+    fieldset: APB7FZR
+  - name: AHB1FZR
+    description: AHB1 peripheral freeze register
+    byte_offset: 40
+    fieldset: AHB1FZR
+  - name: SR
+    description: status register
+    byte_offset: 252
+    fieldset: SR
+  - name: DBG_AUTH_HOST
+    description: debug host authentication register
+    byte_offset: 256
+    fieldset: DBG_AUTH_HOST
+  - name: DBG_AUTH_DEVICE
+    description: debug device authentication register
+    byte_offset: 260
+    fieldset: DBG_AUTH_DEVICE
+  - name: PNCR
+    description: part number codification register
+    byte_offset: 2012
+    fieldset: PNCR
+  - name: PIDR4
+    description: CoreSight peripheral identity register 4
+    byte_offset: 4048
+    fieldset: PIDR4
+  - name: PIDR0
+    description: CoreSight peripheral identity register 0
+    byte_offset: 4064
+    fieldset: PIDR0
+  - name: PIDR1
+    description: CoreSight peripheral identity register 1
+    byte_offset: 4068
+    fieldset: PIDR1
+  - name: PIDR2
+    description: CoreSight peripheral identity register 2
+    byte_offset: 4072
+    fieldset: PIDR2
+  - name: PIDR3
+    description: CoreSight peripheral identity register 3
+    byte_offset: 4076
+    fieldset: PIDR3
+  - name: CIDR0
+    description: CoreSight component identity register 0
+    byte_offset: 4080
+    fieldset: CIDR0
+  - name: CIDR1
+    description: CoreSight peripheral identity register 1
+    byte_offset: 4084
+    fieldset: CIDR1
+  - name: CIDR2
+    description: CoreSight component identity register 2
+    byte_offset: 4088
+    fieldset: CIDR2
+  - name: CIDR3
+    description: CoreSight component identity register 3
+    byte_offset: 4092
+    fieldset: CIDR3
+fieldset/AHB1FZR:
+  description: AHB1 peripheral freeze register
+  fields:
+  - name: DBG_GPDMA1_CH0_STOP
+    description: "GPDMA 1 channel 0 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC0."
+    bit_offset: 0
+    bit_size: 1
+  - name: DBG_GPDMA1_CH1_STOP
+    description: "GPDMA 1 channel 1 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC1."
+    bit_offset: 1
+    bit_size: 1
+  - name: DBG_GPDMA1_CH2_STOP
+    description: "GPDMA 1 channel 2 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC2."
+    bit_offset: 2
+    bit_size: 1
+  - name: DBG_GPDMA1_CH3_STOP
+    description: "GPDMA 1 channel 3 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC3."
+    bit_offset: 3
+    bit_size: 1
+  - name: DBG_GPDMA1_CH4_STOP
+    description: "GPDMA 1 channel 4 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC4."
+    bit_offset: 4
+    bit_size: 1
+  - name: DBG_GPDMA1_CH5_STOP
+    description: "GPDMA 1 channel 5 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC5."
+    bit_offset: 5
+    bit_size: 1
+  - name: DBG_GPDMA1_CH6_STOP
+    description: "GPDMA 1 channel 6 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC6."
+    bit_offset: 6
+    bit_size: 1
+  - name: DBG_GPDMA1_CH7_STOP
+    description: "GPDMA 1 channel 7 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC7."
+    bit_offset: 7
+    bit_size: 1
+fieldset/APB1HFZR:
+  description: APB1H peripheral freeze register
+  fields:
+  - name: DBG_LPTIM2_STOP
+    description: "LPTIM2 stop in CPU debug\r Write access can be protected by GTZC_TZSC.LPTIM2SEC."
+    bit_offset: 5
+    bit_size: 1
+fieldset/APB1LFZR:
+  description: APB1L peripheral freeze register
+  fields:
+  - name: DBG_TIM2_STOP
+    description: "TIM2 stop in CPU debug\r Write access can be protected by GTZC_TZSC.TIM2SEC."
+    bit_offset: 0
+    bit_size: 1
+  - name: DBG_TIM3_STOP
+    description: "TIM3 stop in CPU debug\r Write access can be protected by GTZC_TZSC.TIM3SEC."
+    bit_offset: 1
+    bit_size: 1
+  - name: DBG_WWDG_STOP
+    description: "WWDG stop in CPU debug\r Write access can be protected by GTZC_TZSC.WWDGSEC"
+    bit_offset: 11
+    bit_size: 1
+  - name: DBG_IWDG_STOP
+    description: "IWDG stop in CPU debug\r Write access can be protected by GTZC_TZSC.IWDGSEC."
+    bit_offset: 12
+    bit_size: 1
+  - name: DBG_I2C1_STOP
+    description: "I2C1 SMBUS timeout stop in CPU debug\r Write access can be protected by GTZC_TZSC.I2C1SEC."
+    bit_offset: 21
+    bit_size: 1
+fieldset/APB2FZR:
+  description: APB2 peripheral freeze register
+  fields:
+  - name: DBG_TIM1_STOP
+    description: "TIM1 stop in CPU debug\r Write access can be protected by GTZC_TZSC.TIM1SEC."
+    bit_offset: 11
+    bit_size: 1
+  - name: DBG_TIM16_STOP
+    description: "TIM16 stop in CPU debug\r Write access can be protected by GTZC_TZSC.TIM16SEC."
+    bit_offset: 17
+    bit_size: 1
+  - name: DBG_TIM17_STOP
+    description: "TIM17 stop in CPU debug\r Write access can be protected by GTZC_TZSC.TIM17SEC."
+    bit_offset: 18
+    bit_size: 1
+fieldset/APB7FZR:
+  description: APB7 peripheral freeze register
+  fields:
+  - name: DBG_I2C3_STOP
+    description: "I2C3 stop in CPU debug\r Access can be protected by GTZC_TZSC.I2C3SEC."
+    bit_offset: 10
+    bit_size: 1
+  - name: DBG_LPTIM1_STOP
+    description: "LPTIM1 stop in CPU debug\r Access can be protected by GTZC_TZSC.LPTIM1SEC."
+    bit_offset: 17
+    bit_size: 1
+  - name: DBG_RTC_STOP
+    description: "RTC stop in CPU debug\r Access can be protected by GTZC_TZSC.TIM17SEC.\r Can only be accessed secure when one or more features in the RTC or TAMP is/are secure."
+    bit_offset: 30
+    bit_size: 1
+fieldset/CIDR0:
+  description: CoreSight component identity register 0
+  fields:
+  - name: PREAMBLE
+    description: Component ID bits [7:0]
+    bit_offset: 0
+    bit_size: 8
+fieldset/CIDR1:
+  description: CoreSight peripheral identity register 1
+  fields:
+  - name: PREAMBLE
+    description: Component ID bits [11:8]
+    bit_offset: 0
+    bit_size: 4
+  - name: CLASS
+    description: Component ID bits [15:12] - component class
+    bit_offset: 4
+    bit_size: 4
+fieldset/CIDR2:
+  description: CoreSight component identity register 2
+  fields:
+  - name: PREAMBLE
+    description: Component ID bits [23:16]
+    bit_offset: 0
+    bit_size: 8
+fieldset/CIDR3:
+  description: CoreSight component identity register 3
+  fields:
+  - name: PREAMBLE
+    description: Component ID bits [31:24]
+    bit_offset: 0
+    bit_size: 8
+fieldset/CR:
+  description: status and configuration register
+  fields:
+  - name: DBG_STOP
+    description: "Allows debug in Stop mode\r Write access can be protected by PWR_SECCFGR.LPMSEC.\r The CPU debug and clocks remain active and the HSI16 oscillators is used as system clock during Stop debug mode, allowing CPU debug capability. On exit from Stop mode, the clock settings are set to the Stop mode exit state."
+    bit_offset: 1
+    bit_size: 1
+  - name: DBG_STANDBY
+    description: "Allows debug in Standby mode\r Write access can be protected by PWR_SECCFGR.LPMSEC.\r The CPU debug and clocks remain active and the HSI16 oscillator is used as system clock, the supply and SRAM memory content is maintained during Standby debug mode, allowing CPU debug capability. On exit from Standby mode, a standby reset is performed."
+    bit_offset: 2
+    bit_size: 1
+  - name: LPMS
+    description: "Device low power mode selected\r 10x: Standby mode\r others reserved"
+    bit_offset: 16
+    bit_size: 3
+  - name: STOPF
+    description: Device Stop flag
+    bit_offset: 19
+    bit_size: 1
+  - name: SBF
+    description: Device Standby flag
+    bit_offset: 20
+    bit_size: 1
+  - name: CS
+    description: CPU Sleep
+    bit_offset: 24
+    bit_size: 1
+  - name: CDS
+    description: CPU DeepSleep
+    bit_offset: 25
+    bit_size: 1
+fieldset/DBG_AUTH_DEVICE:
+  description: debug device authentication register
+  fields:
+  - name: AUTH_ID
+    description: "Device specific ID\r Device specific ID used for RDP regression."
+    bit_offset: 0
+    bit_size: 32
+fieldset/DBG_AUTH_HOST:
+  description: debug host authentication register
+  fields:
+  - name: AUTH_KEY
+    description: "Device authentication key\r The device specific 64-bit authentication key (OEMn key) must be written to this register (in two successive 32-bit writes, least significant word first) to permit RDP regression. Writing a wrong key locks access to the device and prevent code execution from the Flash memory."
+    bit_offset: 0
+    bit_size: 32
+fieldset/IDCODE:
+  description: identity code register
+  fields:
+  - name: DEV_ID
+    description: Device ID
+    bit_offset: 0
+    bit_size: 12
+  - name: REV_ID
+    description: Revision ID
+    bit_offset: 16
+    bit_size: 16
+fieldset/PIDR0:
+  description: CoreSight peripheral identity register 0
+  fields:
+  - name: PARTNUM
+    description: Part number bits [7:0]
+    bit_offset: 0
+    bit_size: 8
+fieldset/PIDR1:
+  description: CoreSight peripheral identity register 1
+  fields:
+  - name: PARTNUM
+    description: Part number bits [11:8]
+    bit_offset: 0
+    bit_size: 4
+  - name: JEP106ID
+    description: JEP106 identity code bits [3:0]
+    bit_offset: 4
+    bit_size: 4
+fieldset/PIDR2:
+  description: CoreSight peripheral identity register 2
+  fields:
+  - name: JEP106ID
+    description: JEP106 identity code bits [6:4]
+    bit_offset: 0
+    bit_size: 3
+  - name: JEDEC
+    description: JEDEC assigned value
+    bit_offset: 3
+    bit_size: 1
+  - name: REVISION
+    description: Component revision number
+    bit_offset: 4
+    bit_size: 4
+fieldset/PIDR3:
+  description: CoreSight peripheral identity register 3
+  fields:
+  - name: CMOD
+    description: Customer modified
+    bit_offset: 0
+    bit_size: 4
+  - name: REVAND
+    description: Metal fix version
+    bit_offset: 4
+    bit_size: 4
+fieldset/PIDR4:
+  description: CoreSight peripheral identity register 4
+  fields:
+  - name: JEP106CON
+    description: JEP106 continuation code
+    bit_offset: 0
+    bit_size: 4
+  - name: F4KCOUNT
+    description: Register file size
+    bit_offset: 4
+    bit_size: 4
+fieldset/PNCR:
+  description: part number codification register
+  fields:
+  - name: CODIFICATION
+    description: Part number codification
+    bit_offset: 0
+    bit_size: 32
+fieldset/SR:
+  description: status register
+  fields:
+  - name: AP_PRESENT
+    description: "Bit n identifies whether access port APn is present in device \r Bit n<>=<3D>0: APn absent \r Bit n<>=<3D>1: APn present"
+    bit_offset: 0
+    bit_size: 16
+  - name: AP_ENABLED
+    description: "Bit n identifies whether access port APn is open (can be accessed via the debug port) or locked (debug access to the APn is blocked, except for access) \r Bit n<>=<3D>0: APn locked (except for access to DBGMCU)\r Bit n<>=<3D>1: APn enabled"
+    bit_offset: 16
+    bit_size: 16

data/registers/flash_wba.yaml

@@ -0,0 +1,643 @@
+block/FLASH:
+  description: Embedded memory
+  items:
+  - name: ACR
+    description: access control register
+    byte_offset: 0
+    fieldset: ACR
+  - name: NSKEYR
+    description: key register
+    byte_offset: 8
+    fieldset: NSKEYR
+  - name: SECKEYR
+    description: secure key register
+    byte_offset: 12
+    fieldset: SECKEYR
+  - name: OPTKEYR
+    description: option key register
+    byte_offset: 16
+    fieldset: OPTKEYR
+  - name: PDKEYR
+    description: power-down key register
+    byte_offset: 24
+    fieldset: PDKEYR
+  - name: NSSR
+    description: status register
+    byte_offset: 32
+    fieldset: NSSR
+  - name: SECSR
+    description: secure status register
+    byte_offset: 36
+    fieldset: SECSR
+  - name: NSCR1
+    description: control register
+    byte_offset: 40
+    fieldset: NSCR1
+  - name: SECCR1
+    description: secure control register
+    byte_offset: 44
+    fieldset: SECCR1
+  - name: ECCR
+    description: ECC register
+    byte_offset: 48
+    fieldset: ECCR
+  - name: OPSR
+    description: operation status register
+    byte_offset: 52
+    fieldset: OPSR
+  - name: NSCR2
+    description: control 2 register
+    byte_offset: 56
+    fieldset: NSCR2
+  - name: SECCR2
+    description: secure control 2 register
+    byte_offset: 60
+    fieldset: SECCR2
+  - name: OPTR
+    description: option register
+    byte_offset: 64
+    fieldset: OPTR
+  - name: NSBOOTADD0R
+    description: boot address 0 register
+    byte_offset: 68
+    fieldset: NSBOOTADD0R
+  - name: NSBOOTADD1R
+    description: boot address 1 register
+    byte_offset: 72
+    fieldset: NSBOOTADD1R
+  - name: SECBOOTADD0R
+    description: secure boot address 0 register
+    byte_offset: 76
+    fieldset: SECBOOTADD0R
+  - name: SECWMR1
+    description: secure watermark register 1
+    byte_offset: 80
+    fieldset: SECWMR1
+  - name: SECWMR2
+    description: secure watermark register 2
+    byte_offset: 84
+    fieldset: SECWMR2
+  - name: WRPAR
+    description: WRP area A address register
+    byte_offset: 88
+    fieldset: WRPAR
+  - name: WRPBR
+    description: WRP area B address register
+    byte_offset: 92
+    fieldset: WRPBR
+  - name: OEM1KEYR1
+    description: OEM1 key register 1
+    byte_offset: 112
+  - name: OEM1KEYR2
+    description: OEM1 key register 2
+    byte_offset: 116
+  - name: OEM2KEYR1
+    description: OEM2 key register 1
+    byte_offset: 120
+  - name: OEM2KEYR2
+    description: OEM2 key register 2
+    byte_offset: 124
+  - name: SECBBR
+    description: secure block based register 1
+    array:
+      len: 4
+      stride: 4
+    byte_offset: 128
+    fieldset: BBR
+  - name: SECHDPCR
+    description: secure HDP control register
+    byte_offset: 192
+    fieldset: SECHDPCR
+  - name: PRIFCFGR
+    description: privilege configuration register
+    byte_offset: 196
+    fieldset: PRIFCFGR
+  - name: PRIVBBR
+    description: privilege block based register 1
+    array:
+      len: 4
+      stride: 4
+    byte_offset: 208
+    fieldset: BBR
+fieldset/ACR:
+  description: access control register
+  fields:
+  - name: LATENCY
+    description: "Latency\r These bits represent the ratio between the AHB hclk1 clock period and the memory access time.\r Access to the bit can be secured by RCC SYSCLKSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.\r ...\r Note: Before entering Stop 1 mode software must set wait state latency to at least 1."
+    bit_offset: 0
+    bit_size: 4
+  - name: PRFTEN
+    description: "Prefetch enable\r This bit enables the prefetch buffer in the embedded memory.\r This bit can be protected against unprivileged access by NSPRIV."
+    bit_offset: 8
+    bit_size: 1
+  - name: LPM
+    description: "Low-power read mode\r This bit puts the memory in low-power read mode.\r Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.\r This bit can’t be written when a program or erase operation is busy (BSY = 1) or when the write buffer is not empty (WDW = 1). Changing this bit while a program or erase operation is busy (BSY = 1) is rejected."
+    bit_offset: 11
+    bit_size: 1
+  - name: PDREQ
+    description: "power-down mode request\r This bit requests to enter power-down mode. When enters power-down mode, this bit is cleared by hardware and the PDKEYR is locked.\r This bit is write-protected with PDKEYR. \r Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV."
+    bit_offset: 12
+    bit_size: 1
+  - name: SLEEP_PD
+    description: "memory power-down mode during Sleep mode\r This bit determines whether the memory is in power-down mode or Idle mode when the device is in Sleep mode.\r Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.\r The must not be put in power-down while a program or an erase operation is ongoing."
+    bit_offset: 14
+    bit_size: 1
+fieldset/BBR:
+  description: block based register
+  fields:
+  - name: BLOCK
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 32
+      stride: 1
+fieldset/ECCR:
+  description: ECC register
+  fields:
+  - name: ADDR_ECC
+    description: "ECC fail address\r This field indicates which address is concerned by the ECC error correction or by the double ECC error detection. The address is given relative to base address, from offset 0x0<78>0000 to 0xF<78>FFF0.\r Note that bit 19 is reserved on STM32WBAxEx devices."
+    bit_offset: 0
+    bit_size: 20
+  - name: SYSF_ECC
+    description: "System memory ECC fail\r This bit indicates that the ECC error correction or double ECC error detection is located in the system memory."
+    bit_offset: 22
+    bit_size: 1
+  - name: ECCIE
+    description: "ECC correction interrupt enable\r This bit enables the interrupt generation when the ECCC bit in the ECCR register is set."
+    bit_offset: 24
+    bit_size: 1
+  - name: ECCC
+    description: "ECC correction\r This bit is set by hardware when one ECC error has been detected and corrected (only if ECCC and ECCD were previously cleared). An interrupt is generated if ECCIE is set. This bit is cleared by writing 1."
+    bit_offset: 30
+    bit_size: 1
+  - name: ECCD
+    description: "ECC detection\r This bit is set by hardware when two ECC errors have been detected (only if ECCC and ECCD were previously cleared). When this bit is set, a NMI is generated. This bit is cleared by writing 1."
+    bit_offset: 31
+    bit_size: 1
+fieldset/NSBOOTADD0R:
+  description: boot address 0 register
+  fields:
+  - name: NSBOOTADD0
+    description: "Non-secure boot base address 0\r This address is only used when TZEN = 0.\r The non-secure boot memory address can be programmed to any address in the valid address range (see Table 28: Boot space versus RDP protection) with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or NSWBOOT0 state.\r Examples:\r NSBOOTADD0[24:0] = 0x0100000: Boot from memory (0x0800 0000)\r NSBOOTADD0[24:0] = 0x017F100: Boot from system memory bootloader (0x0BF8 8000)\r NSBOOTADD0[24:0] = 0x0400200: Boot from SRAM2 on S-Bus (0x2001 0000)"
+    bit_offset: 7
+    bit_size: 25
+fieldset/NSBOOTADD1R:
+  description: boot address 1 register
+  fields:
+  - name: NSBOOTADD1
+    description: "Non-secure boot address 1\r This address is only used when TZEN = 0.\r The non-secure boot memory address can be programmed to any address in the valid address range (see Table 28: Boot space versus RDP protection) with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or NSWBOOT0 state. \r Examples:\r NSBOOTADD1[24:0] = 0x0100000: Boot from memory (0x0800 0000)\r NSBOOTADD1[24:0] = 0x017F100: Boot from system memory bootloader (0x0BF8 8000)\r NSBOOTADD1[24:0] = 0x0400200: Boot from SRAM2 (0x2001 0000)"
+    bit_offset: 7
+    bit_size: 25
+fieldset/NSCR1:
+  description: control register
+  fields:
+  - name: PG
+    description: Non-secure programming
+    bit_offset: 0
+    bit_size: 1
+  - name: PER
+    description: Non-secure page erase
+    bit_offset: 1
+    bit_size: 1
+  - name: MER
+    description: "Non-secure mass erase\r This bit triggers the non-secure mass erase (all user pages) when set."
+    bit_offset: 2
+    bit_size: 1
+  - name: PNB
+    description: "Non-secure page number selection\r These bits select the page to erase.\r ...\r Note that bit 9 is reserved on STM32WBA5xEx devices."
+    bit_offset: 3
+    bit_size: 7
+  - name: BWR
+    description: "Non-secure burst write programming mode\r When set, this bit selects the burst write programming mode."
+    bit_offset: 14
+    bit_size: 1
+  - name: STRT
+    description: "Non-secure operation start \r This bit triggers a non-secure erase operation when set. If MER and PER bits are reset and the STRT bit is set, the PGSERR bit in NSSR is set (this condition is forbidden).\r This bit is set only by software and is cleared when the BSY bit is cleared in NSSR."
+    bit_offset: 16
+    bit_size: 1
+  - name: OPTSTRT
+    description: "Options modification start\r This bit triggers an option bytes erase and program operation when set. This bit is write-protected with OPTLOCK.. This bit is set only by software, and is cleared when the BSY bit is cleared in NSSR."
+    bit_offset: 17
+    bit_size: 1
+  - name: EOPIE
+    description: "Non-secure end of operation interrupt enable\r This bit enables the interrupt generation when the EOP bit in the NSSR is set to 1."
+    bit_offset: 24
+    bit_size: 1
+  - name: ERRIE
+    description: "Non-secure error interrupt enable\r This bit enables the interrupt generation when the OPERR bit in the NSSR is set to 1."
+    bit_offset: 25
+    bit_size: 1
+  - name: OBL_LAUNCH
+    description: "Force the option byte loading\r When set to 1, this bit forces the option byte reloading. This bit is cleared only when the option byte loading is complete. This bit is write-protected with OPTLOCK.\r Note: The LSE oscillator must be disabled, LSEON = 0 and LSERDY = 0, before starting OBL_LAUNCH."
+    bit_offset: 27
+    bit_size: 1
+  - name: OPTLOCK
+    description: "Option lock\r This bit is set only. When set, the NSCR1.OPTSRT and OBL_LAUNCH bits concerning user options write access is locked. This bit is cleared by hardware after detecting the unlock sequence in OPTKEYR. The NSCR1.LOCK bit must be cleared before doing the OPTKEYR unlock sequence.\r In case of an unsuccessful unlock operation, this bit remains set until the next reset."
+    bit_offset: 30
+    bit_size: 1
+  - name: LOCK
+    description: "Non-secure lock\r This bit is set only.\r When set, the NSCR1 register write access is locked. This bit is cleared by hardware after detecting the unlock sequence in NSKEYR.\r In case of an unsuccessful unlock operation, this bit remains set until the next system reset."
+    bit_offset: 31
+    bit_size: 1
+fieldset/NSCR2:
+  description: control 2 register
+  fields:
+  - name: PS
+    description: Program suspend request
+    bit_offset: 0
+    bit_size: 1
+  - name: ES
+    description: Erase suspend request
+    bit_offset: 1
+    bit_size: 1
+fieldset/NSKEYR:
+  description: key register
+  fields:
+  - name: NSKEY
+    description: "memory non-secure key\r The following values must be written consecutively to unlock the NSCR1 register, allowing the memory non-secure programming/erasing operations:\r KEY1: 0x4567<36>0123\r KEY2: 0xCDEF<45>89AB"
+    bit_offset: 0
+    bit_size: 32
+fieldset/NSSR:
+  description: status register
+  fields:
+  - name: EOP
+    description: "Non-secure end of operation\r This bit is set by hardware when one or more memory non-secure operation (program/erase) has been completed successfully. This bit is set only if the non-secure end of operation interrupts are enabled (EOPIE = 1 in NSCR1). This bit is cleared by writing<6E>1."
+    bit_offset: 0
+    bit_size: 1
+  - name: OPERR
+    description: "Non-secure operation error\r This bit is set by hardware when a memory non-secure operation (program/erase) completes unsuccessfully. This bit is set only if non-secure error interrupts are enabled (NSERRIE = 1). This bit is cleared by writing 1."
+    bit_offset: 1
+    bit_size: 1
+  - name: PROGERR
+    description: "Non-secure programming error\r This bit is set by hardware when a non-secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1."
+    bit_offset: 3
+    bit_size: 1
+  - name: WRPERR
+    description: "Non-secure write protection error\r This bit is set by hardware when a non-secure address to be erased/programmed belongs to a write-protected part (by WRP or HDP) of the memory. This bit is cleared by writing 1.\r Refer to Section<6F>7.3.10: memory errors flags for full conditions of error flag setting."
+    bit_offset: 4
+    bit_size: 1
+  - name: PGAERR
+    description: "Non-secure programming alignment error\r This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address. This bit is cleared by writing 1."
+    bit_offset: 5
+    bit_size: 1
+  - name: SIZERR
+    description: "Non-secure size error\r This bit is set by hardware when the size of the access is a byte or half-word during a non-secure program sequence. Only quad-word programming is allowed by means of successive word accesses. This bit is cleared by writing 1."
+    bit_offset: 6
+    bit_size: 1
+  - name: PGSERR
+    description: "Non-secure programming sequence error\r This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1.\r Refer to Section<6F>7.3.10: memory errors flags for full conditions of error flag setting."
+    bit_offset: 7
+    bit_size: 1
+  - name: OPTWERR
+    description: "Option write error \r This bit is set by hardware when the options bytes are written with an invalid configuration or when modifying options in RDP level 2.. It is cleared by writing 1.\r Refer to Section<6F>7.3.10: memory errors flags for full conditions of error flag setting."
+    bit_offset: 13
+    bit_size: 1
+  - name: BSY
+    description: "Non-secure busy\r This indicates that a memory secure or non-secure operation is in progress. This bit is set at the beginning of a operation and reset when the operation finishes or when an error occurs."
+    bit_offset: 16
+    bit_size: 1
+  - name: WDW
+    description: "Non-secure wait data to write\r This bit indicates that the memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the memory."
+    bit_offset: 17
+    bit_size: 1
+  - name: OEM1LOCK
+    description: "OEM1 key RDP lock\r This bit indicates that the OEM1 key read during the OBL is not virgin. When set, the OEM1 key RDP lock mechanism is active."
+    bit_offset: 18
+    bit_size: 1
+  - name: OEM2LOCK
+    description: "OEM2 key RDP lock\r This bit indicates that the OEM2 key read during the OBL is not virgin. When set, the OEM2 key RDP lock mechanism is active."
+    bit_offset: 19
+    bit_size: 1
+  - name: PD
+    description: "in power-down mode\r This bit indicates that the memory is in power-down state. It is reset when is in normal mode or being awaken."
+    bit_offset: 20
+    bit_size: 1
+fieldset/OPSR:
+  description: operation status register
+  fields:
+  - name: ADDR_OP
+    description: "Interrupted operation address\r This field indicates which address in the memory was accessed when reset occurred. The address is given relative to the base address, from offset 0x0<78>0000 to 0xF<78>FFF0.\r Note that bit 19 is reserved on STM32WBAxEx devices."
+    bit_offset: 0
+    bit_size: 20
+  - name: SYSF_OP
+    description: "Operation in system memory interrupted\r This bit indicates that the reset occurred during an operation in the system memory."
+    bit_offset: 22
+    bit_size: 1
+  - name: CODE_OP
+    description: "memory operation code\r This field indicates which memory operation has been interrupted by a system reset:"
+    bit_offset: 29
+    bit_size: 3
+    enum: CODE_OP
+fieldset/OPTKEYR:
+  description: option key register
+  fields:
+  - name: OPTKEY
+    description: "Option byte key\r The LOCK bit in the NSCR1 must be cleared before doing the unlock sequence for OPTLOCK bit. The following values must be written consecutively to unlock the NSCR1.OPTSTRT and OBL_LAUNCH register bits concerning user option operations:\r KEY1: 0x0819<31>2A3B\r KEY2: 0x4C5D<35>6E7F"
+    bit_offset: 0
+    bit_size: 32
+fieldset/OPTR:
+  description: option register
+  fields:
+  - name: RDP
+    description: "Readout protection level\r Others: Level 1 (memories readout protection active)\r Note: Refer to Section<6F>7.6.2: Readout protection (RDP) for more details."
+    bit_offset: 0
+    bit_size: 8
+    enum: RDP
+  - name: BOR_LEV
+    description: "BOR reset level\r These bits contain the V<sub>DD</sub> supply level threshold that activates/releases the reset."
+    bit_offset: 8
+    bit_size: 3
+    enum: BOR_LEV
+  - name: NRST_STOP
+    description: Reset generation in Stop mode
+    bit_offset: 12
+    bit_size: 1
+  - name: NRST_STDBY
+    description: Reset generation in Standby mode
+    bit_offset: 13
+    bit_size: 1
+  - name: SRAM1_RST
+    description: SRAM1 erase upon system reset
+    bit_offset: 15
+    bit_size: 1
+  - name: IWDG_SW
+    description: Independent watchdog enable selection
+    bit_offset: 16
+    bit_size: 1
+  - name: IWDG_STOP
+    description: Independent watchdog counter freeze in Stop mode
+    bit_offset: 17
+    bit_size: 1
+  - name: IWDG_STDBY
+    description: Independent watchdog counter freeze in Standby mode
+    bit_offset: 18
+    bit_size: 1
+  - name: WWDG_SW
+    description: Window watchdog selection
+    bit_offset: 19
+    bit_size: 1
+  - name: SRAM2_PE
+    description: SRAM2 parity check enable
+    bit_offset: 24
+    bit_size: 1
+  - name: SRAM2_RST
+    description: SRAM2 erase when system reset
+    bit_offset: 25
+    bit_size: 1
+  - name: NSWBOOT0
+    description: Software BOOT0
+    bit_offset: 26
+    bit_size: 1
+  - name: NBOOT0
+    description: NBOOT0 option bit
+    bit_offset: 27
+    bit_size: 1
+  - name: TZEN
+    description: Global TrustZone security enable
+    bit_offset: 31
+    bit_size: 1
+fieldset/PDKEYR:
+  description: power-down key register
+  fields:
+  - name: PDKEY1
+    description: "power-down key\r The following values must be written consecutively to unlock the PDREQ bit in ACR:\r PDKEY_1: 0x0415<31>2637\r PDKEY_2: 0xFAFB<46>FCFD"
+    bit_offset: 0
+    bit_size: 32
+fieldset/PRIFCFGR:
+  description: privilege configuration register
+  fields:
+  - name: SPRIV
+    description: "Privileged protection for secure registers\r This bit is secure write protected. It can only be written by a secure privileged access when TrustZone is enabled (TZEN<45>=<3D>1)."
+    bit_offset: 0
+    bit_size: 1
+  - name: NSPRIV
+    description: Privileged protection for non-secure registers
+    bit_offset: 1
+    bit_size: 1
+fieldset/SECBOOTADD0R:
+  description: secure boot address 0 register
+  fields:
+  - name: BOOT_LOCK
+    description: "Boot lock\r This lock is only used when TZEN = 0.\r When set, the boot is always forced to base address value programmed in SECBOOTADD0[24:0] option bytes whatever the boot selection option. When set, this bit can only be cleared by an RDP regression level 1 to level 0."
+    bit_offset: 0
+    bit_size: 1
+  - name: SECBOOTADD0
+    description: "Secure boot base address 0\r This address is only used when TZEN = 1.\r The secure boot memory address can be programmed to any address in the valid address range (see Table<6C>28: Boot space versus RDP protection) with a granularity of 128 bytes. This bits correspond to address [31:7] The SECBOOTADD0 option bytes are selected following the BOOT0 pin or NSWBOOT0 state. \r Examples:\r SECBOOTADD0[24:0] = 0x018 0000: Boot from secure user memory (0x0C00 0000)\r SECBOOTADD0[24:0] = 0x01F F000: Boot from RSS system memory (0x0FF8 0000)\r SECBOOTADD0[24:0] = 0x060 0000: Boot from secure SRAM1 on S-Bus (0x3000 0000)"
+    bit_offset: 7
+    bit_size: 25
+fieldset/SECCR1:
+  description: secure control register
+  fields:
+  - name: PG
+    description: Secure programming
+    bit_offset: 0
+    bit_size: 1
+  - name: PER
+    description: Secure page erase
+    bit_offset: 1
+    bit_size: 1
+  - name: MER
+    description: "Secure mass erase\r This bit triggers the secure mass erase (all user pages) when set."
+    bit_offset: 2
+    bit_size: 1
+  - name: PNB
+    description: "Secure page number selection\r These bits select the page to erase:\r ...\r Note that bit 9 is reserved on STM32WBA5xEx devices."
+    bit_offset: 3
+    bit_size: 7
+  - name: BWR
+    description: "Secure burst write programming mode\r When set, this bit selects the burst write programming mode."
+    bit_offset: 14
+    bit_size: 1
+  - name: STRT
+    description: "Secure start \r This bit triggers a secure erase operation when set. If MER and PER bits are reset and the STRT bit is set, the PGSERR in the SECSR is set (this condition is forbidden).\r This bit is set only by software and is cleared when the BSY bit is cleared in SECSR."
+    bit_offset: 16
+    bit_size: 1
+  - name: EOPIE
+    description: "Secure End of operation interrupt enable\r This bit enables the interrupt generation when the EOP bit in SECSR is set to 1."
+    bit_offset: 24
+    bit_size: 1
+  - name: ERRIE
+    description: "Secure error interrupt enable\r This bit enables the interrupt generation when the OPERR bit in SECSR is set to 1."
+    bit_offset: 25
+    bit_size: 1
+  - name: INV
+    description: "memory security state invert\r This bit inverts the memory security state."
+    bit_offset: 29
+    bit_size: 1
+  - name: LOCK
+    description: "Secure lock\r This bit is set only. When set, the SECCR1 register is locked. It is cleared by hardware after detecting the unlock sequence in SECKEYR register.\r In case of an unsuccessful unlock operation, this bit remains set until the next system reset."
+    bit_offset: 31
+    bit_size: 1
+fieldset/SECCR2:
+  description: secure control 2 register
+  fields:
+  - name: PS
+    description: Program suspend request
+    bit_offset: 0
+    bit_size: 1
+  - name: ES
+    description: Erase suspend request
+    bit_offset: 1
+    bit_size: 1
+fieldset/SECHDPCR:
+  description: secure HDP control register
+  fields:
+  - name: HDP_ACCDIS
+    description: "Secure HDP area access disable \r When set, this bit is only cleared by a system reset."
+    bit_offset: 0
+    bit_size: 1
+fieldset/SECKEYR:
+  description: secure key register
+  fields:
+  - name: SECKEY
+    description: "memory secure key\r The following values must be written consecutively to unlock the SECCR1 register, allowing the memory secure programming/erasing operations:\r KEY1: 0x4567<36>0123\r KEY2: 0xCDEF<45>89AB"
+    bit_offset: 0
+    bit_size: 32
+fieldset/SECSR:
+  description: secure status register
+  fields:
+  - name: EOP
+    description: "Secure end of operation\r This bit is set by hardware when one or more memory secure operation (program/erase) has been completed successfully. This bit is set only if the secure end of operation interrupts are enabled (EOPIE = 1 in SECCR1). This bit is cleared by writing<6E>1."
+    bit_offset: 0
+    bit_size: 1
+  - name: OPERR
+    description: "Secure operation error\r This bit is set by hardware when a memory secure operation (program/erase) completes unsuccessfully. This bit is set only if secure error interrupts are enabled (SECERRIE = 1). This bit is cleared by writing 1."
+    bit_offset: 1
+    bit_size: 1
+  - name: PROGERR
+    description: "Secure programming error\r This bit is set by hardware when a secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1."
+    bit_offset: 3
+    bit_size: 1
+  - name: WRPERR
+    description: "Secure write protection error\r This bit is set by hardware when an secure address to be erased/programmed belongs to a write-protected part (by WRP or HDP) of the memory. This bit is cleared by writing 1.\r Refer to Section<6F>7.3.10: memory errors flags for full conditions of error flag setting."
+    bit_offset: 4
+    bit_size: 1
+  - name: PGAERR
+    description: "Secure programming alignment error\r This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address.This bit is cleared by writing 1."
+    bit_offset: 5
+    bit_size: 1
+  - name: SIZERR
+    description: "Secure size error\r This bit is set by hardware when the size of the access is a byte or half-word during a secure program sequence. Only quad-word programming is allowed by means of successive word accesses.This bit is cleared by writing 1."
+    bit_offset: 6
+    bit_size: 1
+  - name: PGSERR
+    description: "Secure programming sequence error\r This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1.\r Refer to Section<6F>7.3.10: memory errors flags for full conditions of error flag setting."
+    bit_offset: 7
+    bit_size: 1
+  - name: BSY
+    description: "Secure busy\r This bit indicates that a memory secure or non-secure operation is in progress. This is set on the beginning of a operation and reset when the operation finishes or when an error occurs."
+    bit_offset: 16
+    bit_size: 1
+  - name: WDW
+    description: "Secure wait data to write\r This bit indicates that the memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the memory."
+    bit_offset: 17
+    bit_size: 1
+fieldset/SECWMR1:
+  description: secure watermark register 1
+  fields:
+  - name: SECWM_PSTRT
+    description: "Start page of secure area\r This field contains the first page of the secure area."
+    bit_offset: 0
+    bit_size: 7
+  - name: SECWM_PEND
+    description: "End page of secure area\r This field contains the last page of the secure area."
+    bit_offset: 16
+    bit_size: 7
+fieldset/SECWMR2:
+  description: secure watermark register 2
+  fields:
+  - name: HDP_PEND
+    description: "End page of secure hide protection area\r This field contains the last page of the secure HDP area."
+    bit_offset: 16
+    bit_size: 7
+  - name: HDPEN
+    description: Secure Hide protection area enable
+    bit_offset: 31
+    bit_size: 1
+fieldset/WRPAR:
+  description: WRP area A address register
+  fields:
+  - name: WRPA_PSTRT
+    description: "WPR area A start page\r This field contains the first page of the WPR area A.\r Note that bit 6 is reserved on STM32WBAxEx devices."
+    bit_offset: 0
+    bit_size: 7
+  - name: WRPA_PEND
+    description: "WPR area A end page\r This field contains the last page of the WPR area A.\r Note that bit 22 is reserved on STM32WBAxEx devices."
+    bit_offset: 16
+    bit_size: 7
+  - name: UNLOCK
+    description: WPR area A unlock
+    bit_offset: 31
+    bit_size: 1
+fieldset/WRPBR:
+  description: WRP area B address register
+  fields:
+  - name: WRPB_PSTRT
+    description: "WRP area B start page\r This field contains the first page of the WRP area B.\r Note that bit 6 is reserved on STM32WBAxEx devices."
+    bit_offset: 0
+    bit_size: 7
+  - name: WRPB_PEND
+    description: "WRP area B end page\r This field contains the last page of the WRP area B.\r Note that bit 22 is reserved on STM32WBAxEx devices."
+    bit_offset: 16
+    bit_size: 7
+  - name: UNLOCK
+    description: WPR area B unlock
+    bit_offset: 31
+    bit_size: 1
+enum/BOR_LEV:
+  bit_size: 3
+  variants:
+  - name: Level0
+    description: BOR level 0 (reset level threshold around 1.7<EFBFBD>V)
+    value: 0
+  - name: Level1
+    description: BOR level 1 (reset level threshold around 2.0<EFBFBD>V)
+    value: 1
+  - name: Level2
+    description: BOR level 2 (reset level threshold around 2.2<EFBFBD>V)
+    value: 2
+  - name: Level3
+    description: BOR level 3 (reset level threshold around 2.5<EFBFBD>V)
+    value: 3
+  - name: Level4
+    description: BOR level 4 (reset level threshold around 2.8<EFBFBD>V)
+    value: 4
+enum/CODE_OP:
+  bit_size: 3
+  variants:
+  - name: B_0x0
+    description: No operation interrupted by previous reset
+    value: 0
+  - name: B_0x1
+    description: Single write operation interrupted
+    value: 1
+  - name: B_0x2
+    description: Burst write operation interrupted
+    value: 2
+  - name: B_0x3
+    description: Page erase operation interrupted
+    value: 3
+  - name: B_0x4
+    description: Reserved
+    value: 4
+  - name: B_0x5
+    description: Mass erase operation interrupted
+    value: 5
+  - name: B_0x6
+    description: Option change operation interrupted
+    value: 6
+  - name: B_0x7
+    description: Reserved
+    value: 7
+enum/RDP:
+  bit_size: 8
+  variants:
+  - name: B_0x55
+    description: Level 0.5 (readout protection not active, only non-secure debug access is possible). Only available when TrustZone is active (TZEN=1)
+    value: 85
+  - name: B_0xAA
+    description: Level 0 (readout protection not active)
+    value: 170
+  - name: B_0xCC
+    description: Level 2 (chip readout protection active)
+    value: 204

data/registers/pwr_wba.yaml

@@ -0,0 +1,537 @@
+block/PWR:
+  description: Power control
+  items:
+  - name: CR1
+    description: control register 1
+    byte_offset: 0
+    fieldset: CR1
+  - name: CR2
+    description: control register 2
+    byte_offset: 4
+    fieldset: CR2
+  - name: CR3
+    description: control register 3
+    byte_offset: 8
+    fieldset: CR3
+  - name: VOSR
+    description: voltage scaling register
+    byte_offset: 12
+    fieldset: VOSR
+  - name: SVMCR
+    description: supply voltage monitoring control register
+    byte_offset: 16
+    fieldset: SVMCR
+  - name: WUCR1
+    description: wakeup control register 1
+    byte_offset: 20
+    fieldset: WUCR1
+  - name: WUCR2
+    description: wakeup control register 2
+    byte_offset: 24
+    fieldset: WUCR2
+  - name: WUCR3
+    description: wakeup control register 3
+    byte_offset: 28
+    fieldset: WUCR3
+  - name: DBPR
+    description: disable Backup domain register
+    byte_offset: 40
+    fieldset: DBPR
+  - name: SECCFGR
+    description: security configuration register
+    byte_offset: 48
+    fieldset: SECCFGR
+  - name: PRIVCFGR
+    description: privilege control register
+    byte_offset: 52
+    fieldset: PRIVCFGR
+  - name: SR
+    description: status register
+    byte_offset: 56
+    fieldset: SR
+  - name: SVMSR
+    description: supply voltage monitoring status register
+    byte_offset: 60
+    fieldset: SVMSR
+  - name: WUSR
+    description: wakeup status register
+    byte_offset: 68
+    fieldset: WUSR
+  - name: WUSCR
+    description: wakeup status clear register
+    byte_offset: 72
+    fieldset: WUSCR
+  - name: IORETENR
+    description: port Standby IO retention enable register
+    array:
+      len: 8
+      stride: 8
+    byte_offset: 80
+    fieldset: IORETENR
+  - name: IORETRA
+    description: port Standby IO retention status register
+    array:
+      len: 8
+      stride: 8
+    byte_offset: 84
+    fieldset: IORETR
+  - name: RADIOSCR
+    description: 2.4 GHz RADIO status and control register
+    byte_offset: 256
+    fieldset: RADIOSCR
+fieldset/CR1:
+  description: control register 1
+  fields:
+  - name: LPMS
+    description: "Low-power mode selection\r These bits select the low-power mode entered when the CPU enters the SleepDeep mode.\r 10x: Standby mode\r others reserved"
+    bit_offset: 0
+    bit_size: 3
+    enum: LPMS
+  - name: R2RSB1
+    description: "SRAM2 retention in Standby mode\r This bit is used to keep the SRAM2 content in Standby retention mode."
+    bit_offset: 5
+    bit_size: 1
+    enum: RRSB
+  - name: ULPMEN
+    description: "BOR0 ultra-low-power mode. \r This bit is used to reduce the consumption by configuring the BOR0 in discontinuous mode for Stop 1 and Standby modes. Discontinuous mode is only available when BOR levels 1 to 4 and PVD are disabled.\r Note: This bit must be set to reach the lowest power consumption in the low-power modes.\r Note: This bit must not be set together with autonomous peripherals using HSI16 as kernel clock.\r Note: When BOR level 1 to 4 or PVD is enabled continuous mode applies independent from ULPMEN."
+    bit_offset: 7
+    bit_size: 1
+  - name: RADIORSB
+    description: "2.4 GHz RADIO SRAMs (RXTXRAM and Sequence RAM) and Sleep clock retention in Standby mode.\r This bit is used to keep the 2.4 GHz RADIO SRAMs content in Standby retention mode and the 2.4 GHz RADIO sleep timer counter operational."
+    bit_offset: 9
+    bit_size: 1
+    enum: RADIORSB
+  - name: R1RSB1
+    description: "SRAM1 retention in Standby mode\r This bit is used to keep the SRAM1 content in Standby retention mode."
+    bit_offset: 12
+    bit_size: 1
+    enum: RRSB
+fieldset/CR2:
+  description: control register 2
+  fields:
+  - name: SRAM1PDS1
+    description: "SRAM1 power-down in Stop modes (Stop 0, 1)\r Note: The SRAM1 retention in Standby mode is controlled by R1RSB1 bit in CR1."
+    bit_offset: 0
+    bit_size: 1
+    enum: SRAMPDS
+  - name: SRAM2PDS1
+    description: "SRAM2 power-down in Stop modes (Stop 0, 1)\r Note: The SRAM2 retention in Standby mode is controlled by R2RSB1 bit in CR1."
+    bit_offset: 4
+    bit_size: 1
+    enum: SRAMPDS
+  - name: ICRAMPDS
+    description: ICACHE SRAM power-down in Stop modes (Stop 0, 1)
+    bit_offset: 8
+    bit_size: 1
+    enum: ICRAMPDS
+  - name: FLASHFWU
+    description: "Flash memory fast wakeup from Stop modes (Stop 0, 1)\r This bit is used to obtain the best trade-off between low-power consumption and wakeup time when exiting the Stop 0 or Stop 1 modes.\r When this bit is set, the Flash memory remains in normal mode in Stop 0 and Stop 1 modes, which offers a faster startup time with higher consumption."
+    bit_offset: 14
+    bit_size: 1
+    enum: FLASHFWU
+fieldset/CR3:
+  description: control register 3
+  fields:
+  - name: FSTEN
+    description: Fast soft start
+    bit_offset: 2
+    bit_size: 1
+fieldset/DBPR:
+  description: disable Backup domain register
+  fields:
+  - name: DBP
+    description: "Disable Backup domain write protection\r In reset state, all registers and SRAM in Backup domain are protected against parasitic write access. This bit must be set to enable the write access to these registers."
+    bit_offset: 0
+    bit_size: 1
+fieldset/IORETENR:
+  description: port A Standby IO retention enable register
+  fields:
+  - name: EN
+    description: "Port A Standby GPIO retention enable\r Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV.\r When set, each bit enables the Standby GPIO retention feature for PAy"
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 16
+      stride: 1
+fieldset/IORETR:
+  description: port A Standby IO retention status register
+  fields:
+  - name: RET
+    description: "Port A Standby GPIO retention active\r Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV."
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 16
+      stride: 1
+fieldset/PRIVCFGR:
+  description: privilege control register
+  fields:
+  - name: SPRIV
+    description: "secure functions privilege configuration\r This bit is set and reset by software.\r It can be written only by a secure privileged access."
+    bit_offset: 0
+    bit_size: 1
+    enum: PRIV
+  - name: NSPRIV
+    description: "non-secure functions privilege configuration\r This bit is set and reset by software.\r It can be written only by privileged access, secure or non-secure."
+    bit_offset: 1
+    bit_size: 1
+    enum: PRIV
+fieldset/RADIOSCR:
+  description: 2.4 GHz RADIO status and control register
+  fields:
+  - name: MODE
+    description: "2.4 GHz RADIO operating mode.\r 1x: 2.4 GHz RADIO active mode"
+    bit_offset: 0
+    bit_size: 2
+    enum: MODE
+  - name: PHYMODE
+    description: 2.4 GHz RADIO PHY operating mode
+    bit_offset: 2
+    bit_size: 1
+  - name: ENCMODE
+    description: 2.4 GHz RADIO encryption function operating mode
+    bit_offset: 3
+    bit_size: 1
+  - name: RFVDDHPA
+    description: "2.4 GHz RADIO VDDHPA control word.\r Bits [3:0] see Table 81: PA output power table format for definition.\r Bit [4] rf_event."
+    bit_offset: 8
+    bit_size: 5
+  - name: REGPARDYVDDRFPA
+    description: "Ready bit for V<sub>DDHPA</sub> voltage level when selecting VDDRFPA input.\r Note: REGPARDYVDDRFPA does not allow to detect correct V<sub>DDHPA</sub> voltage level when request to lower the level."
+    bit_offset: 15
+    bit_size: 1
+    enum: REGPARDYVDDRFPA
+fieldset/SECCFGR:
+  description: security configuration register
+  fields:
+  - name: WUP1SEC
+    description: WUP1 secure protection
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 8
+      stride: 1
+    enum: SEC
+  - name: LPMSEC
+    description: Low-power modes secure protection
+    bit_offset: 12
+    bit_size: 1
+    enum: SEC
+  - name: VDMSEC
+    description: Voltage detection secure protection
+    bit_offset: 13
+    bit_size: 1
+    enum: SEC
+  - name: VBSEC
+    description: Backup domain secure protection
+    bit_offset: 14
+    bit_size: 1
+    enum: SEC
+fieldset/SR:
+  description: status register
+  fields:
+  - name: CSSF
+    description: "Clear Stop and Standby flags\r Access can be secured by LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.\r Writing 1 to this bit clears the STOPF and SBF flags."
+    bit_offset: 0
+    bit_size: 1
+  - name: STOPF
+    description: "Stop flag\r This bit is set by hardware when the device enters a Stop or Standby mode at the same time as the sysclk has been set by hardware to select HSI16. It’s cleared by software by writing 1 to the CSSF bit and by hardware when SBF is set."
+    bit_offset: 1
+    bit_size: 1
+  - name: SBF
+    description: "Standby flag\r This bit is set by hardware when the device enters the Standby mode and the CPU restart from its reset vector. It’s cleared by writing 1 to the CSSF bit, or by a power-on reset. It is not cleared by the system reset."
+    bit_offset: 2
+    bit_size: 1
+fieldset/SVMCR:
+  description: supply voltage monitoring control register
+  fields:
+  - name: PVDE
+    description: Programmable voltage detector enable
+    bit_offset: 4
+    bit_size: 1
+  - name: PVDLS
+    description: "Programmable voltage detector level selection\r These bits select the voltage threshold detected by the programmable voltage detector:"
+    bit_offset: 5
+    bit_size: 3
+    enum: PVDLS
+fieldset/SVMSR:
+  description: supply voltage monitoring status register
+  fields:
+  - name: PVDO
+    description: Programmable voltage detector output
+    bit_offset: 4
+    bit_size: 1
+    enum: PVDO
+  - name: ACTVOSRDY
+    description: Voltage level ready for currently used VOS
+    bit_offset: 15
+    bit_size: 1
+  - name: ACTVOS
+    description: "VOS currently applied to V<sub>CORE</sub>\r This field provides the last VOS value."
+    bit_offset: 16
+    bit_size: 1
+    enum: ACTVOS
+fieldset/VOSR:
+  description: voltage scaling register
+  fields:
+  - name: VOSRDY
+    description: "Ready bit for V<sub>CORE</sub> voltage scaling output selection\r Set and cleared by hardware. When decreasing the voltage scaling range, VOSRDY must be one before increasing the SYSCLK frequency."
+    bit_offset: 15
+    bit_size: 1
+  - name: VOS
+    description: "Voltage scaling range selection\r Set a and cleared by software.\r Cleared by hardware when entering Stop 1 mode.\r Access can be secured by RCC SYSCLKSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV."
+    bit_offset: 16
+    bit_size: 1
+    enum: VOS
+fieldset/WUCR1:
+  description: wakeup control register 1
+  fields:
+  - name: WUPEN
+    description: "Wakeup and interrupt pin WKUP1 enable\r Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV."
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 8
+      stride: 1
+fieldset/WUCR2:
+  description: wakeup control register 2
+  fields:
+  - name: WUPP
+    description: "Wakeup pin WKUP1 polarity.\r This bit must be configured when WUPEN1 = 0.\r Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV."
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 8
+      stride: 1
+    enum: WUPP
+fieldset/WUCR3:
+  description: wakeup control register 3
+  fields:
+  - name: WUSEL1
+    description: "Wakeup and interrupt pin WKUP1 selection\r This field must be configured when WUPEN1 = 0.\r Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV."
+    bit_offset: 0
+    bit_size: 2
+    enum: WUSEL
+  - name: WUSEL2
+    description: "Wakeup and interrupt pin WKUP2 selection\r This field must be configured when WUPEN2 = 0.\r Access can be secured by WUP2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV."
+    bit_offset: 2
+    bit_size: 2
+    enum: WUSEL
+  - name: WUSEL3
+    description: "Wakeup and interrupt pin WKUP3 selection\r This field must be configured when WUPEN3 = 0.\r Access can be secured by WUP3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV."
+    bit_offset: 4
+    bit_size: 2
+    enum: WUSEL
+  - name: WUSEL4
+    description: "Wakeup and interrupt pin WKUP4 selection\r This field must be configured when WUPEN4 = 0.\r Access can be secured by WUP4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV."
+    bit_offset: 6
+    bit_size: 2
+    enum: WUSEL
+  - name: WUSEL5
+    description: "Wakeup and interrupt pin WKUP5 selection\r This field must be configured when WUPEN5 = 0.\r Access can be secured by WUP5SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV."
+    bit_offset: 8
+    bit_size: 2
+    enum: WUSEL
+  - name: WUSEL6
+    description: "Wakeup and interrupt pin WKUP6 selection\r This field must be configured when WUPEN6 = 0.\r Access can be secured by WUP6SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV."
+    bit_offset: 10
+    bit_size: 2
+    enum: WUSEL
+  - name: WUSEL7
+    description: "Wakeup and interrupt pin WKUP7 selection\r This field must be configured when WUPEN7 = 0.\r Access can be secured by WUP7SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV."
+    bit_offset: 12
+    bit_size: 2
+    enum: WUSEL
+  - name: WUSEL8
+    description: "Wakeup and interrupt pin WKUP8 selection\r This field must be configured when WUPEN8 = 0.\r Access can be secured by WUP8SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV."
+    bit_offset: 14
+    bit_size: 2
+    enum: WUSEL
+fieldset/WUSCR:
+  description: wakeup status clear register
+  fields:
+  - name: CWUF
+    description: "Clear wakeup flag 1\r Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.\r Writing 1 to this bit clears the WUF1 flag in WUSR."
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 8
+      stride: 1
+fieldset/WUSR:
+  description: wakeup status register
+  fields:
+  - name: WUF
+    description: "Wakeup and interrupt pending flag 1\r This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by writing 1 in the CWUF1 bit of WUSCR or by hardware when WUPEN1 = 0."
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 8
+      stride: 1
+enum/ACTVOS:
+  bit_size: 1
+  variants:
+  - name: Range2
+    description: Range 2 (lowest power)
+    value: 0
+  - name: Range1
+    description: Range 1 (highest frequency)
+    value: 1
+enum/FLASHFWU:
+  bit_size: 1
+  variants:
+  - name: LowPower
+    description: Flash memory enters low-power mode in Stop 0 and Stop 1 modes (lower-power consumption).
+    value: 0
+  - name: Normal
+    description: Flash memory remains in normal mode in Stop 0 and Stop 1 modes (faster wakeup time).
+    value: 1
+enum/ICRAMPDS:
+  bit_size: 1
+  variants:
+  - name: Retained
+    description: ICACHE SRAM content retained in Stop modes
+    value: 0
+  - name: NotRetained
+    description: ICACHE SRAM content lost in Stop modes
+    value: 1
+enum/LPMS:
+  bit_size: 3
+  variants:
+  - name: Stop0
+    description: Stop 0 mode
+    value: 0
+  - name: Stop1
+    description: Stop 1 mode
+    value: 1
+enum/MODE:
+  bit_size: 2
+  variants:
+  - name: DeepSleep
+    description: 2.4 GHz RADIO deep sleep mode
+    value: 0
+  - name: Sleep
+    description: 2.4 GHz RADIO sleep mode
+    value: 1
+enum/PRIV:
+  bit_size: 1
+  variants:
+  - name: Unprivileged
+    description: Read and write to non-secure functions can be done by privileged or unprivileged access.
+    value: 0
+  - name: Privileged
+    description: Read and write to non-secure functions can be done by privileged access only.
+    value: 1
+enum/PVDLS:
+  bit_size: 3
+  variants:
+  - name: v20
+    description: VPVD0 around 2.0 V
+    value: 0
+  - name: v22
+    description: VPVD1 around 2.2 V
+    value: 1
+  - name: v24
+    description: VPVD2 around 2.4 V
+    value: 2
+  - name: v25
+    description: VPVD3 around 2.5 V
+    value: 3
+  - name: v26
+    description: VPVD4 around 2.6 V
+    value: 4
+  - name: v28
+    description: VPVD5 around 2.8 V
+    value: 5
+  - name: v29
+    description: VPVD6 around 2.9 V
+    value: 6
+  - name: pvd_in
+    description: External input analog voltage PVD_IN (compared internally to VREFINT)
+    value: 7
+enum/PVDO:
+  bit_size: 1
+  variants:
+  - name: AboveOrEqual
+    description: VDD is equal or above the PVD threshold selected by PVDLS[2:0].
+    value: 0
+  - name: Below
+    description: VDD is below the PVD threshold selected by PVDLS[2:0].
+    value: 1
+enum/RADIORSB:
+  bit_size: 1
+  variants:
+  - name: NotRetained
+    description: 2.4 GHz RADIO SRAMs and sleep timer content not retained in Standby mode
+    value: 0
+  - name: Retained
+    description: 2.4 GHz RADIO SRAMs and sleep timer content retained in Standby mode
+    value: 1
+enum/REGPARDYVDDRFPA:
+  bit_size: 1
+  variants:
+  - name: NotReady
+    description: Not ready, V<sub>DDHPA</sub> voltage level < REGPAVOS selected supply level
+    value: 0
+  - name: Ready
+    description: Ready, V<sub>DDHPA</sub> voltage level ≥ REGPAVOS selected supply level
+    value: 1
+enum/RRSB:
+  bit_size: 1
+  variants:
+  - name: B_0x0
+    description: SRAM2 content not retained in Standby mode
+    value: 0
+  - name: B_0x1
+    description: SRAM2 content retained in Standby mode
+    value: 1
+enum/SEC:
+  bit_size: 1
+  variants:
+  - name: NotSecure
+    description: SVMCR and CR3 can be read and written with secure or non-secure access.
+    value: 0
+  - name: Secure
+    description: SVMCR and CR3 can be read and written only with secure access.
+    value: 1
+enum/SRAMPDS:
+  bit_size: 1
+  variants:
+  - name: PoweredOn
+    description: SRAM1 content retained in Stop modes
+    value: 0
+  - name: PoweredOff
+    description: SRAM1 content lost in Stop modes
+    value: 1
+enum/VOS:
+  bit_size: 1
+  variants:
+  - name: Range2
+    description: Range 2 (lowest power)
+    value: 0
+  - name: Range1
+    description: Range 1 (highest frequency).
+    value: 1
+enum/WUPP:
+  bit_size: 1
+  variants:
+  - name: High
+    description: Detection on high level (rising edge)
+    value: 0
+  - name: Low
+    description: Detection on low level (falling edge)
+    value: 1
+enum/WUSEL:
+  bit_size: 2
+  variants:
+  - name: B_0x0
+    description: reserved
+    value: 0
+  - name: B_0x1
+    description: WKUP3_1
+    value: 1
+  - name: B_0x2
+    description: WKUP3_2
+    value: 2
+  - name: B_0x3
+    description: reserved
+    value: 3

data/registers/syscfg_wba.yaml

@@ -0,0 +1,196 @@
+block/SYSCFG:
+  description: System configuration controller
+  items:
+  - name: SECCFGR
+    description: secure configuration register
+    byte_offset: 0
+    fieldset: SECCFGR
+  - name: CFGR1
+    description: configuration register 1
+    byte_offset: 4
+    fieldset: CFGR1
+  - name: FPUIMR
+    description: FPU interrupt mask register
+    byte_offset: 8
+    fieldset: FPUIMR
+  - name: CNSLCKR
+    description: CPU non-secure lock register
+    byte_offset: 12
+    fieldset: CNSLCKR
+  - name: CSLOCKR
+    description: CPU secure lock register
+    byte_offset: 16
+    fieldset: CSLOCKR
+  - name: CFGR2
+    description: configuration register 2
+    byte_offset: 20
+    fieldset: CFGR2
+  - name: MESR
+    description: memory erase status register
+    byte_offset: 24
+    fieldset: MESR
+  - name: CCCSR
+    description: compensation cell control/status register
+    byte_offset: 28
+    fieldset: CCCSR
+  - name: CCVR
+    description: compensation cell value register
+    byte_offset: 32
+    fieldset: CCVR
+  - name: CCCR
+    description: compensation cell code register
+    byte_offset: 36
+    fieldset: CCCR
+  - name: RSSCMDR
+    description: RSS command register
+    byte_offset: 44
+    fieldset: RSSCMDR
+fieldset/CCCR:
+  description: compensation cell code register
+  fields:
+  - name: NCC1
+    description: "NMOS compensation code of the I/Os supplied by V<sub>DD</sub>\r These bits are written by software to define an I/Os compensation cell code for NMOS transistors. This code is applied to the I/Os compensation cell when the CS1 bit of the CCCSR is set."
+    bit_offset: 0
+    bit_size: 4
+  - name: PCC1
+    description: "PMOS compensation code of the I/Os supplied by V<sub>DD</sub>\r These bits are written by software to define an I/Os compensation cell code for PMOS transistors. This code is applied to the I/Os compensation cell when the CS1 bit of the CCCSR is set."
+    bit_offset: 4
+    bit_size: 4
+fieldset/CCCSR:
+  description: compensation cell control/status register
+  fields:
+  - name: EN1
+    description: "VDD I/Os compensation cell enable\r This bit enables the compensation cell of the I/Os supplied by V<sub>DD</sub>."
+    bit_offset: 0
+    bit_size: 1
+  - name: CS1
+    description: "VDD I/Os code selection\r This bit selects the code to be applied for the compensation cell of the I/Os supplied by V<sub>DD</sub>."
+    bit_offset: 1
+    bit_size: 1
+  - name: RDY1
+    description: "VDD I/Os compensation cell ready flag\r This bit provides the compensation cell status of the I/Os supplied by V<sub>DD</sub>.\r Note: The HSI16 clock is required for the compensation cell to work properly. The compensation cell ready bit (RDY1) is not set if the HSI16 clock is not enabled (HSION)."
+    bit_offset: 8
+    bit_size: 1
+fieldset/CCVR:
+  description: compensation cell value register
+  fields:
+  - name: NCV1
+    description: "NMOS compensation value of the I/Os supplied by V<sub>DD</sub>\r This value is provided by the cell and can be used by the CPU to compute an I/Os compensation cell code for NMOS transistors. This code is applied to the I/Os compensation cell when the CS1 bit of the CCCSR is reset."
+    bit_offset: 0
+    bit_size: 4
+  - name: PCV1
+    description: "PMOS compensation value of the I/Os supplied by V<sub>DD</sub>\r This value is provided by the cell and can be used by the CPU to compute an I/Os compensation cell code for PMOS transistors. This code is applied to the I/Os compensation cell when the CS1 bit of the CCCSR is reset."
+    bit_offset: 4
+    bit_size: 4
+fieldset/CFGR1:
+  description: configuration register 1
+  fields:
+  - name: BOOSTEN
+    description: "I/O analog switch voltage booster enable\r Access can be protected by GTZC_TZSC ADC4SEC.\r Note: Refer to Table<6C>121 for setting."
+    bit_offset: 8
+    bit_size: 1
+  - name: ANASWVDD
+    description: "GPIO analog switch control voltage selection\r Access can be protected by GTZC_TZSC ADC4SEC.\r Note: Refer to Table<6C>121 for setting."
+    bit_offset: 9
+    bit_size: 1
+  - name: PA6_FMP
+    description: "Fast-mode Plus drive capability activation on PA6\r This bit can be read and written only with secure access if PA6 is secure in GPIOA. This bit enables the Fast-mode Plus drive mode for PA6 when PA6 is not used by I2C peripheral. This can be used to dive a LED for instance.\r Access can be protected by GPIOA SEC6."
+    bit_offset: 16
+    bit_size: 1
+  - name: PA7_FMP
+    description: "Fast-mode Plus drive capability activation on PA7\r This bit can be read and written only with secure access if PA7 is secure in GPIOA. This bit enables the Fast-mode Plus drive mode for PA7 when PA7 is not used by I2C peripheral. This can be used to dive a LED for instance.\r Access can be protected by GPIOA SEC7."
+    bit_offset: 17
+    bit_size: 1
+  - name: PA15_FMP
+    description: "Fast-mode Plus drive capability activation on PA15\r This bit can be read and written only with secure access if PA15 is secure in GPIOA. This bit enables the Fast-mode Plus drive mode for PA15 when PA15 is not used by I2C peripheral. This can be used to dive a LED for instance.\r Access can be protected by GPIOA SEC15."
+    bit_offset: 18
+    bit_size: 1
+  - name: PB3_FMP
+    description: "Fast-mode Plus drive capability activation on PB3\r This bit can be read and written only with secure access if PB3 is secure in GPIOB. This bit enables the Fast-mode Plus drive mode for PB3 when PB3 is not used by I2C peripheral. This can be used to dive a LED for instance.\r Access can be protected by GPIOB SEC3."
+    bit_offset: 19
+    bit_size: 1
+fieldset/CFGR2:
+  description: configuration register 2
+  fields:
+  - name: CLL
+    description: "Cortex-M33 LOCKUP (hardfault) output enable\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the connection of Cortex-M33 LOCKUP (hardfault) output to TIM1/16/17 break input."
+    bit_offset: 0
+    bit_size: 1
+  - name: SPL
+    description: "SRAM2 parity lock bit\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the SRAM2 parity error signal connection to TIM1/16/17 break inputs."
+    bit_offset: 1
+    bit_size: 1
+  - name: PVDL
+    description: "PVD lock enable bit\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection to TIM1/16/17 break input, as well as the PVDE and PVDLS[2:0] in the PWR register."
+    bit_offset: 2
+    bit_size: 1
+  - name: ECCL
+    description: "ECC lock\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the Flash ECC double error signal connection to TIM1/16/17 break input."
+    bit_offset: 3
+    bit_size: 1
+fieldset/CNSLCKR:
+  description: CPU non-secure lock register
+  fields:
+  - name: LOCKNSVTOR
+    description: "VTOR_NS register lock\r This bit is set by software and cleared only by a system reset."
+    bit_offset: 0
+    bit_size: 1
+  - name: LOCKNSMPU
+    description: "Non-secure MPU registers lock\r This bit is set by software and cleared only by a system reset. When set, this bit disables write access to non-secure MPU_CTRL_NS, MPU_RNR_NS and MPU_RBAR_NS registers."
+    bit_offset: 1
+    bit_size: 1
+fieldset/CSLOCKR:
+  description: CPU secure lock register
+  fields:
+  - name: LOCKSVTAIRCR
+    description: "VTOR_S register and AIRCR register bits lock\r This bit is set by software and cleared only by a system reset. When set, it disables write access to VTOR_S register, PRIS and BFHFNMINS bits in the AIRCR register."
+    bit_offset: 0
+    bit_size: 1
+  - name: LOCKSMPU
+    description: "Secure MPU registers lock\r This bit is set by software and cleared only by a system reset. When set, it disables write access to secure MPU_CTRL, MPU_RNR and MPU_RBAR registers."
+    bit_offset: 1
+    bit_size: 1
+  - name: LOCKSAU
+    description: "SAU registers lock\r This bit is set by software and cleared only by a system reset. When set, it disables write access to SAU_CTRL, SAU_RNR, SAU_RBAR and SAU_RLAR registers."
+    bit_offset: 2
+    bit_size: 1
+fieldset/FPUIMR:
+  description: FPU interrupt mask register
+  fields:
+  - name: FPU_IE
+    description: "Floating point unit interrupts enable bits\r FPU_IE[5]: Inexact interrupt enable (interrupt disable at reset)\r FPU_IE[4]: Input abnormal interrupt enable\r FPU_IE[3]: Overflow interrupt enable\r FPU_IE[2]: Underflow interrupt enable\r FPU_IE[1]: Divide-by-zero interrupt enable\r FPU_IE[0]: Invalid operation Interrupt enable"
+    bit_offset: 0
+    bit_size: 6
+fieldset/MESR:
+  description: memory erase status register
+  fields:
+  - name: MCLR
+    description: "Device memories erase status\r This bit is set by hardware when SRAM2, ICACHE, PKA SRAM erase is completed after power-on reset or tamper detection (refer to Section<6F>75: Tamper and backup registers (TAMP) for more details). This bit is not reset by system reset and is cleared by software by writing 1 to it."
+    bit_offset: 0
+    bit_size: 1
+  - name: IPMEE
+    description: "ICACHE and PKA SRAM erase status\r This bit is set by hardware when ICACHE and PKA SRAM erase is completed after potential tamper detection (refer to Section<6F>75: Tamper and backup registers (TAMP) for more details). This bit is cleared by software by writing 1 to it."
+    bit_offset: 16
+    bit_size: 1
+fieldset/RSSCMDR:
+  description: RSS command register
+  fields:
+  - name: RSSCMD
+    description: "RSS commands\r This field defines a command to be executed by the RSS."
+    bit_offset: 0
+    bit_size: 16
+fieldset/SECCFGR:
+  description: secure configuration register
+  fields:
+  - name: SYSCFGSEC
+    description: clock control, memory erase status and compensation cell registers security
+    bit_offset: 0
+    bit_size: 1
+  - name: CLASSBSEC
+    description: Class B security
+    bit_offset: 1
+    bit_size: 1
+  - name: FPUSEC
+    description: FPU security
+    bit_offset: 3
+    bit_size: 1

stm32-data-gen/src/chips.rs

@@ -216,6 +216,7 @@ impl PeriMatcher {
             ("STM32G4.*:SYSCFG:.*", ("syscfg", "g4", "SYSCFG")),
             ("STM32H7.*:SYSCFG:.*", ("syscfg", "h7", "SYSCFG")),
             ("STM32U5.*:SYSCFG:.*", ("syscfg", "u5", "SYSCFG")),
+            ("STM32WBA.*:SYSCFG:.*", ("syscfg", "wba", "SYSCFG")),
             ("STM32WB.*:SYSCFG:.*", ("syscfg", "wb", "SYSCFG")),
             ("STM32WL5.*:SYSCFG:.*", ("syscfg", "wl5", "SYSCFG")),
             ("STM32WL5.*:ADC:.*", ("adc", "g0", "ADC")),
@@ -245,6 +246,7 @@ impl PeriMatcher {
             ("STM32L0.*:RTC:rtc2_.*", ("rtc", "v2l0", "RTC")),
             ("STM32L1.*:RTC:rtc2_.*", ("rtc", "v2l1", "RTC")),
             ("STM32L4.*:RTC:rtc2_.*", ("rtc", "v2l4", "RTC")),
+            ("STM32WBA.*:RTC:rtc2_.*", ("rtc", "v3u5", "RTC")),
             ("STM32WB.*:RTC:rtc2_.*", ("rtc", "v2wb", "RTC")),
             ("STM32U5.*:RTC:rtc2_.*", ("rtc", "v3u5", "RTC")), // Cube says v2, but it's v3 with security stuff
             (".*:RTC:rtc3_v1_0", ("rtc", "v3", "RTC")),
@@ -297,12 +299,14 @@ impl PeriMatcher {
             ("STM32U5.*:RCC:.*", ("rcc", "u5", "RCC")),
             ("STM32H50.*:RCC:.*", ("rcc", "h50", "RCC")),
             ("STM32H5.*:RCC:.*", ("rcc", "h5", "RCC")),
+            ("STM32WBA.*:RCC:.*", ("rcc", "wba", "RCC")),
             ("STM32WB.*:RCC:.*", ("rcc", "wb", "RCC")),
             ("STM32WL5.*:RCC:.*", ("rcc", "wl5", "RCC")),
             ("STM32WLE.*:RCC:.*", ("rcc", "wle", "RCC")),
             ("STM32F1.*:SPI[1234]:.*", ("spi", "f1", "SPI")),
             ("STM32F3.*:SPI[1234]:.*", ("spi", "v2", "SPI")),
             ("STM32F1.*:AFIO:.*", ("afio", "f1", "AFIO")),
+            ("STM32WBA.*:EXTI:.*", ("exti", "l5", "EXTI")),
             ("STM32L5.*:EXTI:.*", ("exti", "l5", "EXTI")),
             ("STM32C0.*:EXTI:.*", ("exti", "c0", "EXTI")),
             ("STM32G0.*:EXTI:.*", ("exti", "g0", "EXTI")),
@@ -336,6 +340,7 @@ impl PeriMatcher {
             ("STM32L5.*:PWR:.*", ("pwr", "l5", "PWR")),
             ("STM32U5.*:PWR:.*", ("pwr", "u5", "PWR")),
             ("STM32WL.*:PWR:.*", ("pwr", "wl5", "PWR")),
+            ("STM32WBA.*:PWR:.*", ("pwr", "wba", "PWR")),
             ("STM32WB.*:PWR:.*", ("pwr", "wb55", "PWR")),
             ("STM32H50.*:PWR:.*", ("pwr", "h50", "PWR")),
             ("STM32H5.*:PWR:.*", ("pwr", "h5", "PWR")),
@@ -352,6 +357,7 @@ impl PeriMatcher {
             ("STM32L4.*:FLASH:.*", ("flash", "l4", "FLASH")),
             ("STM32L5.*:FLASH:.*", ("flash", "l5", "FLASH")),
             ("STM32U5.*:FLASH:.*", ("flash", "u5", "FLASH")),
+            ("STM32WBA.*:FLASH:.*", ("flash", "wba", "FLASH")),
             ("STM32WB.*:FLASH:.*", ("flash", "wb", "FLASH")),
             ("STM32WL.*:FLASH:.*", ("flash", "wl", "FLASH")),
             ("STM32C0.*:FLASH:.*", ("flash", "c0", "FLASH")),
@@ -363,6 +369,7 @@ impl PeriMatcher {
             ("STM32F[24].*:ETH:.*", ("eth", "v1b", "ETH")),
             ("STM32F7.*:ETH:.*", ("eth", "v1c", "ETH")),
             (".*ETH:ethermac110_v3_0", ("eth", "v2", "ETH")),
+            (".*ETH:ethermac110_v3_0_1", ("eth", "v2", "ETH")),
             ("STM32F4[23][79].*:FMC:.*", ("fmc", "v1x3", "FMC")),
             ("STM32F446.*:FMC:.*", ("fmc", "v2x1", "FMC")),
             ("STM32F469.*:FMC:.*", ("fmc", "v2x1", "FMC")),
@@ -405,6 +412,7 @@ impl PeriMatcher {
             ("STM32L1.*:DBGMCU:.*", ("dbgmcu", "l1", "DBGMCU")),
             ("STM32L4.*:DBGMCU:.*", ("dbgmcu", "l4", "DBGMCU")),
             ("STM32U5.*:DBGMCU:.*", ("dbgmcu", "u5", "DBGMCU")),
+            ("STM32WBA.*:DBGMCU:.*", ("dbgmcu", "wba", "DBGMCU")),
             ("STM32WB.*:DBGMCU:.*", ("dbgmcu", "wb", "DBGMCU")),
             ("STM32WL.*:DBGMCU:.*", ("dbgmcu", "wl", "DBGMCU")),
             ("STM32F1.*:GPIO.*", ("gpio", "v1", "GPIO")),
@@ -546,11 +554,11 @@ pub fn parse_groups() -> Result<(HashMap<String, Chip>, Vec<ChipGroup>), anyhow:
 static NOPELIST: &[&str] = &[
     // Not supported, not planned unless someone wants to do it.
     "STM32MP",
-    // Not supported yet, planned.
-    "STM32WBA",
     // Does not exist in ST website. No datasheet, no RM.
     "STM32GBK",
     "STM32L485",
+    "STM32U5F",
+    "STM32U5G",
     // STM32WxM modules. These are based on a chip that's supported on its own,
     // not sure why we want a separate target for it.
     "STM32WL5M",
@@ -765,7 +773,7 @@ fn process_core(
         if ["L5", "U5"].contains(&&chip_name[5..7]) {
             want_nvic_name = "NVIC2"
         }
-        if ["H56", "H57"].contains(&&chip_name[5..8]) {
+        if ["H56", "H57", "WBA"].contains(&&chip_name[5..8]) {
             want_nvic_name = "NVIC2"
         }
 

stm32-data-gen/src/dma.rs

@@ -298,6 +298,7 @@ impl DmaChannels {
             ("H5_GPDMA.yaml", "GPDMA1", "STM32H5_dma3_Cube", 8, 2),
             ("H5_GPDMA.yaml", "GPDMA2", "Instance2_STM32H5_dma3_Cube", 8, 2),
             ("U5_GPDMA1.yaml", "GPDMA1", "STM32U5_dma3_Cube", 16, 4),
+            ("WBA_GPDMA1.yaml", "GPDMA1", "STM32WBA_dma3_Cube", 8, 0),
         ] {
             let mut chip_dma = ChipDma {
                 peripherals: HashMap::new(),