From 43c1e7b3bec846ce98c9339750018ac2591cb819 Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Sat, 16 Sep 2023 02:06:26 +0200 Subject: [PATCH] Add STM32WBA support. --- data/dmamux/WBA_GPDMA1.yaml | 50 + data/registers/dbgmcu_wba.yaml | 339 +++++++ data/registers/flash_wba.yaml | 643 +++++++++++++ data/registers/pwr_wba.yaml | 537 +++++++++++ data/registers/rcc_wba.yaml | 1572 ++++++++++++++++++++++++++++++++ data/registers/syscfg_wba.yaml | 196 ++++ stm32-data-gen/src/chips.rs | 14 +- stm32-data-gen/src/dma.rs | 1 + 8 files changed, 3349 insertions(+), 3 deletions(-) create mode 100644 data/dmamux/WBA_GPDMA1.yaml create mode 100644 data/registers/dbgmcu_wba.yaml create mode 100644 data/registers/flash_wba.yaml create mode 100644 data/registers/pwr_wba.yaml create mode 100644 data/registers/rcc_wba.yaml create mode 100644 data/registers/syscfg_wba.yaml diff --git a/data/dmamux/WBA_GPDMA1.yaml b/data/dmamux/WBA_GPDMA1.yaml new file mode 100644 index 0000000..f01f151 --- /dev/null +++ b/data/dmamux/WBA_GPDMA1.yaml @@ -0,0 +1,50 @@ +ADC4: 0 +SPI1_RX: 1 +SPI1_TX: 2 +SPI3_RX: 3 +SPI3_TX: 4 +I2C1_RX: 5 +I2C1_TX: 6 +I2C1_EVC: 7 +I2C3_RX: 8 +I2C3_TX: 9 +I2C3_EVC: 10 +USART1_RX: 11 +USART1_TX: 12 +USART2_RX: 13 +USART2_TX: 14 +LPUART1_RX: 15 +LPUART1_TX: 16 +TIM1_CC1: 19 +TIM1_CC2: 20 +TIM1_CC3: 21 +TIM1_CC4: 22 +TIM1_UPD: 23 +TIM1_TRG: 24 +TIM1_COM: 25 +TIM2_CC1: 26 +TIM2_CC2: 27 +TIM2_CC3: 28 +TIM2_CC4: 29 +TIM2_UPD: 30 +TIM3_CC1: 31 +TIM3_CC2: 32 +TIM3_CC3: 33 +TIM3_CC4: 34 +TIM3_UPD: 35 +TIM3_TRG: 36 +TIM16_CC1: 37 +TIM16_UPD: 38 +TIM17_CC1: 39 +TIM17_UPD: 40 +AES_IN: 41 +AES_OUT: 42 +HASH_IN: 43 +SAES_IN: 44 +SAES_OUT: 45 +LPTIM1_IC1: 46 +LPTIM1_IC2: 47 +LPTIM1_UE: 48 +LPTIM2_IC1: 49 +LPTIM2_IC2: 50 +LPTIM2_UE: 51 \ No newline at end of file diff --git a/data/registers/dbgmcu_wba.yaml b/data/registers/dbgmcu_wba.yaml new file mode 100644 index 0000000..264b506 --- /dev/null +++ b/data/registers/dbgmcu_wba.yaml @@ -0,0 +1,339 @@ +block/DBGMCU: + description: Microcontroller debug unit + items: + - name: IDCODE + description: identity code register + byte_offset: 0 + fieldset: IDCODE + - name: CR + description: status and configuration register + byte_offset: 4 + fieldset: CR + - name: APB1LFZR + description: APB1L peripheral freeze register + byte_offset: 8 + fieldset: APB1LFZR + - name: APB1HFZR + description: APB1H peripheral freeze register + byte_offset: 12 + fieldset: APB1HFZR + - name: APB2FZR + description: APB2 peripheral freeze register + byte_offset: 16 + fieldset: APB2FZR + - name: APB7FZR + description: APB7 peripheral freeze register + byte_offset: 36 + fieldset: APB7FZR + - name: AHB1FZR + description: AHB1 peripheral freeze register + byte_offset: 40 + fieldset: AHB1FZR + - name: SR + description: status register + byte_offset: 252 + fieldset: SR + - name: DBG_AUTH_HOST + description: debug host authentication register + byte_offset: 256 + fieldset: DBG_AUTH_HOST + - name: DBG_AUTH_DEVICE + description: debug device authentication register + byte_offset: 260 + fieldset: DBG_AUTH_DEVICE + - name: PNCR + description: part number codification register + byte_offset: 2012 + fieldset: PNCR + - name: PIDR4 + description: CoreSight peripheral identity register 4 + byte_offset: 4048 + fieldset: PIDR4 + - name: PIDR0 + description: CoreSight peripheral identity register 0 + byte_offset: 4064 + fieldset: PIDR0 + - name: PIDR1 + description: CoreSight peripheral identity register 1 + byte_offset: 4068 + fieldset: PIDR1 + - name: PIDR2 + description: CoreSight peripheral identity register 2 + byte_offset: 4072 + fieldset: PIDR2 + - name: PIDR3 + description: CoreSight peripheral identity register 3 + byte_offset: 4076 + fieldset: PIDR3 + - name: CIDR0 + description: CoreSight component identity register 0 + byte_offset: 4080 + fieldset: CIDR0 + - name: CIDR1 + description: CoreSight peripheral identity register 1 + byte_offset: 4084 + fieldset: CIDR1 + - name: CIDR2 + description: CoreSight component identity register 2 + byte_offset: 4088 + fieldset: CIDR2 + - name: CIDR3 + description: CoreSight component identity register 3 + byte_offset: 4092 + fieldset: CIDR3 +fieldset/AHB1FZR: + description: AHB1 peripheral freeze register + fields: + - name: DBG_GPDMA1_CH0_STOP + description: "GPDMA 1 channel 0 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC0." + bit_offset: 0 + bit_size: 1 + - name: DBG_GPDMA1_CH1_STOP + description: "GPDMA 1 channel 1 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC1." + bit_offset: 1 + bit_size: 1 + - name: DBG_GPDMA1_CH2_STOP + description: "GPDMA 1 channel 2 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC2." + bit_offset: 2 + bit_size: 1 + - name: DBG_GPDMA1_CH3_STOP + description: "GPDMA 1 channel 3 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC3." + bit_offset: 3 + bit_size: 1 + - name: DBG_GPDMA1_CH4_STOP + description: "GPDMA 1 channel 4 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC4." + bit_offset: 4 + bit_size: 1 + - name: DBG_GPDMA1_CH5_STOP + description: "GPDMA 1 channel 5 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC5." + bit_offset: 5 + bit_size: 1 + - name: DBG_GPDMA1_CH6_STOP + description: "GPDMA 1 channel 6 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC6." + bit_offset: 6 + bit_size: 1 + - name: DBG_GPDMA1_CH7_STOP + description: "GPDMA 1 channel 7 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC7." + bit_offset: 7 + bit_size: 1 +fieldset/APB1HFZR: + description: APB1H peripheral freeze register + fields: + - name: DBG_LPTIM2_STOP + description: "LPTIM2 stop in CPU debug\r Write access can be protected by GTZC_TZSC.LPTIM2SEC." + bit_offset: 5 + bit_size: 1 +fieldset/APB1LFZR: + description: APB1L peripheral freeze register + fields: + - name: DBG_TIM2_STOP + description: "TIM2 stop in CPU debug\r Write access can be protected by GTZC_TZSC.TIM2SEC." + bit_offset: 0 + bit_size: 1 + - name: DBG_TIM3_STOP + description: "TIM3 stop in CPU debug\r Write access can be protected by GTZC_TZSC.TIM3SEC." + bit_offset: 1 + bit_size: 1 + - name: DBG_WWDG_STOP + description: "WWDG stop in CPU debug\r Write access can be protected by GTZC_TZSC.WWDGSEC" + bit_offset: 11 + bit_size: 1 + - name: DBG_IWDG_STOP + description: "IWDG stop in CPU debug\r Write access can be protected by GTZC_TZSC.IWDGSEC." + bit_offset: 12 + bit_size: 1 + - name: DBG_I2C1_STOP + description: "I2C1 SMBUS timeout stop in CPU debug\r Write access can be protected by GTZC_TZSC.I2C1SEC." + bit_offset: 21 + bit_size: 1 +fieldset/APB2FZR: + description: APB2 peripheral freeze register + fields: + - name: DBG_TIM1_STOP + description: "TIM1 stop in CPU debug\r Write access can be protected by GTZC_TZSC.TIM1SEC." + bit_offset: 11 + bit_size: 1 + - name: DBG_TIM16_STOP + description: "TIM16 stop in CPU debug\r Write access can be protected by GTZC_TZSC.TIM16SEC." + bit_offset: 17 + bit_size: 1 + - name: DBG_TIM17_STOP + description: "TIM17 stop in CPU debug\r Write access can be protected by GTZC_TZSC.TIM17SEC." + bit_offset: 18 + bit_size: 1 +fieldset/APB7FZR: + description: APB7 peripheral freeze register + fields: + - name: DBG_I2C3_STOP + description: "I2C3 stop in CPU debug\r Access can be protected by GTZC_TZSC.I2C3SEC." + bit_offset: 10 + bit_size: 1 + - name: DBG_LPTIM1_STOP + description: "LPTIM1 stop in CPU debug\r Access can be protected by GTZC_TZSC.LPTIM1SEC." + bit_offset: 17 + bit_size: 1 + - name: DBG_RTC_STOP + description: "RTC stop in CPU debug\r Access can be protected by GTZC_TZSC.TIM17SEC.\r Can only be accessed secure when one or more features in the RTC or TAMP is/are secure." + bit_offset: 30 + bit_size: 1 +fieldset/CIDR0: + description: CoreSight component identity register 0 + fields: + - name: PREAMBLE + description: Component ID bits [7:0] + bit_offset: 0 + bit_size: 8 +fieldset/CIDR1: + description: CoreSight peripheral identity register 1 + fields: + - name: PREAMBLE + description: Component ID bits [11:8] + bit_offset: 0 + bit_size: 4 + - name: CLASS + description: Component ID bits [15:12] - component class + bit_offset: 4 + bit_size: 4 +fieldset/CIDR2: + description: CoreSight component identity register 2 + fields: + - name: PREAMBLE + description: Component ID bits [23:16] + bit_offset: 0 + bit_size: 8 +fieldset/CIDR3: + description: CoreSight component identity register 3 + fields: + - name: PREAMBLE + description: Component ID bits [31:24] + bit_offset: 0 + bit_size: 8 +fieldset/CR: + description: status and configuration register + fields: + - name: DBG_STOP + description: "Allows debug in Stop mode\r Write access can be protected by PWR_SECCFGR.LPMSEC.\r The CPU debug and clocks remain active and the HSI16 oscillators is used as system clock during Stop debug mode, allowing CPU debug capability. On exit from Stop mode, the clock settings are set to the Stop mode exit state." + bit_offset: 1 + bit_size: 1 + - name: DBG_STANDBY + description: "Allows debug in Standby mode\r Write access can be protected by PWR_SECCFGR.LPMSEC.\r The CPU debug and clocks remain active and the HSI16 oscillator is used as system clock, the supply and SRAM memory content is maintained during Standby debug mode, allowing CPU debug capability. On exit from Standby mode, a standby reset is performed." + bit_offset: 2 + bit_size: 1 + - name: LPMS + description: "Device low power mode selected\r 10x: Standby mode\r others reserved" + bit_offset: 16 + bit_size: 3 + - name: STOPF + description: Device Stop flag + bit_offset: 19 + bit_size: 1 + - name: SBF + description: Device Standby flag + bit_offset: 20 + bit_size: 1 + - name: CS + description: CPU Sleep + bit_offset: 24 + bit_size: 1 + - name: CDS + description: CPU DeepSleep + bit_offset: 25 + bit_size: 1 +fieldset/DBG_AUTH_DEVICE: + description: debug device authentication register + fields: + - name: AUTH_ID + description: "Device specific ID\r Device specific ID used for RDP regression." + bit_offset: 0 + bit_size: 32 +fieldset/DBG_AUTH_HOST: + description: debug host authentication register + fields: + - name: AUTH_KEY + description: "Device authentication key\r The device specific 64-bit authentication key (OEMn key) must be written to this register (in two successive 32-bit writes, least significant word first) to permit RDP regression. Writing a wrong key locks access to the device and prevent code execution from the Flash memory." + bit_offset: 0 + bit_size: 32 +fieldset/IDCODE: + description: identity code register + fields: + - name: DEV_ID + description: Device ID + bit_offset: 0 + bit_size: 12 + - name: REV_ID + description: Revision ID + bit_offset: 16 + bit_size: 16 +fieldset/PIDR0: + description: CoreSight peripheral identity register 0 + fields: + - name: PARTNUM + description: Part number bits [7:0] + bit_offset: 0 + bit_size: 8 +fieldset/PIDR1: + description: CoreSight peripheral identity register 1 + fields: + - name: PARTNUM + description: Part number bits [11:8] + bit_offset: 0 + bit_size: 4 + - name: JEP106ID + description: JEP106 identity code bits [3:0] + bit_offset: 4 + bit_size: 4 +fieldset/PIDR2: + description: CoreSight peripheral identity register 2 + fields: + - name: JEP106ID + description: JEP106 identity code bits [6:4] + bit_offset: 0 + bit_size: 3 + - name: JEDEC + description: JEDEC assigned value + bit_offset: 3 + bit_size: 1 + - name: REVISION + description: Component revision number + bit_offset: 4 + bit_size: 4 +fieldset/PIDR3: + description: CoreSight peripheral identity register 3 + fields: + - name: CMOD + description: Customer modified + bit_offset: 0 + bit_size: 4 + - name: REVAND + description: Metal fix version + bit_offset: 4 + bit_size: 4 +fieldset/PIDR4: + description: CoreSight peripheral identity register 4 + fields: + - name: JEP106CON + description: JEP106 continuation code + bit_offset: 0 + bit_size: 4 + - name: F4KCOUNT + description: Register file size + bit_offset: 4 + bit_size: 4 +fieldset/PNCR: + description: part number codification register + fields: + - name: CODIFICATION + description: Part number codification + bit_offset: 0 + bit_size: 32 +fieldset/SR: + description: status register + fields: + - name: AP_PRESENT + description: "Bit n identifies whether access port APn is present in device \r Bit n�=�0: APn absent \r Bit n�=�1: APn present" + bit_offset: 0 + bit_size: 16 + - name: AP_ENABLED + description: "Bit n identifies whether access port APn is open (can be accessed via the debug port) or locked (debug access to the APn is blocked, except for access) \r Bit n�=�0: APn locked (except for access to DBGMCU)\r Bit n�=�1: APn enabled" + bit_offset: 16 + bit_size: 16 diff --git a/data/registers/flash_wba.yaml b/data/registers/flash_wba.yaml new file mode 100644 index 0000000..21aa791 --- /dev/null +++ b/data/registers/flash_wba.yaml @@ -0,0 +1,643 @@ +block/FLASH: + description: Embedded memory + items: + - name: ACR + description: access control register + byte_offset: 0 + fieldset: ACR + - name: NSKEYR + description: key register + byte_offset: 8 + fieldset: NSKEYR + - name: SECKEYR + description: secure key register + byte_offset: 12 + fieldset: SECKEYR + - name: OPTKEYR + description: option key register + byte_offset: 16 + fieldset: OPTKEYR + - name: PDKEYR + description: power-down key register + byte_offset: 24 + fieldset: PDKEYR + - name: NSSR + description: status register + byte_offset: 32 + fieldset: NSSR + - name: SECSR + description: secure status register + byte_offset: 36 + fieldset: SECSR + - name: NSCR1 + description: control register + byte_offset: 40 + fieldset: NSCR1 + - name: SECCR1 + description: secure control register + byte_offset: 44 + fieldset: SECCR1 + - name: ECCR + description: ECC register + byte_offset: 48 + fieldset: ECCR + - name: OPSR + description: operation status register + byte_offset: 52 + fieldset: OPSR + - name: NSCR2 + description: control 2 register + byte_offset: 56 + fieldset: NSCR2 + - name: SECCR2 + description: secure control 2 register + byte_offset: 60 + fieldset: SECCR2 + - name: OPTR + description: option register + byte_offset: 64 + fieldset: OPTR + - name: NSBOOTADD0R + description: boot address 0 register + byte_offset: 68 + fieldset: NSBOOTADD0R + - name: NSBOOTADD1R + description: boot address 1 register + byte_offset: 72 + fieldset: NSBOOTADD1R + - name: SECBOOTADD0R + description: secure boot address 0 register + byte_offset: 76 + fieldset: SECBOOTADD0R + - name: SECWMR1 + description: secure watermark register 1 + byte_offset: 80 + fieldset: SECWMR1 + - name: SECWMR2 + description: secure watermark register 2 + byte_offset: 84 + fieldset: SECWMR2 + - name: WRPAR + description: WRP area A address register + byte_offset: 88 + fieldset: WRPAR + - name: WRPBR + description: WRP area B address register + byte_offset: 92 + fieldset: WRPBR + - name: OEM1KEYR1 + description: OEM1 key register 1 + byte_offset: 112 + - name: OEM1KEYR2 + description: OEM1 key register 2 + byte_offset: 116 + - name: OEM2KEYR1 + description: OEM2 key register 1 + byte_offset: 120 + - name: OEM2KEYR2 + description: OEM2 key register 2 + byte_offset: 124 + - name: SECBBR + description: secure block based register 1 + array: + len: 4 + stride: 4 + byte_offset: 128 + fieldset: BBR + - name: SECHDPCR + description: secure HDP control register + byte_offset: 192 + fieldset: SECHDPCR + - name: PRIFCFGR + description: privilege configuration register + byte_offset: 196 + fieldset: PRIFCFGR + - name: PRIVBBR + description: privilege block based register 1 + array: + len: 4 + stride: 4 + byte_offset: 208 + fieldset: BBR +fieldset/ACR: + description: access control register + fields: + - name: LATENCY + description: "Latency\r These bits represent the ratio between the AHB hclk1 clock period and the memory access time.\r Access to the bit can be secured by RCC SYSCLKSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.\r ...\r Note: Before entering Stop 1 mode software must set wait state latency to at least 1." + bit_offset: 0 + bit_size: 4 + - name: PRFTEN + description: "Prefetch enable\r This bit enables the prefetch buffer in the embedded memory.\r This bit can be protected against unprivileged access by NSPRIV." + bit_offset: 8 + bit_size: 1 + - name: LPM + description: "Low-power read mode\r This bit puts the memory in low-power read mode.\r Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.\r This bit can’t be written when a program or erase operation is busy (BSY = 1) or when the write buffer is not empty (WDW = 1). Changing this bit while a program or erase operation is busy (BSY = 1) is rejected." + bit_offset: 11 + bit_size: 1 + - name: PDREQ + description: "power-down mode request\r This bit requests to enter power-down mode. When enters power-down mode, this bit is cleared by hardware and the PDKEYR is locked.\r This bit is write-protected with PDKEYR. \r Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV." + bit_offset: 12 + bit_size: 1 + - name: SLEEP_PD + description: "memory power-down mode during Sleep mode\r This bit determines whether the memory is in power-down mode or Idle mode when the device is in Sleep mode.\r Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.\r The must not be put in power-down while a program or an erase operation is ongoing." + bit_offset: 14 + bit_size: 1 +fieldset/BBR: + description: block based register + fields: + - name: BLOCK + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 +fieldset/ECCR: + description: ECC register + fields: + - name: ADDR_ECC + description: "ECC fail address\r This field indicates which address is concerned by the ECC error correction or by the double ECC error detection. The address is given relative to base address, from offset 0x0�0000 to 0xF�FFF0.\r Note that bit 19 is reserved on STM32WBAxEx devices." + bit_offset: 0 + bit_size: 20 + - name: SYSF_ECC + description: "System memory ECC fail\r This bit indicates that the ECC error correction or double ECC error detection is located in the system memory." + bit_offset: 22 + bit_size: 1 + - name: ECCIE + description: "ECC correction interrupt enable\r This bit enables the interrupt generation when the ECCC bit in the ECCR register is set." + bit_offset: 24 + bit_size: 1 + - name: ECCC + description: "ECC correction\r This bit is set by hardware when one ECC error has been detected and corrected (only if ECCC and ECCD were previously cleared). An interrupt is generated if ECCIE is set. This bit is cleared by writing 1." + bit_offset: 30 + bit_size: 1 + - name: ECCD + description: "ECC detection\r This bit is set by hardware when two ECC errors have been detected (only if ECCC and ECCD were previously cleared). When this bit is set, a NMI is generated. This bit is cleared by writing 1." + bit_offset: 31 + bit_size: 1 +fieldset/NSBOOTADD0R: + description: boot address 0 register + fields: + - name: NSBOOTADD0 + description: "Non-secure boot base address 0\r This address is only used when TZEN = 0.\r The non-secure boot memory address can be programmed to any address in the valid address range (see Table 28: Boot space versus RDP protection) with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or NSWBOOT0 state.\r Examples:\r NSBOOTADD0[24:0] = 0x0100000: Boot from memory (0x0800 0000)\r NSBOOTADD0[24:0] = 0x017F100: Boot from system memory bootloader (0x0BF8 8000)\r NSBOOTADD0[24:0] = 0x0400200: Boot from SRAM2 on S-Bus (0x2001 0000)" + bit_offset: 7 + bit_size: 25 +fieldset/NSBOOTADD1R: + description: boot address 1 register + fields: + - name: NSBOOTADD1 + description: "Non-secure boot address 1\r This address is only used when TZEN = 0.\r The non-secure boot memory address can be programmed to any address in the valid address range (see Table 28: Boot space versus RDP protection) with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or NSWBOOT0 state. \r Examples:\r NSBOOTADD1[24:0] = 0x0100000: Boot from memory (0x0800 0000)\r NSBOOTADD1[24:0] = 0x017F100: Boot from system memory bootloader (0x0BF8 8000)\r NSBOOTADD1[24:0] = 0x0400200: Boot from SRAM2 (0x2001 0000)" + bit_offset: 7 + bit_size: 25 +fieldset/NSCR1: + description: control register + fields: + - name: PG + description: Non-secure programming + bit_offset: 0 + bit_size: 1 + - name: PER + description: Non-secure page erase + bit_offset: 1 + bit_size: 1 + - name: MER + description: "Non-secure mass erase\r This bit triggers the non-secure mass erase (all user pages) when set." + bit_offset: 2 + bit_size: 1 + - name: PNB + description: "Non-secure page number selection\r These bits select the page to erase.\r ...\r Note that bit 9 is reserved on STM32WBA5xEx devices." + bit_offset: 3 + bit_size: 7 + - name: BWR + description: "Non-secure burst write programming mode\r When set, this bit selects the burst write programming mode." + bit_offset: 14 + bit_size: 1 + - name: STRT + description: "Non-secure operation start \r This bit triggers a non-secure erase operation when set. If MER and PER bits are reset and the STRT bit is set, the PGSERR bit in NSSR is set (this condition is forbidden).\r This bit is set only by software and is cleared when the BSY bit is cleared in NSSR." + bit_offset: 16 + bit_size: 1 + - name: OPTSTRT + description: "Options modification start\r This bit triggers an option bytes erase and program operation when set. This bit is write-protected with OPTLOCK.. This bit is set only by software, and is cleared when the BSY bit is cleared in NSSR." + bit_offset: 17 + bit_size: 1 + - name: EOPIE + description: "Non-secure end of operation interrupt enable\r This bit enables the interrupt generation when the EOP bit in the NSSR is set to 1." + bit_offset: 24 + bit_size: 1 + - name: ERRIE + description: "Non-secure error interrupt enable\r This bit enables the interrupt generation when the OPERR bit in the NSSR is set to 1." + bit_offset: 25 + bit_size: 1 + - name: OBL_LAUNCH + description: "Force the option byte loading\r When set to 1, this bit forces the option byte reloading. This bit is cleared only when the option byte loading is complete. This bit is write-protected with OPTLOCK.\r Note: The LSE oscillator must be disabled, LSEON = 0 and LSERDY = 0, before starting OBL_LAUNCH." + bit_offset: 27 + bit_size: 1 + - name: OPTLOCK + description: "Option lock\r This bit is set only. When set, the NSCR1.OPTSRT and OBL_LAUNCH bits concerning user options write access is locked. This bit is cleared by hardware after detecting the unlock sequence in OPTKEYR. The NSCR1.LOCK bit must be cleared before doing the OPTKEYR unlock sequence.\r In case of an unsuccessful unlock operation, this bit remains set until the next reset." + bit_offset: 30 + bit_size: 1 + - name: LOCK + description: "Non-secure lock\r This bit is set only.\r When set, the NSCR1 register write access is locked. This bit is cleared by hardware after detecting the unlock sequence in NSKEYR.\r In case of an unsuccessful unlock operation, this bit remains set until the next system reset." + bit_offset: 31 + bit_size: 1 +fieldset/NSCR2: + description: control 2 register + fields: + - name: PS + description: Program suspend request + bit_offset: 0 + bit_size: 1 + - name: ES + description: Erase suspend request + bit_offset: 1 + bit_size: 1 +fieldset/NSKEYR: + description: key register + fields: + - name: NSKEY + description: "memory non-secure key\r The following values must be written consecutively to unlock the NSCR1 register, allowing the memory non-secure programming/erasing operations:\r KEY1: 0x4567�0123\r KEY2: 0xCDEF�89AB" + bit_offset: 0 + bit_size: 32 +fieldset/NSSR: + description: status register + fields: + - name: EOP + description: "Non-secure end of operation\r This bit is set by hardware when one or more memory non-secure operation (program/erase) has been completed successfully. This bit is set only if the non-secure end of operation interrupts are enabled (EOPIE = 1 in NSCR1). This bit is cleared by writing�1." + bit_offset: 0 + bit_size: 1 + - name: OPERR + description: "Non-secure operation error\r This bit is set by hardware when a memory non-secure operation (program/erase) completes unsuccessfully. This bit is set only if non-secure error interrupts are enabled (NSERRIE = 1). This bit is cleared by writing 1." + bit_offset: 1 + bit_size: 1 + - name: PROGERR + description: "Non-secure programming error\r This bit is set by hardware when a non-secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1." + bit_offset: 3 + bit_size: 1 + - name: WRPERR + description: "Non-secure write protection error\r This bit is set by hardware when a non-secure address to be erased/programmed belongs to a write-protected part (by WRP or HDP) of the memory. This bit is cleared by writing 1.\r Refer to Section�7.3.10: memory errors flags for full conditions of error flag setting." + bit_offset: 4 + bit_size: 1 + - name: PGAERR + description: "Non-secure programming alignment error\r This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address. This bit is cleared by writing 1." + bit_offset: 5 + bit_size: 1 + - name: SIZERR + description: "Non-secure size error\r This bit is set by hardware when the size of the access is a byte or half-word during a non-secure program sequence. Only quad-word programming is allowed by means of successive word accesses. This bit is cleared by writing 1." + bit_offset: 6 + bit_size: 1 + - name: PGSERR + description: "Non-secure programming sequence error\r This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1.\r Refer to Section�7.3.10: memory errors flags for full conditions of error flag setting." + bit_offset: 7 + bit_size: 1 + - name: OPTWERR + description: "Option write error \r This bit is set by hardware when the options bytes are written with an invalid configuration or when modifying options in RDP level 2.. It is cleared by writing 1.\r Refer to Section�7.3.10: memory errors flags for full conditions of error flag setting." + bit_offset: 13 + bit_size: 1 + - name: BSY + description: "Non-secure busy\r This indicates that a memory secure or non-secure operation is in progress. This bit is set at the beginning of a operation and reset when the operation finishes or when an error occurs." + bit_offset: 16 + bit_size: 1 + - name: WDW + description: "Non-secure wait data to write\r This bit indicates that the memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the memory." + bit_offset: 17 + bit_size: 1 + - name: OEM1LOCK + description: "OEM1 key RDP lock\r This bit indicates that the OEM1 key read during the OBL is not virgin. When set, the OEM1 key RDP lock mechanism is active." + bit_offset: 18 + bit_size: 1 + - name: OEM2LOCK + description: "OEM2 key RDP lock\r This bit indicates that the OEM2 key read during the OBL is not virgin. When set, the OEM2 key RDP lock mechanism is active." + bit_offset: 19 + bit_size: 1 + - name: PD + description: "in power-down mode\r This bit indicates that the memory is in power-down state. It is reset when is in normal mode or being awaken." + bit_offset: 20 + bit_size: 1 +fieldset/OPSR: + description: operation status register + fields: + - name: ADDR_OP + description: "Interrupted operation address\r This field indicates which address in the memory was accessed when reset occurred. The address is given relative to the base address, from offset 0x0�0000 to 0xF�FFF0.\r Note that bit 19 is reserved on STM32WBAxEx devices." + bit_offset: 0 + bit_size: 20 + - name: SYSF_OP + description: "Operation in system memory interrupted\r This bit indicates that the reset occurred during an operation in the system memory." + bit_offset: 22 + bit_size: 1 + - name: CODE_OP + description: "memory operation code\r This field indicates which memory operation has been interrupted by a system reset:" + bit_offset: 29 + bit_size: 3 + enum: CODE_OP +fieldset/OPTKEYR: + description: option key register + fields: + - name: OPTKEY + description: "Option byte key\r The LOCK bit in the NSCR1 must be cleared before doing the unlock sequence for OPTLOCK bit. The following values must be written consecutively to unlock the NSCR1.OPTSTRT and OBL_LAUNCH register bits concerning user option operations:\r KEY1: 0x0819�2A3B\r KEY2: 0x4C5D�6E7F" + bit_offset: 0 + bit_size: 32 +fieldset/OPTR: + description: option register + fields: + - name: RDP + description: "Readout protection level\r Others: Level 1 (memories readout protection active)\r Note: Refer to Section�7.6.2: Readout protection (RDP) for more details." + bit_offset: 0 + bit_size: 8 + enum: RDP + - name: BOR_LEV + description: "BOR reset level\r These bits contain the VDD supply level threshold that activates/releases the reset." + bit_offset: 8 + bit_size: 3 + enum: BOR_LEV + - name: NRST_STOP + description: Reset generation in Stop mode + bit_offset: 12 + bit_size: 1 + - name: NRST_STDBY + description: Reset generation in Standby mode + bit_offset: 13 + bit_size: 1 + - name: SRAM1_RST + description: SRAM1 erase upon system reset + bit_offset: 15 + bit_size: 1 + - name: IWDG_SW + description: Independent watchdog enable selection + bit_offset: 16 + bit_size: 1 + - name: IWDG_STOP + description: Independent watchdog counter freeze in Stop mode + bit_offset: 17 + bit_size: 1 + - name: IWDG_STDBY + description: Independent watchdog counter freeze in Standby mode + bit_offset: 18 + bit_size: 1 + - name: WWDG_SW + description: Window watchdog selection + bit_offset: 19 + bit_size: 1 + - name: SRAM2_PE + description: SRAM2 parity check enable + bit_offset: 24 + bit_size: 1 + - name: SRAM2_RST + description: SRAM2 erase when system reset + bit_offset: 25 + bit_size: 1 + - name: NSWBOOT0 + description: Software BOOT0 + bit_offset: 26 + bit_size: 1 + - name: NBOOT0 + description: NBOOT0 option bit + bit_offset: 27 + bit_size: 1 + - name: TZEN + description: Global TrustZone security enable + bit_offset: 31 + bit_size: 1 +fieldset/PDKEYR: + description: power-down key register + fields: + - name: PDKEY1 + description: "power-down key\r The following values must be written consecutively to unlock the PDREQ bit in ACR:\r PDKEY_1: 0x0415�2637\r PDKEY_2: 0xFAFB�FCFD" + bit_offset: 0 + bit_size: 32 +fieldset/PRIFCFGR: + description: privilege configuration register + fields: + - name: SPRIV + description: "Privileged protection for secure registers\r This bit is secure write protected. It can only be written by a secure privileged access when TrustZone is enabled (TZEN�=�1)." + bit_offset: 0 + bit_size: 1 + - name: NSPRIV + description: Privileged protection for non-secure registers + bit_offset: 1 + bit_size: 1 +fieldset/SECBOOTADD0R: + description: secure boot address 0 register + fields: + - name: BOOT_LOCK + description: "Boot lock\r This lock is only used when TZEN = 0.\r When set, the boot is always forced to base address value programmed in SECBOOTADD0[24:0] option bytes whatever the boot selection option. When set, this bit can only be cleared by an RDP regression level 1 to level 0." + bit_offset: 0 + bit_size: 1 + - name: SECBOOTADD0 + description: "Secure boot base address 0\r This address is only used when TZEN = 1.\r The secure boot memory address can be programmed to any address in the valid address range (see Table�28: Boot space versus RDP protection) with a granularity of 128 bytes. This bits correspond to address [31:7] The SECBOOTADD0 option bytes are selected following the BOOT0 pin or NSWBOOT0 state. \r Examples:\r SECBOOTADD0[24:0] = 0x018 0000: Boot from secure user memory (0x0C00 0000)\r SECBOOTADD0[24:0] = 0x01F F000: Boot from RSS system memory (0x0FF8 0000)\r SECBOOTADD0[24:0] = 0x060 0000: Boot from secure SRAM1 on S-Bus (0x3000 0000)" + bit_offset: 7 + bit_size: 25 +fieldset/SECCR1: + description: secure control register + fields: + - name: PG + description: Secure programming + bit_offset: 0 + bit_size: 1 + - name: PER + description: Secure page erase + bit_offset: 1 + bit_size: 1 + - name: MER + description: "Secure mass erase\r This bit triggers the secure mass erase (all user pages) when set." + bit_offset: 2 + bit_size: 1 + - name: PNB + description: "Secure page number selection\r These bits select the page to erase:\r ...\r Note that bit 9 is reserved on STM32WBA5xEx devices." + bit_offset: 3 + bit_size: 7 + - name: BWR + description: "Secure burst write programming mode\r When set, this bit selects the burst write programming mode." + bit_offset: 14 + bit_size: 1 + - name: STRT + description: "Secure start \r This bit triggers a secure erase operation when set. If MER and PER bits are reset and the STRT bit is set, the PGSERR in the SECSR is set (this condition is forbidden).\r This bit is set only by software and is cleared when the BSY bit is cleared in SECSR." + bit_offset: 16 + bit_size: 1 + - name: EOPIE + description: "Secure End of operation interrupt enable\r This bit enables the interrupt generation when the EOP bit in SECSR is set to 1." + bit_offset: 24 + bit_size: 1 + - name: ERRIE + description: "Secure error interrupt enable\r This bit enables the interrupt generation when the OPERR bit in SECSR is set to 1." + bit_offset: 25 + bit_size: 1 + - name: INV + description: "memory security state invert\r This bit inverts the memory security state." + bit_offset: 29 + bit_size: 1 + - name: LOCK + description: "Secure lock\r This bit is set only. When set, the SECCR1 register is locked. It is cleared by hardware after detecting the unlock sequence in SECKEYR register.\r In case of an unsuccessful unlock operation, this bit remains set until the next system reset." + bit_offset: 31 + bit_size: 1 +fieldset/SECCR2: + description: secure control 2 register + fields: + - name: PS + description: Program suspend request + bit_offset: 0 + bit_size: 1 + - name: ES + description: Erase suspend request + bit_offset: 1 + bit_size: 1 +fieldset/SECHDPCR: + description: secure HDP control register + fields: + - name: HDP_ACCDIS + description: "Secure HDP area access disable \r When set, this bit is only cleared by a system reset." + bit_offset: 0 + bit_size: 1 +fieldset/SECKEYR: + description: secure key register + fields: + - name: SECKEY + description: "memory secure key\r The following values must be written consecutively to unlock the SECCR1 register, allowing the memory secure programming/erasing operations:\r KEY1: 0x4567�0123\r KEY2: 0xCDEF�89AB" + bit_offset: 0 + bit_size: 32 +fieldset/SECSR: + description: secure status register + fields: + - name: EOP + description: "Secure end of operation\r This bit is set by hardware when one or more memory secure operation (program/erase) has been completed successfully. This bit is set only if the secure end of operation interrupts are enabled (EOPIE = 1 in SECCR1). This bit is cleared by writing�1." + bit_offset: 0 + bit_size: 1 + - name: OPERR + description: "Secure operation error\r This bit is set by hardware when a memory secure operation (program/erase) completes unsuccessfully. This bit is set only if secure error interrupts are enabled (SECERRIE = 1). This bit is cleared by writing 1." + bit_offset: 1 + bit_size: 1 + - name: PROGERR + description: "Secure programming error\r This bit is set by hardware when a secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1." + bit_offset: 3 + bit_size: 1 + - name: WRPERR + description: "Secure write protection error\r This bit is set by hardware when an secure address to be erased/programmed belongs to a write-protected part (by WRP or HDP) of the memory. This bit is cleared by writing 1.\r Refer to Section�7.3.10: memory errors flags for full conditions of error flag setting." + bit_offset: 4 + bit_size: 1 + - name: PGAERR + description: "Secure programming alignment error\r This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address.This bit is cleared by writing 1." + bit_offset: 5 + bit_size: 1 + - name: SIZERR + description: "Secure size error\r This bit is set by hardware when the size of the access is a byte or half-word during a secure program sequence. Only quad-word programming is allowed by means of successive word accesses.This bit is cleared by writing 1." + bit_offset: 6 + bit_size: 1 + - name: PGSERR + description: "Secure programming sequence error\r This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1.\r Refer to Section�7.3.10: memory errors flags for full conditions of error flag setting." + bit_offset: 7 + bit_size: 1 + - name: BSY + description: "Secure busy\r This bit indicates that a memory secure or non-secure operation is in progress. This is set on the beginning of a operation and reset when the operation finishes or when an error occurs." + bit_offset: 16 + bit_size: 1 + - name: WDW + description: "Secure wait data to write\r This bit indicates that the memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the memory." + bit_offset: 17 + bit_size: 1 +fieldset/SECWMR1: + description: secure watermark register 1 + fields: + - name: SECWM_PSTRT + description: "Start page of secure area\r This field contains the first page of the secure area." + bit_offset: 0 + bit_size: 7 + - name: SECWM_PEND + description: "End page of secure area\r This field contains the last page of the secure area." + bit_offset: 16 + bit_size: 7 +fieldset/SECWMR2: + description: secure watermark register 2 + fields: + - name: HDP_PEND + description: "End page of secure hide protection area\r This field contains the last page of the secure HDP area." + bit_offset: 16 + bit_size: 7 + - name: HDPEN + description: Secure Hide protection area enable + bit_offset: 31 + bit_size: 1 +fieldset/WRPAR: + description: WRP area A address register + fields: + - name: WRPA_PSTRT + description: "WPR area A start page\r This field contains the first page of the WPR area A.\r Note that bit 6 is reserved on STM32WBAxEx devices." + bit_offset: 0 + bit_size: 7 + - name: WRPA_PEND + description: "WPR area A end page\r This field contains the last page of the WPR area A.\r Note that bit 22 is reserved on STM32WBAxEx devices." + bit_offset: 16 + bit_size: 7 + - name: UNLOCK + description: WPR area A unlock + bit_offset: 31 + bit_size: 1 +fieldset/WRPBR: + description: WRP area B address register + fields: + - name: WRPB_PSTRT + description: "WRP area B start page\r This field contains the first page of the WRP area B.\r Note that bit 6 is reserved on STM32WBAxEx devices." + bit_offset: 0 + bit_size: 7 + - name: WRPB_PEND + description: "WRP area B end page\r This field contains the last page of the WRP area B.\r Note that bit 22 is reserved on STM32WBAxEx devices." + bit_offset: 16 + bit_size: 7 + - name: UNLOCK + description: WPR area B unlock + bit_offset: 31 + bit_size: 1 +enum/BOR_LEV: + bit_size: 3 + variants: + - name: Level0 + description: BOR level 0 (reset level threshold around 1.7�V) + value: 0 + - name: Level1 + description: BOR level 1 (reset level threshold around 2.0�V) + value: 1 + - name: Level2 + description: BOR level 2 (reset level threshold around 2.2�V) + value: 2 + - name: Level3 + description: BOR level 3 (reset level threshold around 2.5�V) + value: 3 + - name: Level4 + description: BOR level 4 (reset level threshold around 2.8�V) + value: 4 +enum/CODE_OP: + bit_size: 3 + variants: + - name: B_0x0 + description: No operation interrupted by previous reset + value: 0 + - name: B_0x1 + description: Single write operation interrupted + value: 1 + - name: B_0x2 + description: Burst write operation interrupted + value: 2 + - name: B_0x3 + description: Page erase operation interrupted + value: 3 + - name: B_0x4 + description: Reserved + value: 4 + - name: B_0x5 + description: Mass erase operation interrupted + value: 5 + - name: B_0x6 + description: Option change operation interrupted + value: 6 + - name: B_0x7 + description: Reserved + value: 7 +enum/RDP: + bit_size: 8 + variants: + - name: B_0x55 + description: Level 0.5 (readout protection not active, only non-secure debug access is possible). Only available when TrustZone is active (TZEN=1) + value: 85 + - name: B_0xAA + description: Level 0 (readout protection not active) + value: 170 + - name: B_0xCC + description: Level 2 (chip readout protection active) + value: 204 diff --git a/data/registers/pwr_wba.yaml b/data/registers/pwr_wba.yaml new file mode 100644 index 0000000..b1d12af --- /dev/null +++ b/data/registers/pwr_wba.yaml @@ -0,0 +1,537 @@ +block/PWR: + description: Power control + items: + - name: CR1 + description: control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2 + - name: CR3 + description: control register 3 + byte_offset: 8 + fieldset: CR3 + - name: VOSR + description: voltage scaling register + byte_offset: 12 + fieldset: VOSR + - name: SVMCR + description: supply voltage monitoring control register + byte_offset: 16 + fieldset: SVMCR + - name: WUCR1 + description: wakeup control register 1 + byte_offset: 20 + fieldset: WUCR1 + - name: WUCR2 + description: wakeup control register 2 + byte_offset: 24 + fieldset: WUCR2 + - name: WUCR3 + description: wakeup control register 3 + byte_offset: 28 + fieldset: WUCR3 + - name: DBPR + description: disable Backup domain register + byte_offset: 40 + fieldset: DBPR + - name: SECCFGR + description: security configuration register + byte_offset: 48 + fieldset: SECCFGR + - name: PRIVCFGR + description: privilege control register + byte_offset: 52 + fieldset: PRIVCFGR + - name: SR + description: status register + byte_offset: 56 + fieldset: SR + - name: SVMSR + description: supply voltage monitoring status register + byte_offset: 60 + fieldset: SVMSR + - name: WUSR + description: wakeup status register + byte_offset: 68 + fieldset: WUSR + - name: WUSCR + description: wakeup status clear register + byte_offset: 72 + fieldset: WUSCR + - name: IORETENR + description: port Standby IO retention enable register + array: + len: 8 + stride: 8 + byte_offset: 80 + fieldset: IORETENR + - name: IORETRA + description: port Standby IO retention status register + array: + len: 8 + stride: 8 + byte_offset: 84 + fieldset: IORETR + - name: RADIOSCR + description: 2.4 GHz RADIO status and control register + byte_offset: 256 + fieldset: RADIOSCR +fieldset/CR1: + description: control register 1 + fields: + - name: LPMS + description: "Low-power mode selection\r These bits select the low-power mode entered when the CPU enters the SleepDeep mode.\r 10x: Standby mode\r others reserved" + bit_offset: 0 + bit_size: 3 + enum: LPMS + - name: R2RSB1 + description: "SRAM2 retention in Standby mode\r This bit is used to keep the SRAM2 content in Standby retention mode." + bit_offset: 5 + bit_size: 1 + enum: RRSB + - name: ULPMEN + description: "BOR0 ultra-low-power mode. \r This bit is used to reduce the consumption by configuring the BOR0 in discontinuous mode for Stop 1 and Standby modes. Discontinuous mode is only available when BOR levels 1 to 4 and PVD are disabled.\r Note: This bit must be set to reach the lowest power consumption in the low-power modes.\r Note: This bit must not be set together with autonomous peripherals using HSI16 as kernel clock.\r Note: When BOR level 1 to 4 or PVD is enabled continuous mode applies independent from ULPMEN." + bit_offset: 7 + bit_size: 1 + - name: RADIORSB + description: "2.4 GHz RADIO SRAMs (RXTXRAM and Sequence RAM) and Sleep clock retention in Standby mode.\r This bit is used to keep the 2.4 GHz RADIO SRAMs content in Standby retention mode and the 2.4 GHz RADIO sleep timer counter operational." + bit_offset: 9 + bit_size: 1 + enum: RADIORSB + - name: R1RSB1 + description: "SRAM1 retention in Standby mode\r This bit is used to keep the SRAM1 content in Standby retention mode." + bit_offset: 12 + bit_size: 1 + enum: RRSB +fieldset/CR2: + description: control register 2 + fields: + - name: SRAM1PDS1 + description: "SRAM1 power-down in Stop modes (Stop 0, 1)\r Note: The SRAM1 retention in Standby mode is controlled by R1RSB1 bit in CR1." + bit_offset: 0 + bit_size: 1 + enum: SRAMPDS + - name: SRAM2PDS1 + description: "SRAM2 power-down in Stop modes (Stop 0, 1)\r Note: The SRAM2 retention in Standby mode is controlled by R2RSB1 bit in CR1." + bit_offset: 4 + bit_size: 1 + enum: SRAMPDS + - name: ICRAMPDS + description: ICACHE SRAM power-down in Stop modes (Stop 0, 1) + bit_offset: 8 + bit_size: 1 + enum: ICRAMPDS + - name: FLASHFWU + description: "Flash memory fast wakeup from Stop modes (Stop 0, 1)\r This bit is used to obtain the best trade-off between low-power consumption and wakeup time when exiting the Stop 0 or Stop 1 modes.\r When this bit is set, the Flash memory remains in normal mode in Stop 0 and Stop 1 modes, which offers a faster startup time with higher consumption." + bit_offset: 14 + bit_size: 1 + enum: FLASHFWU +fieldset/CR3: + description: control register 3 + fields: + - name: FSTEN + description: Fast soft start + bit_offset: 2 + bit_size: 1 +fieldset/DBPR: + description: disable Backup domain register + fields: + - name: DBP + description: "Disable Backup domain write protection\r In reset state, all registers and SRAM in Backup domain are protected against parasitic write access. This bit must be set to enable the write access to these registers." + bit_offset: 0 + bit_size: 1 +fieldset/IORETENR: + description: port A Standby IO retention enable register + fields: + - name: EN + description: "Port A Standby GPIO retention enable\r Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV.\r When set, each bit enables the Standby GPIO retention feature for PAy" + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 +fieldset/IORETR: + description: port A Standby IO retention status register + fields: + - name: RET + description: "Port A Standby GPIO retention active\r Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV." + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 +fieldset/PRIVCFGR: + description: privilege control register + fields: + - name: SPRIV + description: "secure functions privilege configuration\r This bit is set and reset by software.\r It can be written only by a secure privileged access." + bit_offset: 0 + bit_size: 1 + enum: PRIV + - name: NSPRIV + description: "non-secure functions privilege configuration\r This bit is set and reset by software.\r It can be written only by privileged access, secure or non-secure." + bit_offset: 1 + bit_size: 1 + enum: PRIV +fieldset/RADIOSCR: + description: 2.4 GHz RADIO status and control register + fields: + - name: MODE + description: "2.4 GHz RADIO operating mode.\r 1x: 2.4 GHz RADIO active mode" + bit_offset: 0 + bit_size: 2 + enum: MODE + - name: PHYMODE + description: 2.4 GHz RADIO PHY operating mode + bit_offset: 2 + bit_size: 1 + - name: ENCMODE + description: 2.4 GHz RADIO encryption function operating mode + bit_offset: 3 + bit_size: 1 + - name: RFVDDHPA + description: "2.4 GHz RADIO VDDHPA control word.\r Bits [3:0] see Table 81: PA output power table format for definition.\r Bit [4] rf_event." + bit_offset: 8 + bit_size: 5 + - name: REGPARDYVDDRFPA + description: "Ready bit for VDDHPA voltage level when selecting VDDRFPA input.\r Note: REGPARDYVDDRFPA does not allow to detect correct VDDHPA voltage level when request to lower the level." + bit_offset: 15 + bit_size: 1 + enum: REGPARDYVDDRFPA +fieldset/SECCFGR: + description: security configuration register + fields: + - name: WUP1SEC + description: WUP1 secure protection + bit_offset: 0 + bit_size: 1 + array: + len: 8 + stride: 1 + enum: SEC + - name: LPMSEC + description: Low-power modes secure protection + bit_offset: 12 + bit_size: 1 + enum: SEC + - name: VDMSEC + description: Voltage detection secure protection + bit_offset: 13 + bit_size: 1 + enum: SEC + - name: VBSEC + description: Backup domain secure protection + bit_offset: 14 + bit_size: 1 + enum: SEC +fieldset/SR: + description: status register + fields: + - name: CSSF + description: "Clear Stop and Standby flags\r Access can be secured by LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.\r Writing 1 to this bit clears the STOPF and SBF flags." + bit_offset: 0 + bit_size: 1 + - name: STOPF + description: "Stop flag\r This bit is set by hardware when the device enters a Stop or Standby mode at the same time as the sysclk has been set by hardware to select HSI16. It’s cleared by software by writing 1 to the CSSF bit and by hardware when SBF is set." + bit_offset: 1 + bit_size: 1 + - name: SBF + description: "Standby flag\r This bit is set by hardware when the device enters the Standby mode and the CPU restart from its reset vector. It’s cleared by writing 1 to the CSSF bit, or by a power-on reset. It is not cleared by the system reset." + bit_offset: 2 + bit_size: 1 +fieldset/SVMCR: + description: supply voltage monitoring control register + fields: + - name: PVDE + description: Programmable voltage detector enable + bit_offset: 4 + bit_size: 1 + - name: PVDLS + description: "Programmable voltage detector level selection\r These bits select the voltage threshold detected by the programmable voltage detector:" + bit_offset: 5 + bit_size: 3 + enum: PVDLS +fieldset/SVMSR: + description: supply voltage monitoring status register + fields: + - name: PVDO + description: Programmable voltage detector output + bit_offset: 4 + bit_size: 1 + enum: PVDO + - name: ACTVOSRDY + description: Voltage level ready for currently used VOS + bit_offset: 15 + bit_size: 1 + - name: ACTVOS + description: "VOS currently applied to VCORE\r This field provides the last VOS value." + bit_offset: 16 + bit_size: 1 + enum: ACTVOS +fieldset/VOSR: + description: voltage scaling register + fields: + - name: VOSRDY + description: "Ready bit for VCORE voltage scaling output selection\r Set and cleared by hardware. When decreasing the voltage scaling range, VOSRDY must be one before increasing the SYSCLK frequency." + bit_offset: 15 + bit_size: 1 + - name: VOS + description: "Voltage scaling range selection\r Set a and cleared by software.\r Cleared by hardware when entering Stop 1 mode.\r Access can be secured by RCC SYSCLKSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV." + bit_offset: 16 + bit_size: 1 + enum: VOS +fieldset/WUCR1: + description: wakeup control register 1 + fields: + - name: WUPEN + description: "Wakeup and interrupt pin WKUP1 enable\r Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV." + bit_offset: 0 + bit_size: 1 + array: + len: 8 + stride: 1 +fieldset/WUCR2: + description: wakeup control register 2 + fields: + - name: WUPP + description: "Wakeup pin WKUP1 polarity.\r This bit must be configured when WUPEN1 = 0.\r Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV." + bit_offset: 0 + bit_size: 1 + array: + len: 8 + stride: 1 + enum: WUPP +fieldset/WUCR3: + description: wakeup control register 3 + fields: + - name: WUSEL1 + description: "Wakeup and interrupt pin WKUP1 selection\r This field must be configured when WUPEN1 = 0.\r Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV." + bit_offset: 0 + bit_size: 2 + enum: WUSEL + - name: WUSEL2 + description: "Wakeup and interrupt pin WKUP2 selection\r This field must be configured when WUPEN2 = 0.\r Access can be secured by WUP2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV." + bit_offset: 2 + bit_size: 2 + enum: WUSEL + - name: WUSEL3 + description: "Wakeup and interrupt pin WKUP3 selection\r This field must be configured when WUPEN3 = 0.\r Access can be secured by WUP3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV." + bit_offset: 4 + bit_size: 2 + enum: WUSEL + - name: WUSEL4 + description: "Wakeup and interrupt pin WKUP4 selection\r This field must be configured when WUPEN4 = 0.\r Access can be secured by WUP4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV." + bit_offset: 6 + bit_size: 2 + enum: WUSEL + - name: WUSEL5 + description: "Wakeup and interrupt pin WKUP5 selection\r This field must be configured when WUPEN5 = 0.\r Access can be secured by WUP5SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV." + bit_offset: 8 + bit_size: 2 + enum: WUSEL + - name: WUSEL6 + description: "Wakeup and interrupt pin WKUP6 selection\r This field must be configured when WUPEN6 = 0.\r Access can be secured by WUP6SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV." + bit_offset: 10 + bit_size: 2 + enum: WUSEL + - name: WUSEL7 + description: "Wakeup and interrupt pin WKUP7 selection\r This field must be configured when WUPEN7 = 0.\r Access can be secured by WUP7SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV." + bit_offset: 12 + bit_size: 2 + enum: WUSEL + - name: WUSEL8 + description: "Wakeup and interrupt pin WKUP8 selection\r This field must be configured when WUPEN8 = 0.\r Access can be secured by WUP8SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV." + bit_offset: 14 + bit_size: 2 + enum: WUSEL +fieldset/WUSCR: + description: wakeup status clear register + fields: + - name: CWUF + description: "Clear wakeup flag 1\r Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.\r Writing 1 to this bit clears the WUF1 flag in WUSR." + bit_offset: 0 + bit_size: 1 + array: + len: 8 + stride: 1 +fieldset/WUSR: + description: wakeup status register + fields: + - name: WUF + description: "Wakeup and interrupt pending flag 1\r This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by writing 1 in the CWUF1 bit of WUSCR or by hardware when WUPEN1 = 0." + bit_offset: 0 + bit_size: 1 + array: + len: 8 + stride: 1 +enum/ACTVOS: + bit_size: 1 + variants: + - name: Range2 + description: Range 2 (lowest power) + value: 0 + - name: Range1 + description: Range 1 (highest frequency) + value: 1 +enum/FLASHFWU: + bit_size: 1 + variants: + - name: LowPower + description: Flash memory enters low-power mode in Stop 0 and Stop 1 modes (lower-power consumption). + value: 0 + - name: Normal + description: Flash memory remains in normal mode in Stop 0 and Stop 1 modes (faster wakeup time). + value: 1 +enum/ICRAMPDS: + bit_size: 1 + variants: + - name: Retained + description: ICACHE SRAM content retained in Stop modes + value: 0 + - name: NotRetained + description: ICACHE SRAM content lost in Stop modes + value: 1 +enum/LPMS: + bit_size: 3 + variants: + - name: Stop0 + description: Stop 0 mode + value: 0 + - name: Stop1 + description: Stop 1 mode + value: 1 +enum/MODE: + bit_size: 2 + variants: + - name: DeepSleep + description: 2.4 GHz RADIO deep sleep mode + value: 0 + - name: Sleep + description: 2.4 GHz RADIO sleep mode + value: 1 +enum/PRIV: + bit_size: 1 + variants: + - name: Unprivileged + description: Read and write to non-secure functions can be done by privileged or unprivileged access. + value: 0 + - name: Privileged + description: Read and write to non-secure functions can be done by privileged access only. + value: 1 +enum/PVDLS: + bit_size: 3 + variants: + - name: v20 + description: VPVD0 around 2.0 V + value: 0 + - name: v22 + description: VPVD1 around 2.2 V + value: 1 + - name: v24 + description: VPVD2 around 2.4 V + value: 2 + - name: v25 + description: VPVD3 around 2.5 V + value: 3 + - name: v26 + description: VPVD4 around 2.6 V + value: 4 + - name: v28 + description: VPVD5 around 2.8 V + value: 5 + - name: v29 + description: VPVD6 around 2.9 V + value: 6 + - name: pvd_in + description: External input analog voltage PVD_IN (compared internally to VREFINT) + value: 7 +enum/PVDO: + bit_size: 1 + variants: + - name: AboveOrEqual + description: VDD is equal or above the PVD threshold selected by PVDLS[2:0]. + value: 0 + - name: Below + description: VDD is below the PVD threshold selected by PVDLS[2:0]. + value: 1 +enum/RADIORSB: + bit_size: 1 + variants: + - name: NotRetained + description: 2.4 GHz RADIO SRAMs and sleep timer content not retained in Standby mode + value: 0 + - name: Retained + description: 2.4 GHz RADIO SRAMs and sleep timer content retained in Standby mode + value: 1 +enum/REGPARDYVDDRFPA: + bit_size: 1 + variants: + - name: NotReady + description: Not ready, VDDHPA voltage level < REGPAVOS selected supply level + value: 0 + - name: Ready + description: Ready, VDDHPA voltage level ≥ REGPAVOS selected supply level + value: 1 +enum/RRSB: + bit_size: 1 + variants: + - name: B_0x0 + description: SRAM2 content not retained in Standby mode + value: 0 + - name: B_0x1 + description: SRAM2 content retained in Standby mode + value: 1 +enum/SEC: + bit_size: 1 + variants: + - name: NotSecure + description: SVMCR and CR3 can be read and written with secure or non-secure access. + value: 0 + - name: Secure + description: SVMCR and CR3 can be read and written only with secure access. + value: 1 +enum/SRAMPDS: + bit_size: 1 + variants: + - name: PoweredOn + description: SRAM1 content retained in Stop modes + value: 0 + - name: PoweredOff + description: SRAM1 content lost in Stop modes + value: 1 +enum/VOS: + bit_size: 1 + variants: + - name: Range2 + description: Range 2 (lowest power) + value: 0 + - name: Range1 + description: Range 1 (highest frequency). + value: 1 +enum/WUPP: + bit_size: 1 + variants: + - name: High + description: Detection on high level (rising edge) + value: 0 + - name: Low + description: Detection on low level (falling edge) + value: 1 +enum/WUSEL: + bit_size: 2 + variants: + - name: B_0x0 + description: reserved + value: 0 + - name: B_0x1 + description: WKUP3_1 + value: 1 + - name: B_0x2 + description: WKUP3_2 + value: 2 + - name: B_0x3 + description: reserved + value: 3 diff --git a/data/registers/rcc_wba.yaml b/data/registers/rcc_wba.yaml new file mode 100644 index 0000000..6748bfd --- /dev/null +++ b/data/registers/rcc_wba.yaml @@ -0,0 +1,1572 @@ +block/RCC: + description: Reset and clock control + items: + - name: CR + description: RCC clock control register + byte_offset: 0 + fieldset: CR + - name: ICSCR3 + description: RCC internal clock sources calibration register 3 + byte_offset: 16 + fieldset: ICSCR3 + - name: CFGR1 + description: RCC clock configuration register 1 + byte_offset: 28 + fieldset: CFGR1 + - name: CFGR2 + description: RCC clock configuration register 2 + byte_offset: 32 + fieldset: CFGR2 + - name: CFGR3 + description: RCC clock configuration register 3 + byte_offset: 36 + fieldset: CFGR3 + - name: PLL1CFGR + description: RCC PLL1 configuration register + byte_offset: 40 + fieldset: PLL1CFGR + - name: PLL1DIVR + description: RCC PLL1 dividers register + byte_offset: 52 + fieldset: PLL1DIVR + - name: PLL1FRACR + description: RCC PLL1 fractional divider register + byte_offset: 56 + fieldset: PLL1FRACR + - name: CIER + description: RCC clock interrupt enable register + byte_offset: 80 + fieldset: CIER + - name: CIFR + description: RCC clock interrupt flag register + byte_offset: 84 + fieldset: CIFR + - name: CICR + description: RCC clock interrupt clear register + byte_offset: 88 + fieldset: CICR + - name: AHB1RSTR + description: RCC AHB1 peripheral reset register + byte_offset: 96 + fieldset: AHB1RSTR + - name: AHB2RSTR + description: RCC AHB2 peripheral reset register + byte_offset: 100 + fieldset: AHB2RSTR + - name: AHB4RSTR + description: RCC AHB4 peripheral reset register + byte_offset: 108 + fieldset: AHB4RSTR + - name: AHB5RSTR + description: RCC AHB5 peripheral reset register + byte_offset: 112 + fieldset: AHB5RSTR + - name: APB1RSTR1 + description: RCC APB1 peripheral reset register 1 + byte_offset: 116 + fieldset: APB1RSTR1 + - name: APB1RSTR2 + description: RCC APB1 peripheral reset register 2 + byte_offset: 120 + fieldset: APB1RSTR2 + - name: APB2RSTR + description: RCC APB2 peripheral reset register + byte_offset: 124 + fieldset: APB2RSTR + - name: APB7RSTR + description: RCC APB7 peripheral reset register + byte_offset: 128 + fieldset: APB7RSTR + - name: AHB1ENR + description: RCC AHB1 peripheral clock enable register + byte_offset: 136 + fieldset: AHB1ENR + - name: AHB2ENR + description: RCC AHB2 peripheral clock enable register + byte_offset: 140 + fieldset: AHB2ENR + - name: AHB4ENR + description: RCC AHB4 peripheral clock enable register + byte_offset: 148 + fieldset: AHB4ENR + - name: AHB5ENR + description: RCC AHB5 peripheral clock enable register + byte_offset: 152 + fieldset: AHB5ENR + - name: APB1ENR1 + description: RCC APB1 peripheral clock enable register 1 + byte_offset: 156 + fieldset: APB1ENR1 + - name: APB1ENR2 + description: RCC APB1 peripheral clock enable register 2 + byte_offset: 160 + fieldset: APB1ENR2 + - name: APB2ENR + description: RCC APB2 peripheral clock enable register + byte_offset: 164 + fieldset: APB2ENR + - name: APB7ENR + description: RCC APB7 peripheral clock enable register + byte_offset: 168 + fieldset: APB7ENR + - name: AHB1SMENR + description: RCC AHB1 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 176 + fieldset: AHB1SMENR + - name: AHB2SMENR + description: RCC AHB2 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 180 + fieldset: AHB2SMENR + - name: AHB4SMENR + description: RCC AHB4 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 188 + fieldset: AHB4SMENR + - name: AHB5SMENR + description: RCC AHB5 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 192 + fieldset: AHB5SMENR + - name: APB1SMENR1 + description: "RCC APB1 peripheral clocks enable in Sleep and Stop modes\tregister 1" + byte_offset: 196 + fieldset: APB1SMENR1 + - name: APB1SMENR2 + description: "RCC APB1 peripheral clocks enable in Sleep and Stop modes \tregister 2" + byte_offset: 200 + fieldset: APB1SMENR2 + - name: APB2SMENR + description: RCC APB2 peripheral clocks enable in Sleep and Stop modes register + byte_offset: 204 + fieldset: APB2SMENR + - name: APB7SMENR + description: RCC APB7 peripheral clock enable in Sleep and Stop modes register + byte_offset: 208 + fieldset: APB7SMENR + - name: CCIPR1 + description: RCC peripherals independent clock configuration register 1 + byte_offset: 224 + fieldset: CCIPR1 + - name: CCIPR2 + description: RCC peripherals independent clock configuration register 2 + byte_offset: 228 + fieldset: CCIPR2 + - name: CCIPR3 + description: RCC peripherals independent clock configuration register 3 + byte_offset: 232 + fieldset: CCIPR3 + - name: BDCR + description: RCC backup domain control register + byte_offset: 240 + fieldset: BDCR + - name: CSR + description: RCC control/status register + byte_offset: 244 + fieldset: CSR + - name: SECCFGR + description: RCC secure configuration register + byte_offset: 272 + fieldset: SECCFGR + - name: PRIVCFGR + description: RCC privilege configuration register + byte_offset: 276 + fieldset: PRIVCFGR + - name: CFGR4 + description: RCC clock configuration register 2 + byte_offset: 512 + fieldset: CFGR4 + - name: RADIOENR + description: RCC RADIO peripheral clock enable register + byte_offset: 520 + fieldset: RADIOENR + - name: ECSCR1 + description: RCC external clock sources calibration register 1 + byte_offset: 528 + fieldset: ECSCR1 +fieldset/AHB1ENR: + description: RCC AHB1 peripheral clock enable register + fields: + - name: GPDMA1EN + description: "GPDMA1 bus clock enable\r Set and cleared by software.\r Access can be secured by GPDMA1 SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 0 + bit_size: 1 + - name: FLASHEN + description: "FLASH bus clock enable\r Set and cleared by software. This bit can be disabled only when the Flash memory is in power down mode.\r Can only be accessed secured when the Flash security state is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 8 + bit_size: 1 + - name: CRCEN + description: "CRC bus clock enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC CRCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 12 + bit_size: 1 + - name: TSCEN + description: "Touch sensing controller bus clock enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TSCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 16 + bit_size: 1 + - name: RAMCFGEN + description: "RAMCFG bus clock enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC RAMCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 17 + bit_size: 1 + - name: GTZC1EN + description: "GTZC1 bus clock enable \r Set and reset by software.\r Can only be accessed secure when device is secure (TZEN = 1). When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 24 + bit_size: 1 + - name: SRAM1EN + description: "SRAM1 bus clock enable \r Set and reset by software.\r Access can be secured by GTZC_MPCBB1 SECx, INVSECSTATE. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 31 + bit_size: 1 +fieldset/AHB1RSTR: + description: RCC AHB1 peripheral reset register + fields: + - name: GPDMA1RST + description: "GPDMA1 reset\r Set and cleared by software.\r Access can be secured by GPDMA1 SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 0 + bit_size: 1 + - name: CRCRST + description: "CRC reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC CRCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 12 + bit_size: 1 + - name: TSCRST + description: "TSC reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TSCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 16 + bit_size: 1 +fieldset/AHB1SMENR: + description: RCC AHB1 peripheral clocks enable in Sleep and Stop modes register + fields: + - name: GPDMA1SMEN + description: "GPDMA1 bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GPDMA1 SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 0 + bit_size: 1 + - name: FLASHSMEN + description: "FLASH bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Can only be accessed secured when the Flash security state is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 8 + bit_size: 1 + - name: CRCSMEN + description: "CRC bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC CRCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 12 + bit_size: 1 + - name: TSCSMEN + description: "TSC bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TSCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.." + bit_offset: 16 + bit_size: 1 + - name: RAMCFGSMEN + description: "RAMCFG bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC RAMCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 17 + bit_size: 1 + - name: GTZC1SMEN + description: "GTZC1 bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Can only be accessed secure when one device is secure (TZEN = 1). When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 24 + bit_size: 1 + - name: ICACHESMEN + description: "ICACHE bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC ICACHE_REGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.." + bit_offset: 29 + bit_size: 1 + - name: SRAM1SMEN + description: "SRAM1 bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_MPCBB1 SECx, INVSECSTATE. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 31 + bit_size: 1 +fieldset/AHB2ENR: + description: RCC AHB2 peripheral clock enable register + fields: + - name: GPIOAEN + description: "IO port A bus clock enable\r Set and cleared by software.\r Access can be secured by GPIOA SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: "IO port B bus clock enable\r Set and cleared by software.\r Access can be secured by GPIOB SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: "IO port C bus clock enable\r Set and cleared by software.\r Access can be secured by GPIOC SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 2 + bit_size: 1 + - name: GPIOHEN + description: "IO port H bus clock enable\r Set and cleared by software.\r Access can be secured by GPIOH SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 7 + bit_size: 1 + - name: AESEN + description: "AES bus clock enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC AESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 16 + bit_size: 1 + - name: HASHEN + description: "HASH bus clock enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC HASHSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 17 + bit_size: 1 + - name: RNGEN + description: "RNG bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC RNGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 18 + bit_size: 1 + - name: SAESEN + description: "SAES bus clock enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC SAESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 19 + bit_size: 1 + - name: HSEMEN + description: "HSEM bus clock enable\r Set and cleared by software.\r Can only be accessed secure when one or more features in the HSEM is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 20 + bit_size: 1 + - name: PKAEN + description: "PKA bus clock enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC PKASEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 21 + bit_size: 1 + - name: SRAM2EN + description: "SRAM2 bus clock enable\r Set and cleared by software.\r Access can be secured by GTZC_MPCBB2 SECx, INVSECSTATE. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 30 + bit_size: 1 +fieldset/AHB2RSTR: + description: RCC AHB2 peripheral reset register + fields: + - name: GPIOARST + description: "IO port A reset\r Set and cleared by software.\r Access can be secured by GPIOA SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 0 + bit_size: 1 + - name: GPIOBRST + description: "IO port B reset\r Set and cleared by software.\r Access can be secured by GPIOB SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 1 + bit_size: 1 + - name: GPIOCRST + description: "IO port C reset\r Set and cleared by software.\r Access can be secured by GPIOC SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 2 + bit_size: 1 + - name: GPIOHRST + description: "IO port H reset\r Set and cleared by software.\r Access can be secured by GPIOH SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 7 + bit_size: 1 + - name: AESRST + description: "AES hardware accelerator reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC AESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 16 + bit_size: 1 + - name: HASHRST + description: "Hash reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC HASHSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 17 + bit_size: 1 + - name: RNGRST + description: "Random number generator reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC RNGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 18 + bit_size: 1 + - name: SAESRST + description: "SAES hardware accelerator reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC SAESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 19 + bit_size: 1 + - name: HSEMRST + description: "HSEM hardware accelerator reset\r Set and cleared by software.\r Can only be accessed secure when one or more features in the HSEM is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 20 + bit_size: 1 + - name: PKARST + description: "PKA reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC PKASEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 21 + bit_size: 1 +fieldset/AHB2SMENR: + description: RCC AHB2 peripheral clocks enable in Sleep and Stop modes register + fields: + - name: GPIOASMEN + description: "IO port A bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GPIOA SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 0 + bit_size: 1 + - name: GPIOBSMEN + description: "IO port B bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GPIOB SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 1 + bit_size: 1 + - name: GPIOCSMEN + description: "IO port C bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GPIOC SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 2 + bit_size: 1 + - name: GPIOHSMEN + description: "IO port H bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GPIOH SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 7 + bit_size: 1 + - name: AESSMEN + description: "AES bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC AESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 16 + bit_size: 1 + - name: HASHSMEN + description: "HASH bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC HASHSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 17 + bit_size: 1 + - name: RNGSMEN + description: "Random number generator (RNG) bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC RNGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 18 + bit_size: 1 + - name: SAESSMEN + description: "SAES accelerator bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC SAESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 19 + bit_size: 1 + - name: PKASMEN + description: "PKA bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC PKASEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 21 + bit_size: 1 + - name: SRAM2SMEN + description: "SRAM2 bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_MPCBB2 SECx, INVSECSTATE. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 30 + bit_size: 1 +fieldset/AHB4ENR: + description: RCC AHB4 peripheral clock enable register + fields: + - name: PWREN + description: "PWR bus clock enable\r Set and cleared by software.\r Can only be accessed secure when one or more features in the PWR is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 2 + bit_size: 1 + - name: ADC4EN + description: "ADC4 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC ADC4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 5 + bit_size: 1 +fieldset/AHB4RSTR: + description: RCC AHB4 peripheral reset register + fields: + - name: ADC4RST + description: "ADC4 reset\r Set and cleared by software.\r Access can be secred by GTZC_TZSC ADC4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 5 + bit_size: 1 +fieldset/AHB4SMENR: + description: RCC AHB4 peripheral clocks enable in Sleep and Stop modes register + fields: + - name: PWRSMEN + description: "PWR bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Can only be accessed secure when one or more features in the PWR is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 2 + bit_size: 1 + - name: ADC4SMEN + description: "ADC4 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC ADC4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 5 + bit_size: 1 +fieldset/AHB5ENR: + description: RCC AHB5 peripheral clock enable register + fields: + - name: RADIOEN + description: "2.4 GHz RADIO bus clock enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC RADIOSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Before accessing the 2.4 GHz RADIO sleep timers registers the RADIOCLKRDY bit must be checked.\r Note: When RADIOSMEN and STRADIOCLKON are both cleared, RADIOCLKRDY bit must be re-checked when exiting low-power modes (Sleep and Stop)." + bit_offset: 0 + bit_size: 1 +fieldset/AHB5RSTR: + description: RCC AHB5 peripheral reset register + fields: + - name: RADIORST + description: "2.4 GHz RADIO reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC RADIOSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 0 + bit_size: 1 +fieldset/AHB5SMENR: + description: RCC AHB5 peripheral clocks enable in Sleep and Stop modes register + fields: + - name: RADIOSMEN + description: "2.4 GHz RADIO bus clock enable during Sleep and Stop modes when the 2.4 GHz RADIO is active.\r Set and cleared by software.\r Access can be secured by GTZC_TZSC RADIOSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 0 + bit_size: 1 +fieldset/APB1ENR1: + description: RCC APB1 peripheral clock enable register 1 + fields: + - name: TIM2EN + description: "TIM2 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: "TIM3 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 1 + bit_size: 1 + - name: WWDGEN + description: "WWDG bus clock enable\r Set by software to enable the window watchdog bus clock. Reset by hardware system reset.\r This bit can also be set by hardware if the WWDG_SW option bit is reset.\r Access can be secured by GTZC_TZSC WWDGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 11 + bit_size: 1 + - name: USART2EN + description: "USART2 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC USART2SEC When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.." + bit_offset: 17 + bit_size: 1 + - name: I2C1EN + description: "I2C1 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 21 + bit_size: 1 +fieldset/APB1ENR2: + description: RCC APB1 peripheral clock enable register 2 + fields: + - name: LPTIM2EN + description: "LPTIM2 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 5 + bit_size: 1 +fieldset/APB1RSTR1: + description: RCC APB1 peripheral reset register 1 + fields: + - name: TIM2RST + description: "TIM2 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: "TIM3 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 1 + bit_size: 1 + - name: USART2RST + description: "USART2 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC UART2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 17 + bit_size: 1 + - name: I2C1RST + description: "I2C1 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 21 + bit_size: 1 +fieldset/APB1RSTR2: + description: RCC APB1 peripheral reset register 2 + fields: + - name: LPTIM2RST + description: "LPTIM2 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 5 + bit_size: 1 +fieldset/APB1SMENR1: + description: "RCC APB1 peripheral clocks enable in Sleep and Stop modes\tregister 1" + fields: + - name: TIM2SMEN + description: "TIM2 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 0 + bit_size: 1 + - name: TIM3SMEN + description: "TIM3 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 1 + bit_size: 1 + - name: WWDGSMEN + description: "Window watchdog bus clock enable during Sleep and Stop modes\r Set and cleared by software. This bit is forced to 1 by hardware when the hardware WWDG option is activated.\r Access can be secured by GTZC_TZSC WWDGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 11 + bit_size: 1 + - name: USART2SMEN + description: "USART2 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC USART2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 17 + bit_size: 1 + - name: I2C1SMEN + description: "I2C1 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 21 + bit_size: 1 +fieldset/APB1SMENR2: + description: "RCC APB1 peripheral clocks enable in Sleep and Stop modes \tregister 2" + fields: + - name: LPTIM2SMEN + description: "LPTIM2 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 5 + bit_size: 1 +fieldset/APB2ENR: + description: RCC APB2 peripheral clock enable register + fields: + - name: TIM1EN + description: "TIM1 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: "SPI1 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC SPI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 12 + bit_size: 1 + - name: USART1EN + description: "USART1bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC USART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 14 + bit_size: 1 + - name: TIM16EN + description: "TIM16 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM16SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: "TIM17 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM17SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 18 + bit_size: 1 +fieldset/APB2RSTR: + description: RCC APB2 peripheral reset register + fields: + - name: TIM1RST + description: "TIM1 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: "SPI1 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC SPI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 12 + bit_size: 1 + - name: USART1RST + description: "USART1 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC USART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 14 + bit_size: 1 + - name: TIM16RST + description: "TIM16 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM16SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: "TIM17 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM17SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 18 + bit_size: 1 +fieldset/APB2SMENR: + description: RCC APB2 peripheral clocks enable in Sleep and Stop modes register + fields: + - name: TIM1SMEN + description: "TIM1 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 11 + bit_size: 1 + - name: SPI1SMEN + description: "SPI1 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC SPI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 12 + bit_size: 1 + - name: USART1SMEN + description: "USART1 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC USART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 14 + bit_size: 1 + - name: TIM16SMEN + description: "TIM16 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM16SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 17 + bit_size: 1 + - name: TIM17SMEN + description: "TIM17 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM17SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 18 + bit_size: 1 +fieldset/APB7ENR: + description: RCC APB7 peripheral clock enable register + fields: + - name: SYSCFGEN + description: "SYSCFG bus clock enable\r Set and cleared by software.\r Access can be secured by SYSCFG SYSCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 1 + bit_size: 1 + - name: SPI3EN + description: "SPI3 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC SPI3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 5 + bit_size: 1 + - name: LPUART1EN + description: "LPUART1 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC LPUART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 6 + bit_size: 1 + - name: I2C3EN + description: "I2C3 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 7 + bit_size: 1 + - name: LPTIM1EN + description: "LPTIM1 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 11 + bit_size: 1 + - name: RTCAPBEN + description: "RTC and TAMP bus clock enable\r Set and cleared by software.\r Can only be accessed secure when one or more features in the RTC or TAMP is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 21 + bit_size: 1 +fieldset/APB7RSTR: + description: RCC APB7 peripheral reset register + fields: + - name: SYSCFGRST + description: "SYSCFG reset\r Set and cleared by software.\r Access can be secured by SYSCFG SYSCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 1 + bit_size: 1 + - name: SPI3RST + description: "SPI3 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC SPI3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 5 + bit_size: 1 + - name: LPUART1RST + description: "LPUART1 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC LPUART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 6 + bit_size: 1 + - name: I2C3RST + description: "I2C3 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 7 + bit_size: 1 + - name: LPTIM1RST + description: "LPTIM1 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 11 + bit_size: 1 +fieldset/APB7SMENR: + description: RCC APB7 peripheral clock enable in Sleep and Stop modes register + fields: + - name: SYSCFGSMEN + description: "SYSCFG bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by SYSCFG SYSCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 1 + bit_size: 1 + - name: SPI3SMEN + description: "SPI3 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC SPI3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 5 + bit_size: 1 + - name: LPUART1SMEN + description: "LPUART1 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC LPUART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 6 + bit_size: 1 + - name: I2C3SMEN + description: "I2C3 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 7 + bit_size: 1 + - name: LPTIM1SMEN + description: "LPTIM1 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 11 + bit_size: 1 + - name: RTCAPBSMEN + description: "RTC and TAMP APB clock enable during Sleep and Stop modes\r Set and cleared by software.\r Can only be accessed secure when one or more features in the RTC or TAMP is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes." + bit_offset: 21 + bit_size: 1 +fieldset/BDCR: + description: RCC backup domain control register + fields: + - name: LSEON + description: "LSE oscillator enable\r Set and cleared by software.\r Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: "LSE oscillator ready\r Set and cleared by hardware to indicate when the external 32�kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles.\r Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: "LSE oscillator bypass\r Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32�kHz oscillator is disabled (LSEON = 0 and LSERDY = 0).\r Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 2 + bit_size: 1 + - name: LSEDRV + description: "LSE oscillator drive capability\r Set by software to modulate the drive capability of the LSE oscillator. LSEDRV must be programmed to a different value than 0 before enabling the LSE oscillator in ‘Xtal’ mode.\r Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The oscillator is in ‘Xtal mode’ when it is not in bypass mode." + bit_offset: 3 + bit_size: 2 + enum: LSEDRV + - name: LSECSSON + description: "Low speed external clock security enable\r Set by software to enable the LSECSS. LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware) and after the RTCSEL bit is selected.\r Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD�=�1). In that case, the software must disable the LSECSSON bit.\r Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 5 + bit_size: 1 + - name: LSECSSD + description: "Low speed external clock security, LSE failure Detection\r Set by hardware to indicate when a failure is detected by the LSECCS on the external 32�kHz oscillator.\r Reset when LSCSSON bit is cleared.\r Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 6 + bit_size: 1 + - name: LSESYSEN + description: "LSE system clock (LSESYS) enable\r Set by software to enable the LSE system clock generated by RCC. The lsesys clock is used for peripherals (USART, LPUART, LPTIM, RNG, 2.4 GHz RADIO) and functions (LSCO, MCO, TIM triggers, LPTIM trigger) excluding the RTC, TAMP and LSECSS.\r Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 7 + bit_size: 1 + - name: RTCSEL + description: "RTC and TAMP kernel clock source enable and selection\r Set by software to enable and select the clock source for the RTC.\r Can only be accessed secure when one or more features in the RTC or TAMP is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: LSESYSRDY + description: "LSE system clock (LSESYS) ready\r Set and cleared by hardware to indicate when the LSE system clock is stable.When the LSESYSEN bit is set, the LSESYSRDY flag is set after two LSE clock cycles.\r The LSE clock must be already enabled and stable (LSEON and LSERDY are set). \r When the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles.\r Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 11 + bit_size: 1 + - name: LSEGFON + description: "LSE clock glitch filter enable\r Set and cleared by hardware to enable the LSE glitch filter. This bit can be written only when the LSE is disabled (LSEON = 0 and LSERDY = 0).\r Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 12 + bit_size: 1 + - name: LSETRIM + description: "LSE trimming\r These bits are initialized at startup and after OBL_LAUNCH with SBF cleared with the factory-programmed LSE calibration value.\r Set and cleared by software. These bits must be modified only once after a BOR reset or an OBL_LAUNCH and before enabling LSE with LSEON (when both LSEON = 0 and LSERDY�= 0).\r Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: OBL_LAUNCH of this field occurs only when SBF is cleared and must then only be started by software when LSE oscillator is disabled, LSEON = 0 and LSERDY = 0." + bit_offset: 13 + bit_size: 2 + enum: LSETRIM + - name: BDRST + description: "Backup domain software reset\r Set and cleared by software.\r Can only be accessed secure when one or more features in the RTC or TAMP is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 16 + bit_size: 1 + - name: RADIOSTSEL + description: "2.4 GHz RADIO sleep timer kernel clock enable and selection\r Set and cleared by software.\r Access can be secured by GTZC_TZSC RADIOSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 18 + bit_size: 2 + enum: RADIOSTSEL + - name: LSCOEN + description: "Low-speed clock output (LSCO) enable\r Set and cleared by software.\r Access can be secured by RCC LSISEC and/or RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 24 + bit_size: 1 + - name: LSCOSEL + description: "Low-speed clock output selection\r Set and cleared by software.\r Access can be secured by RCC LSISEC and/or RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 25 + bit_size: 1 + enum: LSCOSEL + - name: LSI1ON + description: "LSI1 oscillator enable\r Set and cleared by software.\r Access can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 26 + bit_size: 1 + - name: LSI1RDY + description: "LSI1 oscillator ready\r Set and cleared by hardware to indicate when the LSI1 oscillator is stable. After the LSI1ON bit is cleared, LSI1RDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI1 is used by IWDG or RTC, even if LSI1ON = 0.\r Access can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 27 + bit_size: 1 + - name: LSI1PREDIV + description: "LSI1 Low-speed clock divider configuration\r Set and cleared by software to enable the LSI1 division. This bit can be written only when the LSI1 is disabled (LSI1ON = 0 and LSI1RDY = 0). The LSI1PREDIV cannot be changed if the LSI1 is used by the IWDG or by the RTC.\r Access can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 28 + bit_size: 1 + enum: LSIPREDIV +fieldset/CCIPR1: + description: RCC peripherals independent clock configuration register 1 + fields: + - name: USART1SEL + description: "USART1 kernel clock source selection\r This bits are used to select the USART1 kernel clock source.\r Access can be secured by GTZC_TZSC USART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The USART1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE." + bit_offset: 0 + bit_size: 2 + enum: USARTSEL + - name: USART2SEL + description: "USART2 kernel clock source selection\r This bits are used to select the USART2 kernel clock source.\r Access can be secured by GTZC_TZSC USART2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The USART2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE." + bit_offset: 2 + bit_size: 2 + enum: USARTSEL + - name: I2C1SEL + description: "I2C1 kernel clock source selection\r These bits are used to select the I2C1 kernel clock source.\r Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The I2C1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16." + bit_offset: 10 + bit_size: 2 + enum: ICSEL + - name: LPTIM2SEL + description: "Low-power timer 2 kernel clock source selection\r These bits are used to select the LPTIM2 kernel clock source.\r Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The LPTIM2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is LSI, LSE or HSI16 if HSIKERON = 1." + bit_offset: 18 + bit_size: 2 + enum: LPTIMSEL + - name: SPI1SEL + description: "SPI1 kernel clock source selection\r These bits are used to select the SPI1 kernel clock source.\r Access can be secured by GTZC_TZSC SPI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The SPI1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16." + bit_offset: 20 + bit_size: 2 + enum: SPISEL + - name: SYSTICKSEL + description: "SysTick clock source selection\r These bits are used to select the SysTick clock source.\r Access can be secured by RCC SYSCLKSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: When LSE or LSI is selected, the AHB frequency must be at least four times higher than the LSI or LSE frequency. In addition, a jitter up to one hclk1 cycle is introduced, due to the LSE or LSI sampling with hclk1 in the SysTick circuitry." + bit_offset: 22 + bit_size: 2 + enum: SYSTICKSEL + - name: TIMICSEL + description: "Clocks sources for TIM16,TIM17 and LPTIM2 internal input capture \r When the TIMICSEL bit is set, the TIM16, TIM17 and LPTIM2 internal input capture can be connected to HSI16/256. \r When TIMICSEL is cleared, the HSI16, clock sources cannot be selected as TIM16, TIM17 or LPTIM2 internal input capture.\r Access can be secured by GTZC_TZSC TIM16SEC, TIM17SEC, or LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The clock division must be disabled (TIMICSEL configured to 0) before selecting or changing a clock sources division." + bit_offset: 31 + bit_size: 1 + enum: TIMICSEL +fieldset/CCIPR2: + description: RCC peripherals independent clock configuration register 2 + fields: + - name: RNGSEL + description: "RNGSEL kernel clock source selection\r These bits allow to select the RNG kernel clock source.\r Access can be secured by GTZC_TZSC RNGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 12 + bit_size: 2 + enum: RNGSEL +fieldset/CCIPR3: + description: RCC peripherals independent clock configuration register 3 + fields: + - name: LPUART1SEL + description: "LPUART1 kernel clock source selection\r These bits are used to select the LPUART1 kernel clock source.\r Access can be secured by GTZC_TZSC LPUART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The LPUART1 is functional in Stop modes only when the kernel clock is HSI16 or LSE." + bit_offset: 0 + bit_size: 2 + enum: LPUARTSEL + - name: SPI3SEL + description: "SPI3 kernel clock source selection\r These bits are used to select the SPI3 kernel clock source.\r Access can be secured by GTZC_TZSC SPI3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The SPI3 is functional in Stop modes only when the kernel clock is HSI16." + bit_offset: 3 + bit_size: 2 + enum: SPISEL + - name: I2C3SEL + description: "I2C3 kernel clock source selection\r These bits are used to select the I2C3 kernel clock source.\r Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The I2C3 is functional in Stop modes only when the kernel clock is HSI16" + bit_offset: 6 + bit_size: 2 + enum: ICSEL + - name: LPTIM1SEL + description: "LPTIM1 kernel clock source selection\r These bits are used to select the LPTIM1 kernel clock source.\r Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The LPTIM1 is functional in Stop modes only when the kernel clock is LSI, LSE, HSI16 with HSIKERON = 1." + bit_offset: 10 + bit_size: 2 + enum: LPTIMSEL + - name: ADCSEL + description: "ADC4 kernel clock source selection\r These bits are used to select the ADC4 kernel clock source.\r Access can be secured by GTZC_TZSC ADC4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r others: reserved\r Note: The ADC4 is functional in Stop modes only when the kernel clock is HSI16." + bit_offset: 12 + bit_size: 3 + enum: ADCSEL +fieldset/CFGR1: + description: RCC clock configuration register 1 + fields: + - name: SW + description: "system clock switch\r Set and cleared by software to select system clock source (SYSCLK).\r Cleared by hardware when entering Stop and Standby modes\r When selecting HSE32 directly or indirectly as system clock and HSE32 oscillator clock security fails, cleared by hardware." + bit_offset: 0 + bit_size: 2 + enum: SW + - name: SWS + description: "system clock switch status\r Set and cleared by hardware to indicate which clock source is used as system clock." + bit_offset: 2 + bit_size: 2 + enum: SW + - name: MCOSEL + description: "microcontroller clock output\r Set and cleared by software.\r others: reserved\r Note: This clock output may have some truncated cycles at startup or during MCO clock source switching." + bit_offset: 24 + bit_size: 4 + enum: MCOSEL + - name: MCOPRE + description: "microcontroller clock output prescaler\r Set and cleared by software.\r It is highly recommended to change this prescaler before MCO output is enabled.\r others: not allowed" + bit_offset: 28 + bit_size: 3 + enum: MCOPRE +fieldset/CFGR2: + description: RCC clock configuration register 2 + fields: + - name: HPRE + description: "AHB1, AHB2 and AHB4 prescaler\r Set and cleared by software to control the division factor of the AHB1, AHB2 and AHB4 clock (hclk1).\r The software must limit the incremental frequency step by setting these bits correctly to ensure that the hclk1 maximum incremental frequency step does not exceed the maximum allowed incremental frequency step (for more details, refer to Table�99: SYSCLK and bus maximum frequency). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account.\r 0xx: hclk1 = SYSCLK not divided" + bit_offset: 0 + bit_size: 3 + enum: HPRE + - name: PPRE1 + description: "APB1 prescaler\r Set and cleared by software to control the division factor of the APB1 clock (pclk1).\r 0xx: pclk1 = hclk1 not divided" + bit_offset: 4 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: "APB2 prescaler\r Set and cleared by software to control the division factor of the APB2 clock (pclk2).\r 0xx: pclk2 = hclk1 not divided" + bit_offset: 8 + bit_size: 3 + enum: PPRE +fieldset/CFGR3: + description: RCC clock configuration register 3 + fields: + - name: PPRE7 + description: "APB7 prescaler\r Set and cleared by software to control the division factor of the APB7 clock (pclk7).\r 0xx: hclk1 not divided" + bit_offset: 4 + bit_size: 3 + enum: PPRE +fieldset/CFGR4: + description: RCC clock configuration register 2 + fields: + - name: HPRE5 + description: "AHB5 prescaler when SWS select PLL1\r Set and cleared by software to control the division factor of the AHB5 clock (hclk5).\r Must not be changed when SYSCLK source indicated by SWS is PLL1.\r When SYSCLK source indicated by SWS is not PLL1: HPRE5 is not taken into account.\r When SYSCLK source indicated by SWS is PLL1: HPRE5 is taken into account, from the moment the system clock switch occurs\r Depending on the device voltage range, the software must set these bits correctly to ensure that the AHB5 frequency does not exceed the maximum allowed frequency (for more details, refer to Table�99: SYSCLK and bus maximum frequency). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account.\r 0xx: hclk5 = SYSCLK not divided" + bit_offset: 0 + bit_size: 3 + enum: HPRE5 + - name: HDIV5 + description: "AHB5 divider when SWS select HSI16 or HSE32\r Set and reset by software.\r Set to 1 by hardware when entering Stop 1 mode.\r When SYSCLK source indicated by SWS is HSI16 or HSE32: HDIV5 is taken into account\r When SYSCLK source indicated by SWS is PLL1: HDIV5 is taken not taken into account\r Depending on the device voltage range, the software must set this bit correctly to ensure that the AHB5 frequency does not exceed the maximum allowed frequency (for more details, refer to Table�99). After a write operation to this bit and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account." + bit_offset: 4 + bit_size: 1 + enum: HDIV5 +fieldset/CICR: + description: RCC clock interrupt clear register + fields: + - name: LSI1RDYC + description: "LSI1 ready interrupt clear\r Writing this bit to 1 clears the LSI1RDYF flag. Writing 0 has no effect.\r Access to the bit can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 0 + bit_size: 1 + - name: LSERDYC + description: "LSE ready interrupt clear\r Writing this bit to 1 clears the LSERDYF flag. Writing 0 has no effect.\r Access to the bit can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 1 + bit_size: 1 + - name: HSIRDYC + description: "HSI16 ready interrupt clear\r Writing this bit to 1 clears the HSIRDYF flag. Writing 0 has no effect.\\\r Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 3 + bit_size: 1 + - name: HSERDYC + description: "HSE32 ready interrupt clear\r Writing this bit to 1 clears the HSERDYF flag. Writing 0 has no effect.\r Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 4 + bit_size: 1 + - name: PLLRDYC + description: "PLL1 ready interrupt clear\r Writing this bit to 1 clears the PLL1RDYF flag. Writing 0 has no effect.\r Access to the bit can be secured by RCC PLL1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 6 + bit_size: 1 + - name: HSECSSC + description: "High speed external clock security system interrupt clear\r Writing this bit to 1 clears the HSECSSF flag. Writing 0 has no effect.\r Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 10 + bit_size: 1 +fieldset/CIER: + description: RCC clock interrupt enable register + fields: + - name: LSI1RDYIE + description: "LSI1 ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the LSI1 oscillator stabilization.\r Access to the bit can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 0 + bit_size: 1 + - name: LSERDYIE + description: "LSE ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization.\r Access to the bit can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 1 + bit_size: 1 + - name: HSIRDYIE + description: "HSI16 ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization.\r Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 3 + bit_size: 1 + - name: HSERDYIE + description: "HSE32 ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSE32 oscillator stabilization.\r Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 4 + bit_size: 1 + - name: PLLRDYIE + description: "PLL1 ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by PLL1 lock.\r Access to the bit can be secured by RCC PLL1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 6 + bit_size: 1 +fieldset/CIFR: + description: RCC clock interrupt flag register + fields: + - name: LSI1RDYF + description: "LSI1 ready interrupt flag\r Set by hardware when the LSI1 clock becomes stable and LSI1RDYIE is set.\r Cleared by software setting the LSI1RDYC bit.\r Access to the bit can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: "LSE ready interrupt flag\r Set by hardware when the LSE clock becomes stable and LSERDYIE is set.\r Cleared by software setting the LSERDYC bit.\r Access to the bit can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 1 + bit_size: 1 + - name: HSIRDYF + description: "HSI16 ready interrupt flag\r Set by hardware when the HSI16 clock becomes stable and HSIRDYIE is set in a response to setting the HSION (see CR). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated.\r Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Cleared by software setting the HSIRDYC bit." + bit_offset: 3 + bit_size: 1 + - name: HSERDYF + description: "HSE32 ready interrupt flag\r Set by hardware when the HSE32 clock becomes stable and HSERDYIE is set.\r Cleared by software setting the HSERDYC bit.\r Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 4 + bit_size: 1 + - name: PLLRDYF + description: "PLL1 ready interrupt flag\r Set by hardware when the PLL1 locks and PLL1RDYIE is set.\r Cleared by software setting the PLL1RDYC bit.\r Access to the bit can be secured by RCC PLL1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 6 + bit_size: 1 + - name: HSECSSF + description: "HSE32 clock security system interrupt flag\r Set by hardware when a clock security failure is detected in the HSE32 oscillator.\r Cleared by software setting the HSECSSC bit.\r Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 10 + bit_size: 1 +fieldset/CR: + description: RCC clock control register + fields: + - name: HSION + description: "HSI16 clock enable\r Set and cleared by software.\r Cleared by hardware when entering Stop and Standby modes. \r Set by hardware to force the HSI16 oscillator on when exiting Stop and Standby modes.\r Set by hardware to force the HSI16 oscillator on in case of clock security failure of the HSE32 crystal oscillator.\r This bit is set by hardware if the HSI16 is used directly or indirectly as system clock.\r Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 8 + bit_size: 1 + - name: HSIKERON + description: "HSI16 enable for some peripheral kernels\r Set and cleared by software to force HSI16 oscillator on even in Stop modes. \r Keeping the HSI16 oscillator on in Stop modes allows the communication speed not to be reduced by the HSI16 oscillator startup time. This bit has no effect on register bit HSION value.\r Cleared by hardware when entering Standby modes. \r Refer to Peripherals clock gating and autonomous mode for more details.\r Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 9 + bit_size: 1 + - name: HSIRDY + description: "HSI16 clock ready flag\r Set by hardware to indicate that HSI16 oscillator is stable. This bit is set only when HSI16 is enabled by software by setting HSION.\r Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: Once the HSION bit is cleared, HSIRDY goes low after six HSI16 clock cycles." + bit_offset: 10 + bit_size: 1 + - name: HSEON + description: "HSE32 clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSE32 clock for the CPU when entering Stop and Standby modes and on a HSECSS failure.\r When the HSE32 is used as 2.4 GHz RADIO kernel clock, enabled by RADIOEN and RADIOSMEN and the 2.4 GHz RADIO is active, HSEON is not be cleared when entering low power mode. In this case only Stop 0 mode is entered as low power mode.\r This bit cannot be reset if the HSE32 oscillator is used directly or indirectly as the system clock.\r Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: "HSE32 clock ready flag\r Set by hardware to indicate that the HSE32 oscillator is stable. This bit is set both when HSE32 is enabled by software by setting HSEON and when requested as kernel clock by the 2.4 GHz RADIO.\r Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 17 + bit_size: 1 + - name: HSECSSON + description: "HSE32 clock security system enable\r Set by software to enable the HSE32 clock security system. When HSECSSON is set, the clock detector is enabled by hardware when the HSE32 oscillator is ready and disabled by hardware if a HSE32 clock failure is detected. This bit is set only and is cleared by reset.\r Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 19 + bit_size: 1 + - name: HSEPRE + description: "HSE32 clock for SYSCLK prescaler\r Set and cleared by software to control the division factor of the HSE32 clock for SYSCLK.\r Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 20 + bit_size: 1 + enum: HSEPRE + - name: PLLON + description: "PLL1 enable\r Set and cleared by software to enable the main PLL.\r Cleared by hardware when entering Stop or Standby modes and when PLL1 on HSE32 is selected as sysclk, on a HSECSS failure.\r This bit cannot be reset if the PLL1 clock is used as the system clock.\r Access to the bit can be secured by RCC PLL1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: "PLL1 clock ready flag\r Set by hardware to indicate that the PLL1 is locked.\r Access to the bit can be secured by RCC PLL1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 25 + bit_size: 1 +fieldset/CSR: + description: RCC control/status register + fields: + - name: RMVF + description: "Remove reset flag\r Set by software to clear the reset flags.\r Access can be secured by RCC RMVFSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + bit_offset: 23 + bit_size: 1 + - name: OBLRSTF + description: "Option byte loader reset flag\r Set by hardware when a reset from the option byte loading occurs.\r Cleared by writing to the RMVF bit." + bit_offset: 25 + bit_size: 1 + - name: PINRSTF + description: "NRST pin reset flag\r Set by hardware when a reset from the NRST pin occurs.\r Cleared by writing to the RMVF bit." + bit_offset: 26 + bit_size: 1 + - name: BORRSTF + description: "BOR flag\r Set by hardware when a BOR occurs.\r Cleared by writing to the RMVF bit." + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: "Software reset flag\r Set by hardware when a software reset occurs.\r Cleared by writing to the RMVF bit." + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: "Independent watchdog reset flag\r Set by hardware when an independent watchdog reset domain occurs.\r Cleared by writing to the RMVF bit." + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: "Window watchdog reset flag\r Set by hardware when a window watchdog reset occurs.\r Cleared by writing to the RMVF bit." + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: "Low-power reset flag\r Set by hardware when a reset occurs due to illegal Stop and Standby modes entry.\r Cleared by writing to the RMVF bit." + bit_offset: 31 + bit_size: 1 +fieldset/ECSCR1: + description: RCC external clock sources calibration register 1 + fields: + - name: HSETRIM + description: "HSE32 clock trimming \r These bits provide user-programmable capacitor trimming value. It can be programmed to adjust the HSE32 oscillator frequency." + bit_offset: 16 + bit_size: 6 +fieldset/ICSCR3: + description: RCC internal clock sources calibration register 3 + fields: + - name: HSICAL + description: "HSI16 clock calibration\r These bits are initialized at startup with the factory-programmed HSI16 calibration value. When HSITRIM[4:0] is written, HSICAL[11:0] is updated with the sum of HSITRIM[4:0] and the initial factory trim value." + bit_offset: 0 + bit_size: 12 + - name: HSITRIM + description: "HSI16 clock trimming \r These bits provide an additional user-programmable trimming value that is added to the HSICAL[11:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the HSI16." + bit_offset: 16 + bit_size: 5 +fieldset/PLL1CFGR: + description: RCC PLL1 configuration register + fields: + - name: PLLSRC + description: "PLL1 entry clock source\r Set and cleared by software to select PLL1 clock source. These bits can be written only when the PLL1 is disabled.\r Cleared by hardware when entering Stop or Standby modes. \r Note: In order to save power, when no PLL1 clock is used, the value of PLL1SRC must be 0." + bit_offset: 0 + bit_size: 2 + enum: PLLSRC + - name: PLLRGE + description: "PLL1 input frequency range\r Set and reset by software to select the proper reference frequency range used for PLL1.\r This bit must be written before enabling the PLL1.\r 00-01-10: PLL1 input (ref1_ck) clock range frequency between 4 and 8 MHz" + bit_offset: 2 + bit_size: 2 + enum: PLLRGE + - name: PLLFRACEN + description: "PLL1 fractional latch enable\r Set and reset by software to latch the content of PLL1FRACN into the ΣΔ modulator.\r In order to latch the PLL1FRACN value into the ΣΔ modulator, PLL1FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL1FRACN into the modulator (see PLL1 initialization phase for details)." + bit_offset: 4 + bit_size: 1 + - name: PLLM + description: "Prescaler for PLL1\r Set and cleared by software to configure the prescaler of the PLL1. The VCO1 input frequency is PLL1 input clock frequency/PLL1M.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). \r ..." + bit_offset: 8 + bit_size: 3 + - name: PLLPEN + description: "PLL1 DIVP divider output enable\r Set and reset by software to enable the pll1pclk output of the PLL1.\r To save power, PLL1PEN and PLL1P bits must be set to 0 when the pll1pclk is not used. \r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)." + bit_offset: 16 + bit_size: 1 + - name: PLLQEN + description: "PLL1 DIVQ divider output enable\r Set and reset by software to enable the pll1qclk output of the PLL1.\r To save power, PLL1QEN and PLL1Q bits must be set to 0 when the pll1qclk is not used. \r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)." + bit_offset: 17 + bit_size: 1 + - name: PLLREN + description: "PLL1 DIVR divider output enable\r Set and cleared by software to enable the pll1rclk output of the PLL1.\r To save power, PLL1REN and PLL1R bits must be set to 0 when the pll1rclk is not used.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)." + bit_offset: 18 + bit_size: 1 + - name: PLLRCLKPRE + description: "pll1rclk clock for SYSCLK prescaler division enable\r Set and cleared by software to control the division of the pll1rclk clock for SYSCLK." + bit_offset: 20 + bit_size: 1 + enum: PLLRCLKPRE + - name: PLLRCLKPRESTEP + description: "pll1rclk clock for SYSCLK prescaler division step selection\r Set and cleared by software to control the division step of the pll1rclk clock for SYSCLK." + bit_offset: 21 + bit_size: 1 + enum: PLLRCLKPRESTEP + - name: PLLRCLKPRERDY + description: "pll1rclkpre not divided ready.\r Set by hardware after PLL1RCLKPRE has been set from divided to not divide, to indicate that the pll1rclk not divided is available on sysclkpre." + bit_offset: 22 + bit_size: 1 +fieldset/PLL1DIVR: + description: RCC PLL1 dividers register + fields: + - name: PLLN + description: "Multiplication factor for PLL1 VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ...\r ...\r others: reserved\r VCO output frequency = Fref1_ck x multiplication factor for PLL1 VCO, when fractional value 0 has been loaded into PLL1FRACN, with: \r Multiplication factor for PLL1 VCO between 4 and 512\r input frequency Fref1_ck between 4 and 16�MHz" + bit_offset: 0 + bit_size: 9 + - name: PLLP + description: "PLL1 DIVP division factor\r Set and reset by software to control the frequency of the pll1pclk clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r Note that odd division factors are not allowed.\r ..." + bit_offset: 9 + bit_size: 7 + - name: PLLQ + description: "PLL1 DIVQ division factor\r Set and reset by software to control the frequency of the PLl1QCLK clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..." + bit_offset: 16 + bit_size: 7 + - name: PLLR + description: "PLL1 DIVR division factor\r Set and reset by software to control the frequency of the pll1rclk clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..." + bit_offset: 24 + bit_size: 7 +fieldset/PLL1FRACR: + description: RCC PLL1 fractional divider register + fields: + - name: PLLFRACN + description: "Fractional part of the multiplication factor for PLL1 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO.\r These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO.\r VCO output frequency = Fref1_ck x [multiplication factor for PLL1 VCO + (PLL1FRACN / 213)], with: \r Multiplication factor for PLL1 VCO must be between 4 and 512.\r PLL1FRACN can be between 0 and 213- 1.\r The input frequency Fref1_ck must be between 4 and 16 MHz. \r To change the used fractional value on-the-fly even if the PLL1 is enabled, the application must proceed as follows:\r Set the bit PLL1FRACEN to 0. \r Write the new fractional value into PLL1FRACN. \r Set the bit PLL1FRACEN to 1." + bit_offset: 3 + bit_size: 13 +fieldset/PRIVCFGR: + description: RCC privilege configuration register + fields: + - name: SPRIV + description: "RCC secure functions privilege configuration\r Set and reset by software.\r This bit can be written only by a secure privileged access." + bit_offset: 0 + bit_size: 1 + - name: NSPRIV + description: "RCC non-secure functions privilege configuration\r Set and reset by software.\r This bit can be written only by privileged access, secure or non-secure." + bit_offset: 1 + bit_size: 1 +fieldset/RADIOENR: + description: RCC RADIO peripheral clock enable register + fields: + - name: BBCLKEN + description: "2.4 GHz RADIO baseband kernel clock (aclk) enable\r Set and cleared by software.\r Note: The HSE32 oscillator needs to be enabled by either HSEON or STRADIOCLKON." + bit_offset: 1 + bit_size: 1 + - name: STRADIOCLKON + description: "2.4 GHz RADIO bus clock enable and HSE32 oscillator enable by 2.4 GHz RADIO sleep timer wakeup event\r Set by hardware on a 2.4 GHz RADIO sleep timer wakeup event.\r Cleared by software writing zero to this bit.\r Note: Before accessing the 2.4 GHz RADIO registers the RADIOCLKRDY bit must be checked." + bit_offset: 16 + bit_size: 1 + - name: RADIOCLKRDY + description: "2.4 GHz RADIO bus clock ready.\r Set and cleared by hardware to indicate that the 2.4 GHz RADIO bus clock is ready and the 2.4 GHz RADIO registers can be accessed.\r Note: Once both RADIOEN and STRADIOCLKON are cleared, RADIOCLKRDY goes low after three hclk5 clock cycles." + bit_offset: 17 + bit_size: 1 +fieldset/SECCFGR: + description: RCC secure configuration register + fields: + - name: HSISEC + description: "HSI16 clock configuration and status bits security\r Set and reset by software." + bit_offset: 0 + bit_size: 1 + - name: HSESEC + description: "HSE32 clock configuration bits, status bits and HSECSS security\r Set and reset by software." + bit_offset: 1 + bit_size: 1 + - name: LSISEC + description: "LSI clock configuration and status bits security\r Set and reset by software." + bit_offset: 3 + bit_size: 1 + - name: LSESEC + description: "LSE clock configuration and status bits security\r Set and reset by software." + bit_offset: 4 + bit_size: 1 + - name: SYSCLKSEC + description: "SYSCLK selection, clock output on MCO configuration security\r Set and reset by software." + bit_offset: 5 + bit_size: 1 + - name: PRESCSEC + description: "AHBx/APBx prescaler configuration bits security\r Set and reset by software." + bit_offset: 6 + bit_size: 1 + - name: PLLSEC + description: "PLL1 clock configuration and status bits security\r Set and reset by software." + bit_offset: 7 + bit_size: 1 + - name: RMVFSEC + description: "Remove reset flag security\r Set and reset by software." + bit_offset: 12 + bit_size: 1 +enum/ADCSEL: + bit_size: 3 + variants: + - name: HCLK1 + description: hclk1 clock selected + value: 0 + - name: SYSCLK + description: SYSCLK selected + value: 1 + - name: PLL1_P + description: pll1pclk selected + value: 2 + - name: HSE32 + description: HSE32 clock selected + value: 3 + - name: HSI16 + description: HSI16 clock selected + value: 4 +enum/HDIV5: + bit_size: 1 + variants: + - name: Div1 + description: hclk5 = SYSCLK not divided + value: 0 + - name: Div2 + description: hclk5 = SYSCLK divided by 2 + value: 1 +enum/HPRE: + bit_size: 3 + variants: + - name: Div1 + description: DCLK not divided + value: 0 + - name: Div2 + description: hclk = SYSCLK divided by 2 + value: 4 + - name: Div4 + description: hclk = SYSCLK divided by 4 + value: 5 + - name: Div8 + description: hclk = SYSCLK divided by 8 + value: 6 + - name: Div16 + description: hclk = SYSCLK divided by 16 + value: 7 +enum/HPRE5: + bit_size: 3 + variants: + - name: Div1 + description: DCLK not divided + value: 0 + - name: Div2 + description: hclk5 = SYSCLK divided by 2 + value: 4 + - name: Div3 + description: hclk5 = SYSCLK divided by 3 + value: 5 + - name: Div4 + description: hclk5 = SYSCLK divided by 4 + value: 6 + - name: Div6 + description: hclk5 = SYSCLK divided by 6 + value: 7 +enum/HSEPRE: + bit_size: 1 + variants: + - name: Div1 + description: HSE32 not divided, SYSCLK = HSE32 + value: 0 + - name: Div2 + description: HSE32 divided, SYSCLK = HSE32/2 + value: 1 +enum/ICSEL: + bit_size: 2 + variants: + - name: PCLK1 + description: pclk1 selected + value: 0 + - name: SYSCLK + description: SYSCLK selected + value: 1 + - name: HSI16 + description: HSI16 selected + value: 2 +enum/LPTIMSEL: + bit_size: 2 + variants: + - name: PCLK7 + description: pclk7 selected. + value: 0 + - name: LSI + description: LSI selected + value: 1 + - name: HSI16 + description: HSI16 selected + value: 2 + - name: LSE + description: LSE selected + value: 3 +enum/LPUARTSEL: + bit_size: 2 + variants: + - name: PCLK7 + description: pclk7 selected + value: 0 + - name: SYSCLK + description: SYSCLK selected + value: 1 + - name: HSI16 + description: HSI16 selected + value: 2 + - name: LSE + description: LSE selected + value: 3 +enum/LSCOSEL: + bit_size: 1 + variants: + - name: LSI + description: LSI clock selected + value: 0 + - name: LSE + description: LSE clock selected + value: 1 +enum/LSEDRV: + bit_size: 2 + variants: + - name: LOW + description: '''Xtal mode lower driving capability' + value: 0 + - name: MEDIUM_LOW + description: '''Xtal mode medium-low driving capability' + value: 1 + - name: MEDIUM_HIGH + description: '''Xtal mode medium-high driving capability' + value: 2 + - name: HIGH + description: '''Xtal mode higher driving capability' + value: 3 +enum/LSETRIM: + bit_size: 2 + variants: + - name: R5_4 + description: current source resistance 5/4 x R + value: 0 + - name: R + description: current source resistance R + value: 1 + - name: R3_4 + description: current source resistance 3/4 x R + value: 2 + - name: R2_3 + description: current source resistance 2/3 x R + value: 3 +enum/LSIPREDIV: + bit_size: 1 + variants: + - name: Div1 + description: LSI not divided + value: 0 + - name: Div128 + description: LSI divided by 128 + value: 1 +enum/MCOPRE: + bit_size: 3 + variants: + - name: Div1 + description: MCO divided by 1 + value: 0 + - name: Div2 + description: MCO divided by 2 + value: 1 + - name: Div4 + description: MCO divided by 4 + value: 2 + - name: Div8 + description: MCO divided by 8 + value: 3 + - name: Div16 + description: MCO divided by 16 + value: 4 +enum/MCOSEL: + bit_size: 4 + variants: + - name: DISABLED + description: MCO output disabled, no clock on MCO + value: 0 + - name: SYSCLKPRE + description: sysclkpre system clock after PLL1RCLKPRE division selected + value: 1 + - name: HSI16 + description: HSI16 clock selected + value: 3 + - name: HSE32 + description: HSE32 clock selected + value: 4 + - name: PLL1_R + description: pll1rclk clock selected + value: 5 + - name: LSI + description: LSI clock selected + value: 6 + - name: LSE + description: LSE clock selected + value: 7 + - name: PLL1_P + description: pll1pclk clock selected + value: 8 + - name: PLL1_Q + description: pll1qclk clock selected + value: 9 + - name: HCLK5 + description: hclk5 clock selected + value: 10 +enum/PLLRCLKPRE: + bit_size: 1 + variants: + - name: Div1 + description: pll1rclk not divided, sysclkpre = pll1rclk + value: 0 + - name: Divided + description: pll1rclk divided, sysclkpre = pll1rclk divided + value: 1 +enum/PLLRCLKPRESTEP: + bit_size: 1 + variants: + - name: STEP2 + description: pll1rclk 2-step division + value: 0 + - name: STEP3 + description: pll1rclk 3-step division + value: 1 +enum/PLLRGE: + bit_size: 2 + variants: + - name: FREQ_4TO8MHZ + description: PLL2 input (ref2_ck) clock range frequency between 4 and 8 MHz + value: 0 + - name: FREQ_8TO16MHZ + description: PLL2 input (ref2_ck) clock range frequency between 8 and 16 MHz + value: 3 +enum/PLLSRC: + bit_size: 2 + variants: + - name: NONE + description: no clock sent to PLL1 + value: 0 + - name: HSI16 + description: HSI16 clock selected as PLL1 clock entry + value: 2 + - name: HSE32 + description: HSE32 clock after HSEPRE divider selected as PLL1 clock entry + value: 3 +enum/PPRE: + bit_size: 3 + variants: + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 +enum/RADIOSTSEL: + bit_size: 2 + variants: + - name: None + description: no clock selected, 2.4 GHz RADIO sleep timer kernel clock disabled + value: 0 + - name: LSE + description: LSE oscillator clock selected + value: 1 + - name: HSE32 + description: HSE32 oscillator clock divided by 1000 selected + value: 3 +enum/RNGSEL: + bit_size: 2 + variants: + - name: LSE + description: LSE selected + value: 0 + - name: LSI + description: LSI selected + value: 1 + - name: HSI16 + description: HSI16 selected + value: 2 + - name: PLL1_Q + description: pll1qclk divide by 2 selected + value: 3 +enum/RTCSEL: + bit_size: 2 + variants: + - name: NoClock + description: no clock selected, RTC and TAMP kernel clock disabled + value: 0 + - name: LSE + description: LSE oscillator clock selected, and enabled + value: 1 + - name: LSI + description: LSI oscillator clock selected, and enabled + value: 2 + - name: HSE32 + description: HSE32 oscillator clock divided by 32 selected, and enabled + value: 3 +enum/SPISEL: + bit_size: 2 + variants: + - name: PCLK2 + description: pclk2 selected + value: 0 + - name: SYSCLK + description: SYSCLK selected + value: 1 + - name: HSI16 + description: HSI16 selected + value: 2 +enum/SW: + bit_size: 2 + variants: + - name: HSI16 + description: HSI16 selected as system clock + value: 0 + - name: HSE32 + description: HSE32 or HSE32/2, as defined by HSEPRE, selected as system clock + value: 2 + - name: PLL1_R + description: pll1rclk selected as system clock + value: 3 +enum/SYSTICKSEL: + bit_size: 2 + variants: + - name: HCLK1_DIV8 + description: hclk1 divided by 8 selected + value: 0 + - name: LSI + description: LSI selected + value: 1 + - name: LSE + description: LSE selected + value: 2 +enum/TIMICSEL: + bit_size: 1 + variants: + - name: Div1 + description: HSI16 divider disabled + value: 0 + - name: HSI16_DIV_256 + description: HSI16/256 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture + value: 1 +enum/USARTSEL: + bit_size: 2 + variants: + - name: PCLK1 + description: pclk1 selected + value: 0 + - name: SYSCLK + description: SYSCLK selected + value: 1 + - name: HSI16 + description: HSI16 selected + value: 2 + - name: LSE + description: LSE selected + value: 3 diff --git a/data/registers/syscfg_wba.yaml b/data/registers/syscfg_wba.yaml new file mode 100644 index 0000000..9c46714 --- /dev/null +++ b/data/registers/syscfg_wba.yaml @@ -0,0 +1,196 @@ +block/SYSCFG: + description: System configuration controller + items: + - name: SECCFGR + description: secure configuration register + byte_offset: 0 + fieldset: SECCFGR + - name: CFGR1 + description: configuration register 1 + byte_offset: 4 + fieldset: CFGR1 + - name: FPUIMR + description: FPU interrupt mask register + byte_offset: 8 + fieldset: FPUIMR + - name: CNSLCKR + description: CPU non-secure lock register + byte_offset: 12 + fieldset: CNSLCKR + - name: CSLOCKR + description: CPU secure lock register + byte_offset: 16 + fieldset: CSLOCKR + - name: CFGR2 + description: configuration register 2 + byte_offset: 20 + fieldset: CFGR2 + - name: MESR + description: memory erase status register + byte_offset: 24 + fieldset: MESR + - name: CCCSR + description: compensation cell control/status register + byte_offset: 28 + fieldset: CCCSR + - name: CCVR + description: compensation cell value register + byte_offset: 32 + fieldset: CCVR + - name: CCCR + description: compensation cell code register + byte_offset: 36 + fieldset: CCCR + - name: RSSCMDR + description: RSS command register + byte_offset: 44 + fieldset: RSSCMDR +fieldset/CCCR: + description: compensation cell code register + fields: + - name: NCC1 + description: "NMOS compensation code of the I/Os supplied by VDD\r These bits are written by software to define an I/Os compensation cell code for NMOS transistors. This code is applied to the I/Os compensation cell when the CS1 bit of the CCCSR is set." + bit_offset: 0 + bit_size: 4 + - name: PCC1 + description: "PMOS compensation code of the I/Os supplied by VDD\r These bits are written by software to define an I/Os compensation cell code for PMOS transistors. This code is applied to the I/Os compensation cell when the CS1 bit of the CCCSR is set." + bit_offset: 4 + bit_size: 4 +fieldset/CCCSR: + description: compensation cell control/status register + fields: + - name: EN1 + description: "VDD I/Os compensation cell enable\r This bit enables the compensation cell of the I/Os supplied by VDD." + bit_offset: 0 + bit_size: 1 + - name: CS1 + description: "VDD I/Os code selection\r This bit selects the code to be applied for the compensation cell of the I/Os supplied by VDD." + bit_offset: 1 + bit_size: 1 + - name: RDY1 + description: "VDD I/Os compensation cell ready flag\r This bit provides the compensation cell status of the I/Os supplied by VDD.\r Note: The HSI16 clock is required for the compensation cell to work properly. The compensation cell ready bit (RDY1) is not set if the HSI16 clock is not enabled (HSION)." + bit_offset: 8 + bit_size: 1 +fieldset/CCVR: + description: compensation cell value register + fields: + - name: NCV1 + description: "NMOS compensation value of the I/Os supplied by VDD\r This value is provided by the cell and can be used by the CPU to compute an I/Os compensation cell code for NMOS transistors. This code is applied to the I/Os compensation cell when the CS1 bit of the CCCSR is reset." + bit_offset: 0 + bit_size: 4 + - name: PCV1 + description: "PMOS compensation value of the I/Os supplied by VDD\r This value is provided by the cell and can be used by the CPU to compute an I/Os compensation cell code for PMOS transistors. This code is applied to the I/Os compensation cell when the CS1 bit of the CCCSR is reset." + bit_offset: 4 + bit_size: 4 +fieldset/CFGR1: + description: configuration register 1 + fields: + - name: BOOSTEN + description: "I/O analog switch voltage booster enable\r Access can be protected by GTZC_TZSC ADC4SEC.\r Note: Refer to Table�121 for setting." + bit_offset: 8 + bit_size: 1 + - name: ANASWVDD + description: "GPIO analog switch control voltage selection\r Access can be protected by GTZC_TZSC ADC4SEC.\r Note: Refer to Table�121 for setting." + bit_offset: 9 + bit_size: 1 + - name: PA6_FMP + description: "Fast-mode Plus drive capability activation on PA6\r This bit can be read and written only with secure access if PA6 is secure in GPIOA. This bit enables the Fast-mode Plus drive mode for PA6 when PA6 is not used by I2C peripheral. This can be used to dive a LED for instance.\r Access can be protected by GPIOA SEC6." + bit_offset: 16 + bit_size: 1 + - name: PA7_FMP + description: "Fast-mode Plus drive capability activation on PA7\r This bit can be read and written only with secure access if PA7 is secure in GPIOA. This bit enables the Fast-mode Plus drive mode for PA7 when PA7 is not used by I2C peripheral. This can be used to dive a LED for instance.\r Access can be protected by GPIOA SEC7." + bit_offset: 17 + bit_size: 1 + - name: PA15_FMP + description: "Fast-mode Plus drive capability activation on PA15\r This bit can be read and written only with secure access if PA15 is secure in GPIOA. This bit enables the Fast-mode Plus drive mode for PA15 when PA15 is not used by I2C peripheral. This can be used to dive a LED for instance.\r Access can be protected by GPIOA SEC15." + bit_offset: 18 + bit_size: 1 + - name: PB3_FMP + description: "Fast-mode Plus drive capability activation on PB3\r This bit can be read and written only with secure access if PB3 is secure in GPIOB. This bit enables the Fast-mode Plus drive mode for PB3 when PB3 is not used by I2C peripheral. This can be used to dive a LED for instance.\r Access can be protected by GPIOB SEC3." + bit_offset: 19 + bit_size: 1 +fieldset/CFGR2: + description: configuration register 2 + fields: + - name: CLL + description: "Cortex-M33 LOCKUP (hardfault) output enable\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the connection of Cortex-M33 LOCKUP (hardfault) output to TIM1/16/17 break input." + bit_offset: 0 + bit_size: 1 + - name: SPL + description: "SRAM2 parity lock bit\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the SRAM2 parity error signal connection to TIM1/16/17 break inputs." + bit_offset: 1 + bit_size: 1 + - name: PVDL + description: "PVD lock enable bit\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection to TIM1/16/17 break input, as well as the PVDE and PVDLS[2:0] in the PWR register." + bit_offset: 2 + bit_size: 1 + - name: ECCL + description: "ECC lock\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the Flash ECC double error signal connection to TIM1/16/17 break input." + bit_offset: 3 + bit_size: 1 +fieldset/CNSLCKR: + description: CPU non-secure lock register + fields: + - name: LOCKNSVTOR + description: "VTOR_NS register lock\r This bit is set by software and cleared only by a system reset." + bit_offset: 0 + bit_size: 1 + - name: LOCKNSMPU + description: "Non-secure MPU registers lock\r This bit is set by software and cleared only by a system reset. When set, this bit disables write access to non-secure MPU_CTRL_NS, MPU_RNR_NS and MPU_RBAR_NS registers." + bit_offset: 1 + bit_size: 1 +fieldset/CSLOCKR: + description: CPU secure lock register + fields: + - name: LOCKSVTAIRCR + description: "VTOR_S register and AIRCR register bits lock\r This bit is set by software and cleared only by a system reset. When set, it disables write access to VTOR_S register, PRIS and BFHFNMINS bits in the AIRCR register." + bit_offset: 0 + bit_size: 1 + - name: LOCKSMPU + description: "Secure MPU registers lock\r This bit is set by software and cleared only by a system reset. When set, it disables write access to secure MPU_CTRL, MPU_RNR and MPU_RBAR registers." + bit_offset: 1 + bit_size: 1 + - name: LOCKSAU + description: "SAU registers lock\r This bit is set by software and cleared only by a system reset. When set, it disables write access to SAU_CTRL, SAU_RNR, SAU_RBAR and SAU_RLAR registers." + bit_offset: 2 + bit_size: 1 +fieldset/FPUIMR: + description: FPU interrupt mask register + fields: + - name: FPU_IE + description: "Floating point unit interrupts enable bits\r FPU_IE[5]: Inexact interrupt enable (interrupt disable at reset)\r FPU_IE[4]: Input abnormal interrupt enable\r FPU_IE[3]: Overflow interrupt enable\r FPU_IE[2]: Underflow interrupt enable\r FPU_IE[1]: Divide-by-zero interrupt enable\r FPU_IE[0]: Invalid operation Interrupt enable" + bit_offset: 0 + bit_size: 6 +fieldset/MESR: + description: memory erase status register + fields: + - name: MCLR + description: "Device memories erase status\r This bit is set by hardware when SRAM2, ICACHE, PKA SRAM erase is completed after power-on reset or tamper detection (refer to Section�75: Tamper and backup registers (TAMP) for more details). This bit is not reset by system reset and is cleared by software by writing 1 to it." + bit_offset: 0 + bit_size: 1 + - name: IPMEE + description: "ICACHE and PKA SRAM erase status\r This bit is set by hardware when ICACHE and PKA SRAM erase is completed after potential tamper detection (refer to Section�75: Tamper and backup registers (TAMP) for more details). This bit is cleared by software by writing 1 to it." + bit_offset: 16 + bit_size: 1 +fieldset/RSSCMDR: + description: RSS command register + fields: + - name: RSSCMD + description: "RSS commands\r This field defines a command to be executed by the RSS." + bit_offset: 0 + bit_size: 16 +fieldset/SECCFGR: + description: secure configuration register + fields: + - name: SYSCFGSEC + description: clock control, memory erase status and compensation cell registers security + bit_offset: 0 + bit_size: 1 + - name: CLASSBSEC + description: Class B security + bit_offset: 1 + bit_size: 1 + - name: FPUSEC + description: FPU security + bit_offset: 3 + bit_size: 1 diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index 6bb769f..3ede5fa 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -216,6 +216,7 @@ impl PeriMatcher { ("STM32G4.*:SYSCFG:.*", ("syscfg", "g4", "SYSCFG")), ("STM32H7.*:SYSCFG:.*", ("syscfg", "h7", "SYSCFG")), ("STM32U5.*:SYSCFG:.*", ("syscfg", "u5", "SYSCFG")), + ("STM32WBA.*:SYSCFG:.*", ("syscfg", "wba", "SYSCFG")), ("STM32WB.*:SYSCFG:.*", ("syscfg", "wb", "SYSCFG")), ("STM32WL5.*:SYSCFG:.*", ("syscfg", "wl5", "SYSCFG")), ("STM32WL5.*:ADC:.*", ("adc", "g0", "ADC")), @@ -245,6 +246,7 @@ impl PeriMatcher { ("STM32L0.*:RTC:rtc2_.*", ("rtc", "v2l0", "RTC")), ("STM32L1.*:RTC:rtc2_.*", ("rtc", "v2l1", "RTC")), ("STM32L4.*:RTC:rtc2_.*", ("rtc", "v2l4", "RTC")), + ("STM32WBA.*:RTC:rtc2_.*", ("rtc", "v3u5", "RTC")), ("STM32WB.*:RTC:rtc2_.*", ("rtc", "v2wb", "RTC")), ("STM32U5.*:RTC:rtc2_.*", ("rtc", "v3u5", "RTC")), // Cube says v2, but it's v3 with security stuff (".*:RTC:rtc3_v1_0", ("rtc", "v3", "RTC")), @@ -297,12 +299,14 @@ impl PeriMatcher { ("STM32U5.*:RCC:.*", ("rcc", "u5", "RCC")), ("STM32H50.*:RCC:.*", ("rcc", "h50", "RCC")), ("STM32H5.*:RCC:.*", ("rcc", "h5", "RCC")), + ("STM32WBA.*:RCC:.*", ("rcc", "wba", "RCC")), ("STM32WB.*:RCC:.*", ("rcc", "wb", "RCC")), ("STM32WL5.*:RCC:.*", ("rcc", "wl5", "RCC")), ("STM32WLE.*:RCC:.*", ("rcc", "wle", "RCC")), ("STM32F1.*:SPI[1234]:.*", ("spi", "f1", "SPI")), ("STM32F3.*:SPI[1234]:.*", ("spi", "v2", "SPI")), ("STM32F1.*:AFIO:.*", ("afio", "f1", "AFIO")), + ("STM32WBA.*:EXTI:.*", ("exti", "l5", "EXTI")), ("STM32L5.*:EXTI:.*", ("exti", "l5", "EXTI")), ("STM32C0.*:EXTI:.*", ("exti", "c0", "EXTI")), ("STM32G0.*:EXTI:.*", ("exti", "g0", "EXTI")), @@ -336,6 +340,7 @@ impl PeriMatcher { ("STM32L5.*:PWR:.*", ("pwr", "l5", "PWR")), ("STM32U5.*:PWR:.*", ("pwr", "u5", "PWR")), ("STM32WL.*:PWR:.*", ("pwr", "wl5", "PWR")), + ("STM32WBA.*:PWR:.*", ("pwr", "wba", "PWR")), ("STM32WB.*:PWR:.*", ("pwr", "wb55", "PWR")), ("STM32H50.*:PWR:.*", ("pwr", "h50", "PWR")), ("STM32H5.*:PWR:.*", ("pwr", "h5", "PWR")), @@ -352,6 +357,7 @@ impl PeriMatcher { ("STM32L4.*:FLASH:.*", ("flash", "l4", "FLASH")), ("STM32L5.*:FLASH:.*", ("flash", "l5", "FLASH")), ("STM32U5.*:FLASH:.*", ("flash", "u5", "FLASH")), + ("STM32WBA.*:FLASH:.*", ("flash", "wba", "FLASH")), ("STM32WB.*:FLASH:.*", ("flash", "wb", "FLASH")), ("STM32WL.*:FLASH:.*", ("flash", "wl", "FLASH")), ("STM32C0.*:FLASH:.*", ("flash", "c0", "FLASH")), @@ -363,6 +369,7 @@ impl PeriMatcher { ("STM32F[24].*:ETH:.*", ("eth", "v1b", "ETH")), ("STM32F7.*:ETH:.*", ("eth", "v1c", "ETH")), (".*ETH:ethermac110_v3_0", ("eth", "v2", "ETH")), + (".*ETH:ethermac110_v3_0_1", ("eth", "v2", "ETH")), ("STM32F4[23][79].*:FMC:.*", ("fmc", "v1x3", "FMC")), ("STM32F446.*:FMC:.*", ("fmc", "v2x1", "FMC")), ("STM32F469.*:FMC:.*", ("fmc", "v2x1", "FMC")), @@ -405,6 +412,7 @@ impl PeriMatcher { ("STM32L1.*:DBGMCU:.*", ("dbgmcu", "l1", "DBGMCU")), ("STM32L4.*:DBGMCU:.*", ("dbgmcu", "l4", "DBGMCU")), ("STM32U5.*:DBGMCU:.*", ("dbgmcu", "u5", "DBGMCU")), + ("STM32WBA.*:DBGMCU:.*", ("dbgmcu", "wba", "DBGMCU")), ("STM32WB.*:DBGMCU:.*", ("dbgmcu", "wb", "DBGMCU")), ("STM32WL.*:DBGMCU:.*", ("dbgmcu", "wl", "DBGMCU")), ("STM32F1.*:GPIO.*", ("gpio", "v1", "GPIO")), @@ -546,11 +554,11 @@ pub fn parse_groups() -> Result<(HashMap, Vec), anyhow: static NOPELIST: &[&str] = &[ // Not supported, not planned unless someone wants to do it. "STM32MP", - // Not supported yet, planned. - "STM32WBA", // Does not exist in ST website. No datasheet, no RM. "STM32GBK", "STM32L485", + "STM32U5F", + "STM32U5G", // STM32WxM modules. These are based on a chip that's supported on its own, // not sure why we want a separate target for it. "STM32WL5M", @@ -765,7 +773,7 @@ fn process_core( if ["L5", "U5"].contains(&&chip_name[5..7]) { want_nvic_name = "NVIC2" } - if ["H56", "H57"].contains(&&chip_name[5..8]) { + if ["H56", "H57", "WBA"].contains(&&chip_name[5..8]) { want_nvic_name = "NVIC2" } diff --git a/stm32-data-gen/src/dma.rs b/stm32-data-gen/src/dma.rs index 083eaf5..116edc7 100644 --- a/stm32-data-gen/src/dma.rs +++ b/stm32-data-gen/src/dma.rs @@ -298,6 +298,7 @@ impl DmaChannels { ("H5_GPDMA.yaml", "GPDMA1", "STM32H5_dma3_Cube", 8, 2), ("H5_GPDMA.yaml", "GPDMA2", "Instance2_STM32H5_dma3_Cube", 8, 2), ("U5_GPDMA1.yaml", "GPDMA1", "STM32U5_dma3_Cube", 16, 4), + ("WBA_GPDMA1.yaml", "GPDMA1", "STM32WBA_dma3_Cube", 8, 0), ] { let mut chip_dma = ChipDma { peripherals: HashMap::new(),