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rcc: check l4plus and l5

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This commit is contained in:
xoviat 2023-10-17 17:21:06 -05:00
parent c61495fd4e
commit 3d9c8b70e3
5 changed files with 13 additions and 13 deletions
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2
data/registers/rcc_f3.yaml
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@ -1244,7 +1244,7 @@ enum/SW:
enum/TIMSW: enum/TIMSW:
bit_size: 1 bit_size: 1
variants: variants:
- name: PCLK2 - name: PCLK2_TIM
description: PCLK2 clock (doubled frequency when prescaled) description: PCLK2 clock (doubled frequency when prescaled)
value: 0 value: 0
- name: PLL1_P - name: PLL1_P

2
data/registers/rcc_f3_v2.yaml
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@ -1220,7 +1220,7 @@ enum/SW:
enum/TIMSW: enum/TIMSW:
bit_size: 1 bit_size: 1
variants: variants:
- name: PCLK2 - name: PCLK2_TIM
description: PCLK2 clock (doubled frequency when prescaled) description: PCLK2 clock (doubled frequency when prescaled)
value: 0 value: 0
- name: PLL1_P - name: PLL1_P

10
data/registers/rcc_l4plus.yaml
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@ -1668,7 +1668,7 @@ enum/ADCSEL:
- name: DISABLE - name: DISABLE
description: No clock selected description: No clock selected
value: 0 value: 0
- name: PLLADC1CLK - name: PLLSAI1_R
description: PLLADC1CLK clock selected description: PLLADC1CLK clock selected
value: 1 value: 1
- name: SYS - name: SYS
@ -1716,7 +1716,7 @@ enum/DSISEL:
- name: DSIPHY - name: DSIPHY
description: DSI-PHY is selected as DSI byte lane clock source (usual case) description: DSI-PHY is selected as DSI byte lane clock source (usual case)
value: 0 value: 0
- name: PLLDSICLK - name: PLLSAI2_Q
description: PLLDSICLK is selected as DSI byte lane clock source, used in case DSI PLL and DSIPHY are off (low-power mode) description: PLLDSICLK is selected as DSI byte lane clock source, used in case DSI PLL and DSIPHY are off (low-power mode)
value: 1 value: 1
enum/HPRE: enum/HPRE:
@ -1971,7 +1971,7 @@ enum/OSPISEL:
- name: MSI - name: MSI
description: MSI clock selected as OctoSPI kernel clock description: MSI clock selected as OctoSPI kernel clock
value: 1 value: 1
- name: PLL48M1CLK - name: PLL1_Q
description: PLL48M1CLK clock selected as OctoSPI kernel clock description: PLL48M1CLK clock selected as OctoSPI kernel clock
value: 2 value: 2
enum/PLLM: enum/PLLM:
@ -2434,7 +2434,7 @@ enum/SDMMCSEL:
- name: HSI48 - name: HSI48
description: 48 MHz clock is selected as SDMMC kernel clock description: 48 MHz clock is selected as SDMMC kernel clock
value: 0 value: 0
- name: PLLSAI3CLK - name: PLL1_P
description: PLLSAI3CLK is selected as SDMMC kernel clock, used in case higher frequency than 48MHz is needed (for SDR50 mode) description: PLLSAI3CLK is selected as SDMMC kernel clock, used in case higher frequency than 48MHz is needed (for SDR50 mode)
value: 1 value: 1
enum/STOPWUCK: enum/STOPWUCK:
@ -2458,7 +2458,7 @@ enum/SW:
- name: HSE - name: HSE
description: HSE selected as system clock description: HSE selected as system clock
value: 2 value: 2
- name: PLL - name: PLL1_R
description: PLL selected as system clock description: PLL selected as system clock
value: 3 value: 3
enum/UART4SEL: enum/UART4SEL:

10
data/registers/rcc_l5.yaml
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@ -1933,7 +1933,7 @@ enum/CLK48SEL:
- name: PLLSAI1_Q - name: PLLSAI1_Q
description: PLLSAI1_Q aka PLL48M1CLK clock selected description: PLLSAI1_Q aka PLL48M1CLK clock selected
value: 1 value: 1
- name: PLL_Q - name: PLL1_Q
description: PLL_Q aka PLL48M2CLK clock selected description: PLL_Q aka PLL48M2CLK clock selected
value: 2 value: 2
- name: MSI - name: MSI
@ -2468,7 +2468,7 @@ enum/PLLSRC:
- name: MSI - name: MSI
description: MSI selected as PLL input clock description: MSI selected as PLL input clock
value: 1 value: 1
- name: HSI16 - name: HSI
description: HSI selected as PLL input clock description: HSI selected as PLL input clock
value: 2 value: 2
- name: HSE - name: HSE
@ -2513,7 +2513,7 @@ enum/STOPWUCK:
- name: MSI - name: MSI
description: MSI oscillator selected as wake-up from Stop clock and CSS backup clock description: MSI oscillator selected as wake-up from Stop clock and CSS backup clock
value: 0 value: 0
- name: HSI16 - name: HSI
description: HSI oscillator selected as wake-up from stop clock and CSS backup clock description: HSI oscillator selected as wake-up from stop clock and CSS backup clock
value: 1 value: 1
enum/SW: enum/SW:
@ -2522,12 +2522,12 @@ enum/SW:
- name: MSI - name: MSI
description: MSI selected as system clock description: MSI selected as system clock
value: 0 value: 0
- name: HSI16 - name: HSI
description: HSI selected as system clock description: HSI selected as system clock
value: 1 value: 1
- name: HSE - name: HSE
description: HSE selected as system clock description: HSE selected as system clock
value: 2 value: 2
- name: PLL - name: PLL1_R
description: PLL selected as system clock description: PLL selected as system clock
value: 3 value: 3

2
stm32-data-gen/src/rcc.rs
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@ -17,7 +17,7 @@ impl PeripheralToClock {
let mut peripheral_to_clock = HashMap::new(); let mut peripheral_to_clock = HashMap::new();
let checked_rccs = HashSet::from([ let checked_rccs = HashSet::from([
"c0", "f0", "f1", "f100", "f1c1", "f2", "f3", "f3_v2", "f4", "f410", "f7", "g0", "g4", "h5", "h50", "h7", "c0", "f0", "f1", "f100", "f1c1", "f2", "f3", "f3_v2", "f4", "f410", "f7", "g0", "g4", "h5", "h50", "h7",
"h7ab", "h7rm0433", "l0", "l0_v2", "l1", "l4", "h7ab", "h7rm0433", "l0", "l0_v2", "l1", "l4", "l4plus", "l5",
]); ]);
let allowed_variants = HashSet::from([ let allowed_variants = HashSet::from([
"DISABLE", "DISABLE",