From 3d9c8b70e3d22b3c9238842217af116560a3825c Mon Sep 17 00:00:00 2001 From: xoviat Date: Tue, 17 Oct 2023 17:21:06 -0500 Subject: [PATCH] rcc: check l4plus and l5 --- data/registers/rcc_f3.yaml | 2 +- data/registers/rcc_f3_v2.yaml | 2 +- data/registers/rcc_l4plus.yaml | 10 +++++----- data/registers/rcc_l5.yaml | 10 +++++----- stm32-data-gen/src/rcc.rs | 2 +- 5 files changed, 13 insertions(+), 13 deletions(-) diff --git a/data/registers/rcc_f3.yaml b/data/registers/rcc_f3.yaml index 8c3b90f..6a39586 100644 --- a/data/registers/rcc_f3.yaml +++ b/data/registers/rcc_f3.yaml @@ -1244,7 +1244,7 @@ enum/SW: enum/TIMSW: bit_size: 1 variants: - - name: PCLK2 + - name: PCLK2_TIM description: PCLK2 clock (doubled frequency when prescaled) value: 0 - name: PLL1_P diff --git a/data/registers/rcc_f3_v2.yaml b/data/registers/rcc_f3_v2.yaml index 35ec19e..f6d0105 100644 --- a/data/registers/rcc_f3_v2.yaml +++ b/data/registers/rcc_f3_v2.yaml @@ -1220,7 +1220,7 @@ enum/SW: enum/TIMSW: bit_size: 1 variants: - - name: PCLK2 + - name: PCLK2_TIM description: PCLK2 clock (doubled frequency when prescaled) value: 0 - name: PLL1_P diff --git a/data/registers/rcc_l4plus.yaml b/data/registers/rcc_l4plus.yaml index 7e13da1..10105cc 100644 --- a/data/registers/rcc_l4plus.yaml +++ b/data/registers/rcc_l4plus.yaml @@ -1668,7 +1668,7 @@ enum/ADCSEL: - name: DISABLE description: No clock selected value: 0 - - name: PLLADC1CLK + - name: PLLSAI1_R description: PLLADC1CLK clock selected value: 1 - name: SYS @@ -1716,7 +1716,7 @@ enum/DSISEL: - name: DSIPHY description: DSI-PHY is selected as DSI byte lane clock source (usual case) value: 0 - - name: PLLDSICLK + - name: PLLSAI2_Q description: PLLDSICLK is selected as DSI byte lane clock source, used in case DSI PLL and DSIPHY are off (low-power mode) value: 1 enum/HPRE: @@ -1971,7 +1971,7 @@ enum/OSPISEL: - name: MSI description: MSI clock selected as OctoSPI kernel clock value: 1 - - name: PLL48M1CLK + - name: PLL1_Q description: PLL48M1CLK clock selected as OctoSPI kernel clock value: 2 enum/PLLM: @@ -2434,7 +2434,7 @@ enum/SDMMCSEL: - name: HSI48 description: 48 MHz clock is selected as SDMMC kernel clock value: 0 - - name: PLLSAI3CLK + - name: PLL1_P description: PLLSAI3CLK is selected as SDMMC kernel clock, used in case higher frequency than 48MHz is needed (for SDR50 mode) value: 1 enum/STOPWUCK: @@ -2458,7 +2458,7 @@ enum/SW: - name: HSE description: HSE selected as system clock value: 2 - - name: PLL + - name: PLL1_R description: PLL selected as system clock value: 3 enum/UART4SEL: diff --git a/data/registers/rcc_l5.yaml b/data/registers/rcc_l5.yaml index 921fece..e4bcc3b 100644 --- a/data/registers/rcc_l5.yaml +++ b/data/registers/rcc_l5.yaml @@ -1933,7 +1933,7 @@ enum/CLK48SEL: - name: PLLSAI1_Q description: PLLSAI1_Q aka PLL48M1CLK clock selected value: 1 - - name: PLL_Q + - name: PLL1_Q description: PLL_Q aka PLL48M2CLK clock selected value: 2 - name: MSI @@ -2468,7 +2468,7 @@ enum/PLLSRC: - name: MSI description: MSI selected as PLL input clock value: 1 - - name: HSI16 + - name: HSI description: HSI selected as PLL input clock value: 2 - name: HSE @@ -2513,7 +2513,7 @@ enum/STOPWUCK: - name: MSI description: MSI oscillator selected as wake-up from Stop clock and CSS backup clock value: 0 - - name: HSI16 + - name: HSI description: HSI oscillator selected as wake-up from stop clock and CSS backup clock value: 1 enum/SW: @@ -2522,12 +2522,12 @@ enum/SW: - name: MSI description: MSI selected as system clock value: 0 - - name: HSI16 + - name: HSI description: HSI selected as system clock value: 1 - name: HSE description: HSE selected as system clock value: 2 - - name: PLL + - name: PLL1_R description: PLL selected as system clock value: 3 diff --git a/stm32-data-gen/src/rcc.rs b/stm32-data-gen/src/rcc.rs index 4a50e4d..6fb0c79 100644 --- a/stm32-data-gen/src/rcc.rs +++ b/stm32-data-gen/src/rcc.rs @@ -17,7 +17,7 @@ impl PeripheralToClock { let mut peripheral_to_clock = HashMap::new(); let checked_rccs = HashSet::from([ "c0", "f0", "f1", "f100", "f1c1", "f2", "f3", "f3_v2", "f4", "f410", "f7", "g0", "g4", "h5", "h50", "h7", - "h7ab", "h7rm0433", "l0", "l0_v2", "l1", "l4", + "h7ab", "h7rm0433", "l0", "l0_v2", "l1", "l4", "l4plus", "l5", ]); let allowed_variants = HashSet::from([ "DISABLE",