h5: add EXTI.
This commit is contained in:
Dario Nieuwenhuis
parent
c3f659d01f
commit
3ccc957f11
145
data/registers/exti_h5.yaml
Normal file
145
data/registers/exti_h5.yaml
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@ -0,0 +1,145 @@
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---
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block/EXTI:
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description: Extended interrupt and event controller
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items:
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- name: RTSR
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description: rising trigger selection register
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array:
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len: 2
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stride: 32
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byte_offset: 0
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fieldset: LINES
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- name: FTSR
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description: falling trigger selection register
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array:
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len: 2
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stride: 32
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byte_offset: 4
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fieldset: LINES
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- name: SWIER
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description: software interrupt event register
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array:
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len: 2
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stride: 32
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byte_offset: 8
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fieldset: LINES
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- name: RPR
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description: rising edge pending register
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array:
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len: 2
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stride: 32
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byte_offset: 12
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fieldset: LINES
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- name: FPR
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description: falling edge pending register
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array:
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len: 2
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stride: 32
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byte_offset: 16
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fieldset: LINES
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- name: SECCFGR
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description: security configuration register
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array:
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len: 2
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stride: 32
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byte_offset: 20
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fieldset: SEC
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- name: PRIVCFGR
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description: privilege configuration register
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array:
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len: 2
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stride: 32
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byte_offset: 24
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fieldset: PRIV
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- name: EXTICR
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description: external interrupt selection register
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array:
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len: 4
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stride: 4
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byte_offset: 96
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fieldset: EXTI
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- name: LOCKR
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description: lock register
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byte_offset: 112
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fieldset: LOCKR
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- name: IMR
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description: CPU wakeup with interrupt mask register
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array:
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len: 2
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stride: 16
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byte_offset: 128
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fieldset: LINES
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- name: EMR
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description: CPU wakeup with event mask register
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array:
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len: 2
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stride: 16
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byte_offset: 132
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fieldset: LINES
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fieldset/EXTI:
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description: EXTI external interrupt selection register
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fields:
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- name: EXTI
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description: "EXTI12 GPIO port selection\r These bits are written by software to select the source input for EXTI12 external interrupt.\r When EXTI_PRIVCFGR.PRIV12 is disabled, EXTI12 can be accessed with privileged and unprivileged access.\r When EXTI_PRIVCFGR.PRIV12 is enabled, EXTI12 can only be accessed with privileged access. Unprivileged write to this bit is discarded.\r Others: reserved"
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bit_offset: 0
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bit_size: 8
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array:
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len: 4
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stride: 8
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fieldset/LINES:
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description: "EXTI lines register, 1 bit per line"
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fields:
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- name: LINE
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description: EXTI line
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bit_offset: 0
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bit_size: 1
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array:
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len: 32
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stride: 1
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fieldset/LOCKR:
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description: lock register
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fields:
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- name: LOCK
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description: "Global security and privilege configuration registers (EXTI_SECCFGR and EXTI_PRIVCFGR) lock \r This bit is written once after reset."
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bit_offset: 0
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bit_size: 1
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fieldset/PRIV:
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description: privilege configuration register
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fields:
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- name: PRIV
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description: "Security enable on event input x\r When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access.\r When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded."
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bit_offset: 0
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bit_size: 1
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array:
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len: 32
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stride: 1
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enum: PRIV
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fieldset/SEC:
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description: security configuration register
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fields:
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- name: SEC
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description: "Security enable on event input x\r When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access.\r When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded."
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bit_offset: 0
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bit_size: 1
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array:
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len: 32
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stride: 1
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enum: SEC
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enum/PRIV:
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bit_size: 1
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variants:
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- name: Unprivileged
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description: Event privilege disabled (unprivileged)
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value: 0
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- name: Privileged
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description: Event privilege enabled (privileged)
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value: 1
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enum/SEC:
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bit_size: 1
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variants:
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- name: NonSecure
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description: Event security disabled (non-secure)
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value: 0
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- name: Secure
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description: Event security enabled (secure)
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value: 1
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107
data/registers/exti_h50.yaml
Normal file
107
data/registers/exti_h50.yaml
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@ -0,0 +1,107 @@
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---
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block/EXTI:
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description: Extended interrupt and event controller
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items:
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- name: RTSR
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description: rising trigger selection register
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array:
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len: 2
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stride: 32
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byte_offset: 0
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fieldset: LINES
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- name: FTSR
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description: falling trigger selection register
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array:
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len: 2
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stride: 32
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byte_offset: 4
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fieldset: LINES
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- name: SWIER
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description: software interrupt event register
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array:
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len: 2
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stride: 32
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byte_offset: 8
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fieldset: LINES
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- name: RPR
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description: rising edge pending register
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array:
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len: 2
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stride: 32
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byte_offset: 12
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fieldset: LINES
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- name: FPR
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description: falling edge pending register
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array:
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len: 2
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stride: 32
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byte_offset: 16
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fieldset: LINES
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- name: PRIVCFGR
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description: privilege configuration register
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array:
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len: 2
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stride: 32
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byte_offset: 24
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fieldset: PRIV
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- name: EXTICR
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description: external interrupt selection register
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array:
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len: 4
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stride: 4
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byte_offset: 96
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fieldset: EXTI
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- name: IMR
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description: CPU wakeup with interrupt mask register
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array:
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len: 2
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stride: 16
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byte_offset: 128
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fieldset: LINES
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- name: EMR
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description: CPU wakeup with event mask register
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array:
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len: 2
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stride: 16
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byte_offset: 132
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fieldset: LINES
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fieldset/EXTI:
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description: EXTI external interrupt selection register
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fields:
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- name: EXTI
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description: "EXTI12 GPIO port selection\r These bits are written by software to select the source input for EXTI12 external interrupt.\r When EXTI_PRIVCFGR.PRIV12 is disabled, EXTI12 can be accessed with privileged and unprivileged access.\r When EXTI_PRIVCFGR.PRIV12 is enabled, EXTI12 can only be accessed with privileged access. Unprivileged write to this bit is discarded.\r Others: reserved"
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bit_offset: 0
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bit_size: 8
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array:
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len: 4
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stride: 8
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fieldset/LINES:
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description: "EXTI lines register, 1 bit per line"
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fields:
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- name: LINE
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description: EXTI line
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bit_offset: 0
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bit_size: 1
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array:
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len: 32
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stride: 1
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fieldset/PRIV:
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description: privilege configuration register
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fields:
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- name: PRIV
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description: "Security enable on event input x\r When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access.\r When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded."
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bit_offset: 0
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bit_size: 1
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array:
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len: 32
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stride: 1
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enum: PRIV
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enum/PRIV:
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bit_size: 1
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variants:
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- name: Unprivileged
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description: Event privilege disabled (unprivileged)
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value: 0
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- name: Privileged
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description: Event privilege enabled (privileged)
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value: 1
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@ -264,6 +264,8 @@ impl PeriMatcher {
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("STM32WB.*:EXTI:.*", ("exti", "w", "EXTI")),
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("STM32WL5.*:EXTI:.*", ("exti", "w", "EXTI")),
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("STM32WLE.*:EXTI:.*", ("exti", "wle", "EXTI")),
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("STM32H50.*:EXTI:.*", ("exti", "h50", "EXTI")),
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("STM32H5.*:EXTI:.*", ("exti", "h5", "EXTI")),
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(".*:EXTI:.*", ("exti", "v1", "EXTI")),
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("STM32L0.*:CRS:.*", ("crs", "l0", "CRS")),
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(".*SDMMC:sdmmc2_v1_0", ("sdmmc", "v2", "SDMMC")),
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