From 3ccc957f11ea6cf8824634e13c94aa83a5912c4a Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Mon, 27 Mar 2023 21:01:02 +0200 Subject: [PATCH] h5: add EXTI. --- data/registers/exti_h5.yaml | 145 +++++++++++++++++++++++++++++++++++ data/registers/exti_h50.yaml | 107 ++++++++++++++++++++++++++ stm32-data-gen/src/chips.rs | 2 + 3 files changed, 254 insertions(+) create mode 100644 data/registers/exti_h5.yaml create mode 100644 data/registers/exti_h50.yaml diff --git a/data/registers/exti_h5.yaml b/data/registers/exti_h5.yaml new file mode 100644 index 0000000..939979f --- /dev/null +++ b/data/registers/exti_h5.yaml @@ -0,0 +1,145 @@ +--- +block/EXTI: + description: Extended interrupt and event controller + items: + - name: RTSR + description: rising trigger selection register + array: + len: 2 + stride: 32 + byte_offset: 0 + fieldset: LINES + - name: FTSR + description: falling trigger selection register + array: + len: 2 + stride: 32 + byte_offset: 4 + fieldset: LINES + - name: SWIER + description: software interrupt event register + array: + len: 2 + stride: 32 + byte_offset: 8 + fieldset: LINES + - name: RPR + description: rising edge pending register + array: + len: 2 + stride: 32 + byte_offset: 12 + fieldset: LINES + - name: FPR + description: falling edge pending register + array: + len: 2 + stride: 32 + byte_offset: 16 + fieldset: LINES + - name: SECCFGR + description: security configuration register + array: + len: 2 + stride: 32 + byte_offset: 20 + fieldset: SEC + - name: PRIVCFGR + description: privilege configuration register + array: + len: 2 + stride: 32 + byte_offset: 24 + fieldset: PRIV + - name: EXTICR + description: external interrupt selection register + array: + len: 4 + stride: 4 + byte_offset: 96 + fieldset: EXTI + - name: LOCKR + description: lock register + byte_offset: 112 + fieldset: LOCKR + - name: IMR + description: CPU wakeup with interrupt mask register + array: + len: 2 + stride: 16 + byte_offset: 128 + fieldset: LINES + - name: EMR + description: CPU wakeup with event mask register + array: + len: 2 + stride: 16 + byte_offset: 132 + fieldset: LINES +fieldset/EXTI: + description: EXTI external interrupt selection register + fields: + - name: EXTI + description: "EXTI12 GPIO port selection\r These bits are written by software to select the source input for EXTI12 external interrupt.\r When EXTI_PRIVCFGR.PRIV12 is disabled, EXTI12 can be accessed with privileged and unprivileged access.\r When EXTI_PRIVCFGR.PRIV12 is enabled, EXTI12 can only be accessed with privileged access. Unprivileged write to this bit is discarded.\r Others: reserved" + bit_offset: 0 + bit_size: 8 + array: + len: 4 + stride: 8 +fieldset/LINES: + description: "EXTI lines register, 1 bit per line" + fields: + - name: LINE + description: EXTI line + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 +fieldset/LOCKR: + description: lock register + fields: + - name: LOCK + description: "Global security and privilege configuration registers (EXTI_SECCFGR and EXTI_PRIVCFGR) lock \r This bit is written once after reset." + bit_offset: 0 + bit_size: 1 +fieldset/PRIV: + description: privilege configuration register + fields: + - name: PRIV + description: "Security enable on event input x\r When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access.\r When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded." + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 + enum: PRIV +fieldset/SEC: + description: security configuration register + fields: + - name: SEC + description: "Security enable on event input x\r When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access.\r When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded." + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 + enum: SEC +enum/PRIV: + bit_size: 1 + variants: + - name: Unprivileged + description: Event privilege disabled (unprivileged) + value: 0 + - name: Privileged + description: Event privilege enabled (privileged) + value: 1 +enum/SEC: + bit_size: 1 + variants: + - name: NonSecure + description: Event security disabled (non-secure) + value: 0 + - name: Secure + description: Event security enabled (secure) + value: 1 diff --git a/data/registers/exti_h50.yaml b/data/registers/exti_h50.yaml new file mode 100644 index 0000000..265902d --- /dev/null +++ b/data/registers/exti_h50.yaml @@ -0,0 +1,107 @@ +--- +block/EXTI: + description: Extended interrupt and event controller + items: + - name: RTSR + description: rising trigger selection register + array: + len: 2 + stride: 32 + byte_offset: 0 + fieldset: LINES + - name: FTSR + description: falling trigger selection register + array: + len: 2 + stride: 32 + byte_offset: 4 + fieldset: LINES + - name: SWIER + description: software interrupt event register + array: + len: 2 + stride: 32 + byte_offset: 8 + fieldset: LINES + - name: RPR + description: rising edge pending register + array: + len: 2 + stride: 32 + byte_offset: 12 + fieldset: LINES + - name: FPR + description: falling edge pending register + array: + len: 2 + stride: 32 + byte_offset: 16 + fieldset: LINES + - name: PRIVCFGR + description: privilege configuration register + array: + len: 2 + stride: 32 + byte_offset: 24 + fieldset: PRIV + - name: EXTICR + description: external interrupt selection register + array: + len: 4 + stride: 4 + byte_offset: 96 + fieldset: EXTI + - name: IMR + description: CPU wakeup with interrupt mask register + array: + len: 2 + stride: 16 + byte_offset: 128 + fieldset: LINES + - name: EMR + description: CPU wakeup with event mask register + array: + len: 2 + stride: 16 + byte_offset: 132 + fieldset: LINES +fieldset/EXTI: + description: EXTI external interrupt selection register + fields: + - name: EXTI + description: "EXTI12 GPIO port selection\r These bits are written by software to select the source input for EXTI12 external interrupt.\r When EXTI_PRIVCFGR.PRIV12 is disabled, EXTI12 can be accessed with privileged and unprivileged access.\r When EXTI_PRIVCFGR.PRIV12 is enabled, EXTI12 can only be accessed with privileged access. Unprivileged write to this bit is discarded.\r Others: reserved" + bit_offset: 0 + bit_size: 8 + array: + len: 4 + stride: 8 +fieldset/LINES: + description: "EXTI lines register, 1 bit per line" + fields: + - name: LINE + description: EXTI line + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 +fieldset/PRIV: + description: privilege configuration register + fields: + - name: PRIV + description: "Security enable on event input x\r When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access.\r When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded." + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 + enum: PRIV +enum/PRIV: + bit_size: 1 + variants: + - name: Unprivileged + description: Event privilege disabled (unprivileged) + value: 0 + - name: Privileged + description: Event privilege enabled (privileged) + value: 1 diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index ef780af..344bce7 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -264,6 +264,8 @@ impl PeriMatcher { ("STM32WB.*:EXTI:.*", ("exti", "w", "EXTI")), ("STM32WL5.*:EXTI:.*", ("exti", "w", "EXTI")), ("STM32WLE.*:EXTI:.*", ("exti", "wle", "EXTI")), + ("STM32H50.*:EXTI:.*", ("exti", "h50", "EXTI")), + ("STM32H5.*:EXTI:.*", ("exti", "h5", "EXTI")), (".*:EXTI:.*", ("exti", "v1", "EXTI")), ("STM32L0.*:CRS:.*", ("crs", "l0", "CRS")), (".*SDMMC:sdmmc2_v1_0", ("sdmmc", "v2", "SDMMC")),