Fix qspi for all chips.

Co-Authored-By: Tupelov <64274155+Tupelov@users.noreply.github.com>
This commit is contained in:
Dario Nieuwenhuis 2023-12-08 21:52:39 +01:00
parent 019a5da1c4
commit 3634020845
3 changed files with 4 additions and 2 deletions

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@ -157,7 +157,7 @@ fieldset/CR:
- name: FTHRES - name: FTHRES
description: IFO threshold level description: IFO threshold level
bit_offset: 8 bit_offset: 8
bit_size: 5 bit_size: 4
- name: TEIE - name: TEIE
description: Transfer error interrupt enable description: Transfer error interrupt enable
bit_offset: 16 bit_offset: 16

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@ -251,7 +251,7 @@ impl PeriMatcher {
(".*:HRTIM:hrtim_G4", ("hrtim", "v2", "HRTIM")), (".*:HRTIM:hrtim_G4", ("hrtim", "v2", "HRTIM")),
(".*:LTDC:lcdtft1_v1_1", ("ltdc", "v1", "LTDC")), (".*:LTDC:lcdtft1_v1_1", ("ltdc", "v1", "LTDC")),
(".*:MDIOS:mdios1_v1_0", ("mdios", "v1", "MDIOS")), (".*:MDIOS:mdios1_v1_0", ("mdios", "v1", "MDIOS")),
(".*:QUADSPI:quadspi1_v1_0", ("quadspi", "v1", "QUADSPI")), (".*:QUADSPI:.*", ("quadspi", "v1", "QUADSPI")),
("STM32F1.*:BKP.*", ("bkp", "v1", "BKP")), ("STM32F1.*:BKP.*", ("bkp", "v1", "BKP")),
(".*:RTC:rtc1_v1_1", ("rtc", "v1", "RTC")), (".*:RTC:rtc1_v1_1", ("rtc", "v1", "RTC")),
("STM32F0.*:RTC:rtc2_.*", ("rtc", "v2f0", "RTC")), ("STM32F0.*:RTC:rtc2_.*", ("rtc", "v2f0", "RTC")),

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@ -160,6 +160,8 @@ impl Defines {
pub fn get_peri_addr(&self, pname: &str) -> Option<u32> { pub fn get_peri_addr(&self, pname: &str) -> Option<u32> {
const ALT_PERI_DEFINES: &[(&str, &[&str])] = &[ const ALT_PERI_DEFINES: &[(&str, &[&str])] = &[
("DBGMCU", &["DBGMCU_BASE", "DBG_BASE"]), ("DBGMCU", &["DBGMCU_BASE", "DBG_BASE"]),
("QUADSPI", &["QUADSPI_BASE", "QSPI_R", "QSPI_R_BASE", "QSPI_REG_BASE"]),
("QUADSPI1", &["QUADSPI1_BASE", "QSPI_R", "QSPI_R_BASE", "QSPI_REG_BASE"]),
("FLASH", &["FLASH_R_BASE", "FLASH_REG_BASE"]), ("FLASH", &["FLASH_R_BASE", "FLASH_REG_BASE"]),
( (
"ADC_COMMON", "ADC_COMMON",