From 36340208453ac84228c993dcb3a717c018243296 Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Fri, 8 Dec 2023 21:52:39 +0100 Subject: [PATCH] Fix qspi for all chips. Co-Authored-By: Tupelov <64274155+Tupelov@users.noreply.github.com> --- data/registers/quadspi_v1.yaml | 2 +- stm32-data-gen/src/chips.rs | 2 +- stm32-data-gen/src/header.rs | 2 ++ 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/data/registers/quadspi_v1.yaml b/data/registers/quadspi_v1.yaml index ecf3e50..1850259 100644 --- a/data/registers/quadspi_v1.yaml +++ b/data/registers/quadspi_v1.yaml @@ -157,7 +157,7 @@ fieldset/CR: - name: FTHRES description: IFO threshold level bit_offset: 8 - bit_size: 5 + bit_size: 4 - name: TEIE description: Transfer error interrupt enable bit_offset: 16 diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index 345e271..110e547 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -251,7 +251,7 @@ impl PeriMatcher { (".*:HRTIM:hrtim_G4", ("hrtim", "v2", "HRTIM")), (".*:LTDC:lcdtft1_v1_1", ("ltdc", "v1", "LTDC")), (".*:MDIOS:mdios1_v1_0", ("mdios", "v1", "MDIOS")), - (".*:QUADSPI:quadspi1_v1_0", ("quadspi", "v1", "QUADSPI")), + (".*:QUADSPI:.*", ("quadspi", "v1", "QUADSPI")), ("STM32F1.*:BKP.*", ("bkp", "v1", "BKP")), (".*:RTC:rtc1_v1_1", ("rtc", "v1", "RTC")), ("STM32F0.*:RTC:rtc2_.*", ("rtc", "v2f0", "RTC")), diff --git a/stm32-data-gen/src/header.rs b/stm32-data-gen/src/header.rs index 47ee8b8..dd3623a 100644 --- a/stm32-data-gen/src/header.rs +++ b/stm32-data-gen/src/header.rs @@ -160,6 +160,8 @@ impl Defines { pub fn get_peri_addr(&self, pname: &str) -> Option { const ALT_PERI_DEFINES: &[(&str, &[&str])] = &[ ("DBGMCU", &["DBGMCU_BASE", "DBG_BASE"]), + ("QUADSPI", &["QUADSPI_BASE", "QSPI_R", "QSPI_R_BASE", "QSPI_REG_BASE"]), + ("QUADSPI1", &["QUADSPI1_BASE", "QSPI_R", "QSPI_R_BASE", "QSPI_REG_BASE"]), ("FLASH", &["FLASH_R_BASE", "FLASH_REG_BASE"]), ( "ADC_COMMON",