Merge pull request #39 from lulf/add-rcc-f4

Add RCC register for F4, L4

extract.sh

@@ -6,7 +6,7 @@ board=$1
 peri=$2
 mkdir -p regs/$peri
 
-cargo build --release --manifest-path ../../../svd2rust/Cargo.toml 
+cargo build --release --manifest-path ../../svd2rust/Cargo.toml 
 
 transform="transform.yaml"
 
@@ -28,7 +28,7 @@ for f in `ls $query`; do
     f=${f#"stm32"}
     f=${f%".svd"}
     echo -n processing $f ...
-    RUST_LOG=info ../../../svd2rust/target/release/svd4rust extract-peripheral --svd sources/svd/stm32$f.svd --transform $transform --peripheral $peri > regs/$peri/$f.yaml 2> regs/$peri/$f.yaml.out
+    RUST_LOG=info ../../svd2rust/target/release/svd4rust extract-peripheral --svd sources/svd/stm32$f.svd --transform $transform --peripheral $peri > regs/$peri/$f.yaml 2> regs/$peri/$f.yaml.out
     if [ $? -ne 0 ]; then 
         mv regs/$peri/$f.yaml.out regs/$peri/$f.err
         rm regs/$peri/$f.yaml

merge_regs.py

@@ -0,0 +1,61 @@
+import xmltodict
+import yaml
+import re
+import json
+import sys
+import os
+from collections import OrderedDict
+from glob import glob
+
+def item_key(a):
+    return int(a["byte_offset"])
+
+def field_key(a):
+    return int(a["bit_offset"])
+
+def merge_block(origin, new):
+    for newval in new:
+        found = False
+        for val in origin:
+            if val["name"] == newval["name"] and val["byte_offset"] == newval["byte_offset"]:
+                found = True
+        if not found:
+            origin.append(newval)
+    origin.sort(key=item_key)
+
+def merge_fields(origin, new):
+    for newval in new:
+        found = False
+        for val in origin:
+            if val["name"] == newval["name"] and val["bit_offset"] == newval["bit_offset"]:
+                found = True
+        if not found:
+            origin.append(newval)
+    origin.sort(key=field_key)
+
+def merge_dicts(origin, new):
+    for k, v in new.items():
+        if k in origin:
+            if type(v) is dict:
+                merge_dicts(origin[k], v)
+            elif type(v) is list:
+                if k == "items":
+                    merge_block(origin[k], v)
+                if k == "fields":
+                    merge_fields(origin[k], v)
+            else:
+                origin[k] = v
+        else:
+            origin[k] = v
+
+first=True
+reg_map={}
+for regfile in sys.argv[1:]:
+    print("Loading", regfile)
+    with open(regfile, 'r') as f:
+        y = yaml.load(f, Loader=yaml.SafeLoader)
+        merge_dicts(reg_map, y)
+
+
+with open('regs_merged.yaml', 'w') as f:
+    f.write(yaml.dump(reg_map))

parse.py

@@ -242,16 +242,26 @@ perimap = [
     ('STM32L0.*:SYS:.*', 'syscfg_l0/SYSCFG'),
     ('STM32H7.*:SYS:.*', 'syscfg_h7/SYSCFG'),
     ('STM32L0.*:RCC:.*', 'rcc_l0/RCC'),
+    ('STM32L4.*:RCC:.*', 'rcc_l4/RCC'),
+    ('STM32F4.*:RCC:.*', 'rcc_f4/RCC'),
+    ('.*:STM32H7AB_rcc_v1_0', 'rcc_h7ab/RCC'),
+    ('.*:STM32H7_rcc_v1_0', 'rcc_h7/RCC'),
     ('.*:STM32L0_dbgmcu_v1_0', 'dbg_l0/DBG'),
     ('.*:STM32L0_crs_v1_0', 'crs_l0/CRS'),
     ('.*SDMMC:sdmmc2_v1_0', 'sdmmc_v2/SDMMC'),
-    ('.*:STM32H7_rcc_v1_0', 'rcc_h7/RCC'),
     ('.*:STM32H7_pwr_v1_0', 'pwr_h7/PWR'),
     ('.*:STM32H7_flash_v1_0', 'flash_h7/FLASH'),
     ('.*:STM32H7_dbgmcu_v1_0', 'dbgmcu_h7/DBGMCU'),
     ('.*TIM\d.*:gptimer.*', 'timer_v1/TIM_GP16'),
 ]
 
+rng_clock_map = [
+    ('STM32L0.*:RNG:.*', 'AHB'),
+    ('STM32L4.*:RNG:.*', 'AHB2'),
+    ('STM32F4.*:RNG:.*', 'AHB2'),
+    ('STM32H7.*:RNG:.*', 'AHB2'),
+]
+
 
 def match_peri(peri):
     for r, block in perimap:
@@ -266,6 +276,11 @@ def find_af(gpio_af, peri_name, pin_name, signal_name):
                  return af[gpio_af][pin_name][peri_name + '_' + signal_name]
      return None
               
+def match_rng_clock(rcc):
+    for r, clock in rng_clock_map:
+        if re.match(r, rcc):
+            return clock
+    return None
 
 def parse_headers():
     os.makedirs('sources/headers_parsed', exist_ok=True)
@@ -458,6 +473,11 @@ def parse_chips():
                 if len(chip['pins'][pname]) > 0:
                     p['pins'] = chip['pins'][pname]
 
+            # RNG Clock definitions are not easily determined, so lookup in mapping
+            if block is not None and block.startswith("rng_"):
+                if (clock := match_rng_clock(chip_name+':'+pname+':'+pkind)) != None:
+                    p['clock'] = clock
+
             peris[pname] = p
 
 
@@ -599,6 +619,7 @@ def parse_clocks():
                 peripherals = peripherals.split(",")
                 for p in peripherals:
                     chip_clocks[p] = name
+
         clocks[ff] = chip_clocks
 
 

transform-RCC.yaml

@@ -1,4 +1,5 @@
 transforms:
+
   - MergeEnums:
       from: CCMR\d_Input_CC\dS
       to: CCMR_Input_CCS
@@ -10,11 +11,11 @@ transforms:
       to: $1$2$3
       skip_unmergeable: true
 
-  - MakeFieldArray:
+      #- MakeFieldArray:
-      fieldsets: .*
+      #    fieldsets: .*
-      from: ([A-Z]+)\d+
+      #    from: ([A-Z]+)\d([A-Z]*)
-      to: $1
+      #    to: $1$2
-      allow_cursed: true
+      #    allow_cursed: true
   - MakeFieldArray:
       fieldsets: .*
       from: P\d+WP
@@ -41,5 +42,23 @@ transforms:
       from: '[HL](IFCR|ISR)'
       to: $1
   - DeleteEnums:
-      from: '.*[EN]'
+      from: '.*EN'
       bit_size: 1
+  - DeleteEnums:
+      from: '.*RST'
+      bit_size: 1
+  - DeleteEnums:
+      from: '.*ON'
+      bit_size: 1
+  - MakeRegisterArray:
+      blocks: .*
+      from: PLL\d+(.*)
+      to: PLL$1
+  - MakeFieldArray:
+      fieldsets: .*
+      from: PLL\d+(.*)
+      to: PLL$1
+  - MakeFieldArray:
+      fieldsets: (PLLCFGR|PLLCKSELR)
+      from: DIV([A-Z]+)\d+([A-Z]*)
+      to: DIV$1$2