diff --git a/data/registers/rcc_f4.yaml b/data/registers/rcc_f4.yaml new file mode 100644 index 0000000..a919c9c --- /dev/null +++ b/data/registers/rcc_f4.yaml @@ -0,0 +1,2818 @@ +block/RCC: + description: Reset and clock control + items: + - byte_offset: 0 + description: clock control register + fieldset: CR + name: CR + - byte_offset: 4 + description: PLL configuration register + fieldset: PLLCFGR + name: PLLCFGR + - byte_offset: 8 + description: clock configuration register + fieldset: CFGR + name: CFGR + - byte_offset: 12 + description: clock interrupt register + fieldset: CIR + name: CIR + - byte_offset: 16 + description: AHB1 peripheral reset register + fieldset: AHB1RSTR + name: AHB1RSTR + - byte_offset: 20 + description: AHB2 peripheral reset register + fieldset: AHB2RSTR + name: AHB2RSTR + - byte_offset: 32 + description: APB1 peripheral reset register + fieldset: APB1RSTR + name: APB1RSTR + - byte_offset: 36 + description: APB2 peripheral reset register + fieldset: APB2RSTR + name: APB2RSTR + - byte_offset: 48 + description: AHB1 peripheral clock register + fieldset: AHB1ENR + name: AHB1ENR + - byte_offset: 52 + description: AHB2 peripheral clock enable register + fieldset: AHB2ENR + name: AHB2ENR + - byte_offset: 64 + description: APB1 peripheral clock enable register + fieldset: APB1ENR + name: APB1ENR + - byte_offset: 68 + description: APB2 peripheral clock enable register + fieldset: APB2ENR + name: APB2ENR + - byte_offset: 80 + description: AHB1 peripheral clock enable in low power mode register + fieldset: AHB1LPENR + name: AHB1LPENR + - byte_offset: 84 + description: AHB2 peripheral clock enable in low power mode register + fieldset: AHB2LPENR + name: AHB2LPENR + - byte_offset: 96 + description: APB1 peripheral clock enable in low power mode register + fieldset: APB1LPENR + name: APB1LPENR + - byte_offset: 100 + description: APB2 peripheral clock enabled in low power mode register + fieldset: APB2LPENR + name: APB2LPENR + - byte_offset: 112 + description: Backup domain control register + fieldset: BDCR + name: BDCR + - byte_offset: 116 + description: clock control & status register + fieldset: CSR + name: CSR + - byte_offset: 128 + description: spread spectrum clock generation register + fieldset: SSCGR + name: SSCGR + - byte_offset: 132 + description: PLLI2S configuration register + fieldset: PLLI2SCFGR + name: PLLI2SCFGR + - byte_offset: 140 + description: RCC Dedicated Clock Configuration Register + fieldset: DCKCFGR + name: DCKCFGR + - byte_offset: 24 + description: AHB3 peripheral reset register + fieldset: AHB3RSTR + name: AHB3RSTR + - byte_offset: 56 + description: AHB3 peripheral clock enable register + fieldset: AHB3ENR + name: AHB3ENR + - byte_offset: 88 + description: AHB3 peripheral clock enable in low power mode register + fieldset: AHB3LPENR + name: AHB3LPENR + - byte_offset: 148 + description: DCKCFGR2 register + fieldset: DCKCFGR2 + name: DCKCFGR2 + - byte_offset: 144 + description: Clocks gated enable register + fieldset: CKGATENR + name: CKGATENR + - byte_offset: 136 + description: RCC PLL configuration register + fieldset: PLLSAICFGR + name: PLLSAICFGR +enum/CECSEL: + bit_size: 1 + variants: + - description: LSE clock is selected as HDMI-CEC clock + name: LSE + value: 0 + - description: HSI divided by 488 clock is selected as HDMI-CEC clock + name: HSI_Div488 + value: 1 +enum/CKDFSDMASEL: + bit_size: 1 + variants: + - description: CK_I2S_APB1 selected as audio clock + name: I2S1 + value: 0 + - description: CK_I2S_APB2 selected as audio clock + name: I2S2 + value: 1 +enum/CKDFSDMSEL: + bit_size: 1 + variants: + - description: APB2 clock used as Kernel clock + name: APB2 + value: 0 + - description: System clock used as Kernel clock + name: SYSCLK + value: 1 +enum/CKMSEL: + bit_size: 1 + variants: + - description: 48MHz clock from PLL is selected + name: PLL + value: 0 + - description: 48MHz clock from PLLSAI is selected + name: PLLSAI + value: 1 +enum/CSSCW: + bit_size: 1 + variants: + - description: Clear CSSF flag + name: Clear + value: 1 +enum/CSSFR: + bit_size: 1 + variants: + - description: No clock security interrupt caused by HSE clock failure + name: NotInterrupted + value: 0 + - description: Clock security interrupt caused by HSE clock failure + name: Interrupted + value: 1 +enum/DSISEL: + bit_size: 1 + variants: + - description: DSI-PHY used as DSI byte lane clock source (usual case) + name: DSI_PHY + value: 0 + - description: PLLR used as DSI byte lane clock source, used in case DSI PLL and + DSI-PHY are off (low power mode) + name: PLLR + value: 1 +enum/FMPICSEL: + bit_size: 2 + variants: + - description: APB clock selected as I2C clock + name: APB + value: 0 + - description: System clock selected as I2C clock + name: SYSCLK + value: 1 + - description: HSI clock selected as I2C clock + name: HSI + value: 2 +enum/HPRE: + bit_size: 4 + variants: + - description: SYSCLK not divided + name: Div1 + value: 0 + - description: SYSCLK divided by 2 + name: Div2 + value: 8 + - description: SYSCLK divided by 4 + name: Div4 + value: 9 + - description: SYSCLK divided by 8 + name: Div8 + value: 10 + - description: SYSCLK divided by 16 + name: Div16 + value: 11 + - description: SYSCLK divided by 64 + name: Div64 + value: 12 + - description: SYSCLK divided by 128 + name: Div128 + value: 13 + - description: SYSCLK divided by 256 + name: Div256 + value: 14 + - description: SYSCLK divided by 512 + name: Div512 + value: 15 +enum/HSEBYP: + bit_size: 1 + variants: + - description: HSE crystal oscillator not bypassed + name: NotBypassed + value: 0 + - description: HSE crystal oscillator bypassed with external clock + name: Bypassed + value: 1 +enum/HSIRDYR: + bit_size: 1 + variants: + - description: Clock not ready + name: NotReady + value: 0 + - description: Clock ready + name: Ready + value: 1 +enum/I2S1SRC: + bit_size: 2 + variants: + - description: I2Sx clock frequency = f(PLLI2S_R) + name: PLLI2SR + value: 0 + - description: I2Sx clock frequency = I2S_CKIN Alternate function input frequency + name: I2S_CKIN + value: 1 + - description: I2Sx clock frequency = f(PLL_R) + name: PLLR + value: 2 + - description: I2Sx clock frequency = HSI/HSE depends on PLLSRC bit (PLLCFGR[22]) + name: HSI_HSE + value: 3 +enum/I2SSRC: + bit_size: 1 + variants: + - description: PLLI2S clock used as I2S clock source + name: PLLI2S + value: 0 + - description: External clock mapped on the I2S_CKIN pin used as I2S clock source + name: CKIN + value: 1 +enum/ISSRC: + bit_size: 1 + variants: + - description: PLLI2S clock used as I2S clock source + name: PLLI2S + value: 0 + - description: External clock mapped on the I2S_CKIN pin used as I2S clock source + name: CKIN + value: 1 +enum/LPTIMSEL: + bit_size: 2 + variants: + - description: APB1 clock (PCLK1) selected as LPTILM1 clock + name: APB1 + value: 0 + - description: LSI clock is selected as LPTILM1 clock + name: LSI + value: 1 + - description: HSI clock is selected as LPTILM1 clock + name: HSI + value: 2 + - description: LSE clock is selected as LPTILM1 clock + name: LSE + value: 3 +enum/LPWRRSTFR: + bit_size: 1 + variants: + - description: No reset has occured + name: NoReset + value: 0 + - description: A reset has occured + name: Reset + value: 1 +enum/LSEBYP: + bit_size: 1 + variants: + - description: LSE crystal oscillator not bypassed + name: NotBypassed + value: 0 + - description: LSE crystal oscillator bypassed with external clock + name: Bypassed + value: 1 +enum/LSEMOD: + bit_size: 1 + variants: + - description: LSE oscillator low power mode selection + name: Low + value: 0 + - description: LSE oscillator high drive mode selection + name: High + value: 1 +enum/LSERDYR: + bit_size: 1 + variants: + - description: LSE oscillator not ready + name: NotReady + value: 0 + - description: LSE oscillator ready + name: Ready + value: 1 +enum/LSIRDYR: + bit_size: 1 + variants: + - description: LSI oscillator not ready + name: NotReady + value: 0 + - description: LSI oscillator ready + name: Ready + value: 1 +enum/MCO1: + bit_size: 2 + variants: + - description: HSI clock selected + name: HSI + value: 0 + - description: LSE oscillator selected + name: LSE + value: 1 + - description: HSE oscillator clock selected + name: HSE + value: 2 + - description: PLL clock selected + name: PLL + value: 3 +enum/MCO2: + bit_size: 2 + variants: + - description: System clock (SYSCLK) selected + name: SYSCLK + value: 0 + - description: PLLI2S clock selected + name: PLLI2S + value: 1 + - description: HSE oscillator clock selected + name: HSE + value: 2 + - description: PLL clock selected + name: PLL + value: 3 +enum/MCOPRE: + bit_size: 3 + variants: + - description: No division + name: Div1 + value: 0 + - description: Division by 2 + name: Div2 + value: 4 + - description: Division by 3 + name: Div3 + value: 5 + - description: Division by 4 + name: Div4 + value: 6 + - description: Division by 5 + name: Div5 + value: 7 +enum/PLLDIVR: + bit_size: 5 + variants: + - description: PLLSAIDIVQ = /1 + name: Div1 + value: 0 + - description: PLLSAIDIVQ = /2 + name: Div2 + value: 1 + - description: PLLSAIDIVQ = /3 + name: Div3 + value: 2 + - description: PLLSAIDIVQ = /4 + name: Div4 + value: 3 + - description: PLLSAIDIVQ = /5 + name: Div5 + value: 4 + - description: PLLSAIDIVQ = /6 + name: Div6 + value: 5 + - description: PLLSAIDIVQ = /7 + name: Div7 + value: 6 + - description: PLLSAIDIVQ = /8 + name: Div8 + value: 7 + - description: PLLSAIDIVQ = /9 + name: Div9 + value: 8 + - description: PLLSAIDIVQ = /10 + name: Div10 + value: 9 + - description: PLLSAIDIVQ = /11 + name: Div11 + value: 10 + - description: PLLSAIDIVQ = /12 + name: Div12 + value: 11 + - description: PLLSAIDIVQ = /13 + name: Div13 + value: 12 + - description: PLLSAIDIVQ = /14 + name: Div14 + value: 13 + - description: PLLSAIDIVQ = /15 + name: Div15 + value: 14 + - description: PLLSAIDIVQ = /16 + name: Div16 + value: 15 + - description: PLLSAIDIVQ = /17 + name: Div17 + value: 16 + - description: PLLSAIDIVQ = /18 + name: Div18 + value: 17 + - description: PLLSAIDIVQ = /19 + name: Div19 + value: 18 + - description: PLLSAIDIVQ = /20 + name: Div20 + value: 19 + - description: PLLSAIDIVQ = /21 + name: Div21 + value: 20 + - description: PLLSAIDIVQ = /22 + name: Div22 + value: 21 + - description: PLLSAIDIVQ = /23 + name: Div23 + value: 22 + - description: PLLSAIDIVQ = /24 + name: Div24 + value: 23 + - description: PLLSAIDIVQ = /25 + name: Div25 + value: 24 + - description: PLLSAIDIVQ = /26 + name: Div26 + value: 25 + - description: PLLSAIDIVQ = /27 + name: Div27 + value: 26 + - description: PLLSAIDIVQ = /28 + name: Div28 + value: 27 + - description: PLLSAIDIVQ = /29 + name: Div29 + value: 28 + - description: PLLSAIDIVQ = /30 + name: Div30 + value: 29 + - description: PLLSAIDIVQ = /31 + name: Div31 + value: 30 + - description: PLLSAIDIVQ = /32 + name: Div32 + value: 31 +enum/PLLISDIVQ: + bit_size: 5 + variants: + - description: PLLI2SDIVQ = /1 + name: Div1 + value: 0 + - description: PLLI2SDIVQ = /2 + name: Div2 + value: 1 + - description: PLLI2SDIVQ = /3 + name: Div3 + value: 2 + - description: PLLI2SDIVQ = /4 + name: Div4 + value: 3 + - description: PLLI2SDIVQ = /5 + name: Div5 + value: 4 + - description: PLLI2SDIVQ = /6 + name: Div6 + value: 5 + - description: PLLI2SDIVQ = /7 + name: Div7 + value: 6 + - description: PLLI2SDIVQ = /8 + name: Div8 + value: 7 + - description: PLLI2SDIVQ = /9 + name: Div9 + value: 8 + - description: PLLI2SDIVQ = /10 + name: Div10 + value: 9 + - description: PLLI2SDIVQ = /11 + name: Div11 + value: 10 + - description: PLLI2SDIVQ = /12 + name: Div12 + value: 11 + - description: PLLI2SDIVQ = /13 + name: Div13 + value: 12 + - description: PLLI2SDIVQ = /14 + name: Div14 + value: 13 + - description: PLLI2SDIVQ = /15 + name: Div15 + value: 14 + - description: PLLI2SDIVQ = /16 + name: Div16 + value: 15 + - description: PLLI2SDIVQ = /17 + name: Div17 + value: 16 + - description: PLLI2SDIVQ = /18 + name: Div18 + value: 17 + - description: PLLI2SDIVQ = /19 + name: Div19 + value: 18 + - description: PLLI2SDIVQ = /20 + name: Div20 + value: 19 + - description: PLLI2SDIVQ = /21 + name: Div21 + value: 20 + - description: PLLI2SDIVQ = /22 + name: Div22 + value: 21 + - description: PLLI2SDIVQ = /23 + name: Div23 + value: 22 + - description: PLLI2SDIVQ = /24 + name: Div24 + value: 23 + - description: PLLI2SDIVQ = /25 + name: Div25 + value: 24 + - description: PLLI2SDIVQ = /26 + name: Div26 + value: 25 + - description: PLLI2SDIVQ = /27 + name: Div27 + value: 26 + - description: PLLI2SDIVQ = /28 + name: Div28 + value: 27 + - description: PLLI2SDIVQ = /29 + name: Div29 + value: 28 + - description: PLLI2SDIVQ = /30 + name: Div30 + value: 29 + - description: PLLI2SDIVQ = /31 + name: Div31 + value: 30 + - description: PLLI2SDIVQ = /32 + name: Div32 + value: 31 +enum/PLLISDIVR: + bit_size: 5 + variants: + - description: PLLI2SDIVQ = /1 + name: Div1 + value: 0 + - description: PLLI2SDIVQ = /2 + name: Div2 + value: 1 + - description: PLLI2SDIVQ = /3 + name: Div3 + value: 2 + - description: PLLI2SDIVQ = /4 + name: Div4 + value: 3 + - description: PLLI2SDIVQ = /5 + name: Div5 + value: 4 + - description: PLLI2SDIVQ = /6 + name: Div6 + value: 5 + - description: PLLI2SDIVQ = /7 + name: Div7 + value: 6 + - description: PLLI2SDIVQ = /8 + name: Div8 + value: 7 + - description: PLLI2SDIVQ = /9 + name: Div9 + value: 8 + - description: PLLI2SDIVQ = /10 + name: Div10 + value: 9 + - description: PLLI2SDIVQ = /11 + name: Div11 + value: 10 + - description: PLLI2SDIVQ = /12 + name: Div12 + value: 11 + - description: PLLI2SDIVQ = /13 + name: Div13 + value: 12 + - description: PLLI2SDIVQ = /14 + name: Div14 + value: 13 + - description: PLLI2SDIVQ = /15 + name: Div15 + value: 14 + - description: PLLI2SDIVQ = /16 + name: Div16 + value: 15 + - description: PLLI2SDIVQ = /17 + name: Div17 + value: 16 + - description: PLLI2SDIVQ = /18 + name: Div18 + value: 17 + - description: PLLI2SDIVQ = /19 + name: Div19 + value: 18 + - description: PLLI2SDIVQ = /20 + name: Div20 + value: 19 + - description: PLLI2SDIVQ = /21 + name: Div21 + value: 20 + - description: PLLI2SDIVQ = /22 + name: Div22 + value: 21 + - description: PLLI2SDIVQ = /23 + name: Div23 + value: 22 + - description: PLLI2SDIVQ = /24 + name: Div24 + value: 23 + - description: PLLI2SDIVQ = /25 + name: Div25 + value: 24 + - description: PLLI2SDIVQ = /26 + name: Div26 + value: 25 + - description: PLLI2SDIVQ = /27 + name: Div27 + value: 26 + - description: PLLI2SDIVQ = /28 + name: Div28 + value: 27 + - description: PLLI2SDIVQ = /29 + name: Div29 + value: 28 + - description: PLLI2SDIVQ = /30 + name: Div30 + value: 29 + - description: PLLI2SDIVQ = /31 + name: Div31 + value: 30 + - description: PLLI2SDIVQ = /32 + name: Div32 + value: 31 +enum/PLLISP: + bit_size: 2 + variants: + - description: PLL*P=2 + name: Div2 + value: 0 + - description: PLL*P=4 + name: Div4 + value: 1 + - description: PLL*P=6 + name: Div6 + value: 2 + - description: PLL*P=8 + name: Div8 + value: 3 +enum/PLLISRDYCW: + bit_size: 1 + variants: + - description: Clear interrupt flag + name: Clear + value: 1 +enum/PLLISRDYFR: + bit_size: 1 + variants: + - description: No clock ready interrupt + name: NotInterrupted + value: 0 + - description: Clock ready interrupt + name: Interrupted + value: 1 +enum/PLLISRDYIE: + bit_size: 1 + variants: + - description: Interrupt disabled + name: Disabled + value: 0 + - description: Interrupt enabled + name: Enabled + value: 1 +enum/PLLISRDYR: + bit_size: 1 + variants: + - description: Clock not ready + name: NotReady + value: 0 + - description: Clock ready + name: Ready + value: 1 +enum/PLLISSRC: + bit_size: 1 + variants: + - description: HSE or HSI depending on PLLSRC of PLLCFGR + name: HSE_HSI + value: 0 + - description: External AFI clock (CK_PLLI2S_EXT) selected as PLL clock entry + name: External + value: 1 +enum/PLLP: + bit_size: 2 + variants: + - description: PLLP=2 + name: Div2 + value: 0 + - description: PLLP=4 + name: Div4 + value: 1 + - description: PLLP=6 + name: Div6 + value: 2 + - description: PLLP=8 + name: Div8 + value: 3 +enum/PLLRDYFR: + bit_size: 1 + variants: + - description: No clock ready interrupt + name: NotInterrupted + value: 0 + - description: Clock ready interrupt + name: Interrupted + value: 1 +enum/PLLRDYIE: + bit_size: 1 + variants: + - description: Interrupt disabled + name: Disabled + value: 0 + - description: Interrupt enabled + name: Enabled + value: 1 +enum/PLLRDYR: + bit_size: 1 + variants: + - description: Clock not ready + name: NotReady + value: 0 + - description: Clock ready + name: Ready + value: 1 +enum/PLLSAIDIVQ: + bit_size: 5 + variants: + - description: PLLSAIDIVQ = /1 + name: Div1 + value: 0 + - description: PLLSAIDIVQ = /2 + name: Div2 + value: 1 + - description: PLLSAIDIVQ = /3 + name: Div3 + value: 2 + - description: PLLSAIDIVQ = /4 + name: Div4 + value: 3 + - description: PLLSAIDIVQ = /5 + name: Div5 + value: 4 + - description: PLLSAIDIVQ = /6 + name: Div6 + value: 5 + - description: PLLSAIDIVQ = /7 + name: Div7 + value: 6 + - description: PLLSAIDIVQ = /8 + name: Div8 + value: 7 + - description: PLLSAIDIVQ = /9 + name: Div9 + value: 8 + - description: PLLSAIDIVQ = /10 + name: Div10 + value: 9 + - description: PLLSAIDIVQ = /11 + name: Div11 + value: 10 + - description: PLLSAIDIVQ = /12 + name: Div12 + value: 11 + - description: PLLSAIDIVQ = /13 + name: Div13 + value: 12 + - description: PLLSAIDIVQ = /14 + name: Div14 + value: 13 + - description: PLLSAIDIVQ = /15 + name: Div15 + value: 14 + - description: PLLSAIDIVQ = /16 + name: Div16 + value: 15 + - description: PLLSAIDIVQ = /17 + name: Div17 + value: 16 + - description: PLLSAIDIVQ = /18 + name: Div18 + value: 17 + - description: PLLSAIDIVQ = /19 + name: Div19 + value: 18 + - description: PLLSAIDIVQ = /20 + name: Div20 + value: 19 + - description: PLLSAIDIVQ = /21 + name: Div21 + value: 20 + - description: PLLSAIDIVQ = /22 + name: Div22 + value: 21 + - description: PLLSAIDIVQ = /23 + name: Div23 + value: 22 + - description: PLLSAIDIVQ = /24 + name: Div24 + value: 23 + - description: PLLSAIDIVQ = /25 + name: Div25 + value: 24 + - description: PLLSAIDIVQ = /26 + name: Div26 + value: 25 + - description: PLLSAIDIVQ = /27 + name: Div27 + value: 26 + - description: PLLSAIDIVQ = /28 + name: Div28 + value: 27 + - description: PLLSAIDIVQ = /29 + name: Div29 + value: 28 + - description: PLLSAIDIVQ = /30 + name: Div30 + value: 29 + - description: PLLSAIDIVQ = /31 + name: Div31 + value: 30 + - description: PLLSAIDIVQ = /32 + name: Div32 + value: 31 +enum/PLLSAIDIVR: + bit_size: 2 + variants: + - description: PLLSAIDIVR = /2 + name: Div2 + value: 0 + - description: PLLSAIDIVR = /4 + name: Div4 + value: 1 + - description: PLLSAIDIVR = /8 + name: Div8 + value: 2 + - description: PLLSAIDIVR = /16 + name: Div16 + value: 3 +enum/PLLSAIP: + bit_size: 2 + variants: + - description: PLL*P=2 + name: Div2 + value: 0 + - description: PLL*P=4 + name: Div4 + value: 1 + - description: PLL*P=6 + name: Div6 + value: 2 + - description: PLL*P=8 + name: Div8 + value: 3 +enum/PLLSAIRDYCW: + bit_size: 1 + variants: + - description: Clear interrupt flag + name: Clear + value: 1 +enum/PLLSAIRDYFR: + bit_size: 1 + variants: + - description: No clock ready interrupt + name: NotInterrupted + value: 0 + - description: Clock ready interrupt + name: Interrupted + value: 1 +enum/PLLSAIRDYIE: + bit_size: 1 + variants: + - description: Interrupt disabled + name: Disabled + value: 0 + - description: Interrupt enabled + name: Enabled + value: 1 +enum/PLLSRC: + bit_size: 1 + variants: + - description: HSI clock selected as PLL and PLLI2S clock entry + name: HSI + value: 0 + - description: HSE oscillator clock selected as PLL and PLLI2S clock entry + name: HSE + value: 1 +enum/PPRE: + bit_size: 3 + variants: + - description: HCLK not divided + name: Div1 + value: 0 + - description: HCLK divided by 2 + name: Div2 + value: 4 + - description: HCLK divided by 4 + name: Div4 + value: 5 + - description: HCLK divided by 8 + name: Div8 + value: 6 + - description: HCLK divided by 16 + name: Div16 + value: 7 +enum/RMVFW: + bit_size: 1 + variants: + - description: Clears the reset flag + name: Clear + value: 1 +enum/RTCSEL: + bit_size: 2 + variants: + - description: No clock + name: NoClock + value: 0 + - description: LSE oscillator clock used as RTC clock + name: LSE + value: 1 + - description: LSI oscillator clock used as RTC clock + name: LSI + value: 2 + - description: HSE oscillator clock divided by a prescaler used as RTC clock + name: HSE + value: 3 +enum/SAI1SRC: + bit_size: 2 + variants: + - description: SAI1 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ + name: PLLSAI + value: 0 + - description: SAI1 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ + name: PLLI2S + value: 1 + - description: SAI1 clock frequency = f(PLL_R) + name: PLLR + value: 2 + - description: I2S_CKIN Alternate function input frequency + name: I2S_CKIN + value: 3 +enum/SAI2SRC: + bit_size: 2 + variants: + - description: SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ + name: PLLSAI + value: 0 + - description: SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ + name: PLLI2S + value: 1 + - description: SAI2 clock frequency = f(PLL_R) + name: PLLR + value: 2 + - description: SAI2 clock frequency = Alternate function input frequency + name: HSI_HSE + value: 3 +enum/SAIASRC: + bit_size: 2 + variants: + - description: SAI1-A clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ + name: PLLSAI + value: 0 + - description: SAI1-A clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ + name: PLLI2S + value: 1 + - description: SAI1-A clock frequency = Alternate function input frequency + name: I2S_CKIN + value: 2 +enum/SAIBSRC: + bit_size: 2 + variants: + - description: SAI1-B clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ + name: PLLSAI + value: 0 + - description: SAI1-B clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ + name: PLLI2S + value: 1 + - description: SAI1-B clock frequency = Alternate function input frequency + name: I2S_CKIN + value: 2 +enum/SDIOSEL: + bit_size: 1 + variants: + - description: 48 MHz clock is selected as SD clock + name: CK48M + value: 0 + - description: System clock is selected as SD clock + name: SYSCLK + value: 1 +enum/SPDIFRXSEL: + bit_size: 1 + variants: + - description: SPDIF-Rx clock from PLL is selected + name: PLL + value: 0 + - description: SPDIF-Rx clock from PLLI2S is selected + name: PLLI2S + value: 1 +enum/SPREADSEL: + bit_size: 1 + variants: + - description: Center spread + name: Center + value: 0 + - description: Down spread + name: Down + value: 1 +enum/SW: + bit_size: 2 + variants: + - description: HSI selected as system clock + name: HSI + value: 0 + - description: HSE selected as system clock + name: HSE + value: 1 + - description: PLL selected as system clock + name: PLL + value: 2 +enum/SWSR: + bit_size: 2 + variants: + - description: HSI oscillator used as system clock + name: HSI + value: 0 + - description: HSE oscillator used as system clock + name: HSE + value: 1 + - description: PLL used as system clock + name: PLL + value: 2 +enum/TIMPRE: + bit_size: 1 + variants: + - description: If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, + TIMxCLK = 2xPCLKx + name: Mul2 + value: 0 + - description: If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, + TIMxCLK = 4xPCLKx + name: Mul4 + value: 1 +fieldset/AHB1ENR: + description: AHB1 peripheral clock register + fields: + - bit_offset: 0 + bit_size: 1 + description: IO port A clock enable + name: GPIOAEN + - bit_offset: 1 + bit_size: 1 + description: IO port B clock enable + name: GPIOBEN + - bit_offset: 2 + bit_size: 1 + description: IO port C clock enable + name: GPIOCEN + - bit_offset: 3 + bit_size: 1 + description: IO port D clock enable + name: GPIODEN + - bit_offset: 4 + bit_size: 1 + description: IO port E clock enable + name: GPIOEEN + - bit_offset: 7 + bit_size: 1 + description: IO port H clock enable + name: GPIOHEN + - bit_offset: 12 + bit_size: 1 + description: CRC clock enable + name: CRCEN + - bit_offset: 21 + bit_size: 1 + description: DMA1 clock enable + name: DMA1EN + - bit_offset: 22 + bit_size: 1 + description: DMA2 clock enable + name: DMA2EN + - bit_offset: 5 + bit_size: 1 + description: IO port F clock enable + name: GPIOFEN + - bit_offset: 6 + bit_size: 1 + description: IO port G clock enable + name: GPIOGEN + - bit_offset: 8 + bit_size: 1 + description: IO port I clock enable + name: GPIOIEN + - bit_offset: 18 + bit_size: 1 + description: Backup SRAM interface clock enable + name: BKPSRAMEN + - bit_offset: 25 + bit_size: 1 + description: Ethernet MAC clock enable + name: ETHMACEN + - bit_offset: 26 + bit_size: 1 + description: Ethernet Transmission clock enable + name: ETHMACTXEN + - bit_offset: 27 + bit_size: 1 + description: Ethernet Reception clock enable + name: ETHMACRXEN + - bit_offset: 28 + bit_size: 1 + description: Ethernet PTP clock enable + name: ETHMACPTPEN + - bit_offset: 29 + bit_size: 1 + description: USB OTG HS clock enable + name: OTGHSEN + - bit_offset: 30 + bit_size: 1 + description: USB OTG HSULPI clock enable + name: OTGHSULPIEN + - bit_offset: 31 + bit_size: 1 + description: RNG clock enable + name: RNGEN + - bit_offset: 9 + bit_size: 1 + description: IO port J clock enable + name: GPIOJEN + - bit_offset: 10 + bit_size: 1 + description: IO port K clock enable + name: GPIOKEN + - bit_offset: 23 + bit_size: 1 + description: DMA2D clock enable + name: DMA2DEN + - bit_offset: 20 + bit_size: 1 + description: CCM data RAM clock enable + name: CCMDATARAMEN +fieldset/AHB1LPENR: + description: AHB1 peripheral clock enable in low power mode register + fields: + - bit_offset: 0 + bit_size: 1 + description: IO port A clock enable during sleep mode + name: GPIOALPEN + - bit_offset: 1 + bit_size: 1 + description: IO port B clock enable during Sleep mode + name: GPIOBLPEN + - bit_offset: 2 + bit_size: 1 + description: IO port C clock enable during Sleep mode + name: GPIOCLPEN + - bit_offset: 3 + bit_size: 1 + description: IO port D clock enable during Sleep mode + name: GPIODLPEN + - bit_offset: 4 + bit_size: 1 + description: IO port E clock enable during Sleep mode + name: GPIOELPEN + - bit_offset: 7 + bit_size: 1 + description: IO port H clock enable during Sleep mode + name: GPIOHLPEN + - bit_offset: 12 + bit_size: 1 + description: CRC clock enable during Sleep mode + name: CRCLPEN + - bit_offset: 15 + bit_size: 1 + description: Flash interface clock enable during Sleep mode + name: FLITFLPEN + - bit_offset: 16 + bit_size: 1 + description: SRAM 1interface clock enable during Sleep mode + name: SRAM1LPEN + - bit_offset: 21 + bit_size: 1 + description: DMA1 clock enable during Sleep mode + name: DMA1LPEN + - bit_offset: 22 + bit_size: 1 + description: DMA2 clock enable during Sleep mode + name: DMA2LPEN + - bit_offset: 5 + bit_size: 1 + description: IO port F clock enable during Sleep mode + name: GPIOFLPEN + - bit_offset: 6 + bit_size: 1 + description: IO port G clock enable during Sleep mode + name: GPIOGLPEN + - bit_offset: 8 + bit_size: 1 + description: IO port I clock enable during Sleep mode + name: GPIOILPEN + - bit_offset: 17 + bit_size: 1 + description: SRAM 2 interface clock enable during Sleep mode + name: SRAM2LPEN + - bit_offset: 18 + bit_size: 1 + description: Backup SRAM interface clock enable during Sleep mode + name: BKPSRAMLPEN + - bit_offset: 25 + bit_size: 1 + description: Ethernet MAC clock enable during Sleep mode + name: ETHMACLPEN + - bit_offset: 26 + bit_size: 1 + description: Ethernet transmission clock enable during Sleep mode + name: ETHMACTXLPEN + - bit_offset: 27 + bit_size: 1 + description: Ethernet reception clock enable during Sleep mode + name: ETHMACRXLPEN + - bit_offset: 28 + bit_size: 1 + description: Ethernet PTP clock enable during Sleep mode + name: ETHMACPTPLPEN + - bit_offset: 29 + bit_size: 1 + description: USB OTG HS clock enable during Sleep mode + name: OTGHSLPEN + - bit_offset: 30 + bit_size: 1 + description: USB OTG HS ULPI clock enable during Sleep mode + name: OTGHSULPILPEN + - bit_offset: 31 + bit_size: 1 + description: RNG clock enable during sleep mode + name: RNGLPEN + - bit_offset: 9 + bit_size: 1 + description: IO port J clock enable during Sleep mode + name: GPIOJLPEN + - bit_offset: 10 + bit_size: 1 + description: IO port K clock enable during Sleep mode + name: GPIOKLPEN + - bit_offset: 19 + bit_size: 1 + description: SRAM 3 interface clock enable during Sleep mode + name: SRAM3LPEN + - bit_offset: 23 + bit_size: 1 + description: DMA2D clock enable during Sleep mode + name: DMA2DLPEN +fieldset/AHB1RSTR: + description: AHB1 peripheral reset register + fields: + - bit_offset: 0 + bit_size: 1 + description: IO port A reset + name: GPIOARST + - bit_offset: 1 + bit_size: 1 + description: IO port B reset + name: GPIOBRST + - bit_offset: 2 + bit_size: 1 + description: IO port C reset + name: GPIOCRST + - bit_offset: 3 + bit_size: 1 + description: IO port D reset + name: GPIODRST + - bit_offset: 4 + bit_size: 1 + description: IO port E reset + name: GPIOERST + - bit_offset: 7 + bit_size: 1 + description: IO port H reset + name: GPIOHRST + - bit_offset: 12 + bit_size: 1 + description: CRC reset + name: CRCRST + - bit_offset: 21 + bit_size: 1 + description: DMA2 reset + name: DMA1RST + - bit_offset: 22 + bit_size: 1 + description: DMA2 reset + name: DMA2RST + - bit_offset: 5 + bit_size: 1 + description: IO port F reset + name: GPIOFRST + - bit_offset: 6 + bit_size: 1 + description: IO port G reset + name: GPIOGRST + - bit_offset: 8 + bit_size: 1 + description: IO port I reset + name: GPIOIRST + - bit_offset: 25 + bit_size: 1 + description: Ethernet MAC reset + name: ETHMACRST + - bit_offset: 29 + bit_size: 1 + description: USB OTG HS module reset + name: OTGHSRST + - bit_offset: 31 + bit_size: 1 + description: RNGRST + name: RNGRST + - bit_offset: 9 + bit_size: 1 + description: IO port J reset + name: GPIOJRST + - bit_offset: 10 + bit_size: 1 + description: IO port K reset + name: GPIOKRST + - bit_offset: 23 + bit_size: 1 + description: DMA2D reset + name: DMA2DRST +fieldset/AHB2ENR: + description: AHB2 peripheral clock enable register + fields: + - bit_offset: 7 + bit_size: 1 + description: USB OTG FS clock enable + name: OTGFSEN + - bit_offset: 0 + bit_size: 1 + description: Camera interface enable + name: DCMIEN + - bit_offset: 6 + bit_size: 1 + description: Random number generator clock enable + name: RNGEN + - bit_offset: 4 + bit_size: 1 + description: CRYP clock enable + name: CRYPEN + - bit_offset: 5 + bit_size: 1 + description: Hash modules clock enable + name: HASHEN +fieldset/AHB2LPENR: + description: AHB2 peripheral clock enable in low power mode register + fields: + - bit_offset: 7 + bit_size: 1 + description: USB OTG FS clock enable during Sleep mode + name: OTGFSLPEN + - bit_offset: 0 + bit_size: 1 + description: Camera interface enable during Sleep mode + name: DCMILPEN + - bit_offset: 6 + bit_size: 1 + description: Random number generator clock enable during Sleep mode + name: RNGLPEN + - bit_offset: 0 + bit_size: 1 + description: Flexible memory controller module clock enable during Sleep mode + name: FSMCLPEN + - bit_offset: 1 + bit_size: 1 + description: QUADSPI memory controller module clock enable during Sleep mode + name: QSPILPEN + - bit_offset: 4 + bit_size: 1 + description: Cryptography modules clock enable during Sleep mode + name: CRYPLPEN + - bit_offset: 5 + bit_size: 1 + description: Hash modules clock enable during Sleep mode + name: HASHLPEN +fieldset/AHB2RSTR: + description: AHB2 peripheral reset register + fields: + - bit_offset: 7 + bit_size: 1 + description: USB OTG FS module reset + name: OTGFSRST + - bit_offset: 0 + bit_size: 1 + description: Camera interface reset + name: DCMIRST + - bit_offset: 6 + bit_size: 1 + description: Random number generator module reset + name: RNGRST + - bit_offset: 4 + bit_size: 1 + description: CRYP module reset + name: CRYPRST + - bit_offset: 5 + bit_size: 1 + description: Hash module reset + name: HSAHRST +fieldset/AHB3ENR: + description: AHB3 peripheral clock enable register + fields: + - bit_offset: 0 + bit_size: 1 + description: Flexible static memory controller module clock enable + name: FSMCEN + - bit_offset: 1 + bit_size: 1 + description: QUADSPI memory controller module clock enable + name: QSPIEN + - bit_offset: 0 + bit_size: 1 + description: Flexible static memory controller module clock enable + name: FMCEN +fieldset/AHB3LPENR: + description: AHB3 peripheral clock enable in low power mode register + fields: + - bit_offset: 0 + bit_size: 1 + description: Flexible static memory controller module clock enable during Sleep + mode + name: FSMCLPEN + - bit_offset: 1 + bit_size: 1 + description: QUADSPI memory controller module clock enable during Sleep mode + name: QSPILPEN + - bit_offset: 0 + bit_size: 1 + description: Flexible static memory controller module clock enable during Sleep + mode + name: FMCLPEN +fieldset/AHB3RSTR: + description: AHB3 peripheral reset register + fields: + - bit_offset: 0 + bit_size: 1 + description: Flexible static memory controller module reset + name: FSMCRST + - bit_offset: 1 + bit_size: 1 + description: QUADSPI module reset + name: QSPIRST + - bit_offset: 0 + bit_size: 1 + description: Flexible static memory controller module reset + name: FMCRST +fieldset/APB1ENR: + description: APB1 peripheral clock enable register + fields: + - bit_offset: 0 + bit_size: 1 + description: TIM2 clock enable + name: TIM2EN + - bit_offset: 1 + bit_size: 1 + description: TIM3 clock enable + name: TIM3EN + - bit_offset: 2 + bit_size: 1 + description: TIM4 clock enable + name: TIM4EN + - bit_offset: 3 + bit_size: 1 + description: TIM5 clock enable + name: TIM5EN + - bit_offset: 11 + bit_size: 1 + description: Window watchdog clock enable + name: WWDGEN + - bit_offset: 14 + bit_size: 1 + description: SPI2 clock enable + name: SPI2EN + - bit_offset: 15 + bit_size: 1 + description: SPI3 clock enable + name: SPI3EN + - bit_offset: 17 + bit_size: 1 + description: USART 2 clock enable + name: USART2EN + - bit_offset: 21 + bit_size: 1 + description: I2C1 clock enable + name: I2C1EN + - bit_offset: 22 + bit_size: 1 + description: I2C2 clock enable + name: I2C2EN + - bit_offset: 23 + bit_size: 1 + description: I2C3 clock enable + name: I2C3EN + - bit_offset: 28 + bit_size: 1 + description: Power interface clock enable + name: PWREN + - bit_offset: 4 + bit_size: 1 + description: TIM6 clock enable + name: TIM6EN + - bit_offset: 5 + bit_size: 1 + description: TIM7 clock enable + name: TIM7EN + - bit_offset: 6 + bit_size: 1 + description: TIM12 clock enable + name: TIM12EN + - bit_offset: 7 + bit_size: 1 + description: TIM13 clock enable + name: TIM13EN + - bit_offset: 8 + bit_size: 1 + description: TIM14 clock enable + name: TIM14EN + - bit_offset: 18 + bit_size: 1 + description: USART3 clock enable + name: USART3EN + - bit_offset: 19 + bit_size: 1 + description: UART4 clock enable + name: UART4EN + - bit_offset: 20 + bit_size: 1 + description: UART5 clock enable + name: UART5EN + - bit_offset: 25 + bit_size: 1 + description: CAN 1 clock enable + name: CAN1EN + - bit_offset: 26 + bit_size: 1 + description: CAN 2 clock enable + name: CAN2EN + - bit_offset: 29 + bit_size: 1 + description: DAC interface clock enable + name: DACEN + - bit_offset: 9 + bit_size: 1 + description: LPTIM1 clock enable + name: LPTIM1EN + - bit_offset: 10 + bit_size: 1 + description: RTC APB clock enable + name: RTCAPBEN + - bit_offset: 24 + bit_size: 1 + description: FMPI2C1 clock enable + name: FMPI2C1EN + - bit_offset: 9 + bit_size: 1 + description: LPTimer 1 clock enable + name: LPTIMER1EN + - bit_offset: 27 + bit_size: 1 + description: CAN 3 clock enable + name: CAN3EN + - bit_offset: 30 + bit_size: 1 + description: UART7 clock enable + name: UART7EN + - bit_offset: 31 + bit_size: 1 + description: UART8 clock enable + name: UART8EN + - bit_offset: 16 + bit_size: 1 + description: SPDIF-IN clock enable + name: SPDIFEN + - bit_offset: 27 + bit_size: 1 + description: CEC interface clock enable + name: CECEN +fieldset/APB1LPENR: + description: APB1 peripheral clock enable in low power mode register + fields: + - bit_offset: 0 + bit_size: 1 + description: TIM2 clock enable during Sleep mode + name: TIM2LPEN + - bit_offset: 1 + bit_size: 1 + description: TIM3 clock enable during Sleep mode + name: TIM3LPEN + - bit_offset: 2 + bit_size: 1 + description: TIM4 clock enable during Sleep mode + name: TIM4LPEN + - bit_offset: 3 + bit_size: 1 + description: TIM5 clock enable during Sleep mode + name: TIM5LPEN + - bit_offset: 11 + bit_size: 1 + description: Window watchdog clock enable during Sleep mode + name: WWDGLPEN + - bit_offset: 14 + bit_size: 1 + description: SPI2 clock enable during Sleep mode + name: SPI2LPEN + - bit_offset: 15 + bit_size: 1 + description: SPI3 clock enable during Sleep mode + name: SPI3LPEN + - bit_offset: 17 + bit_size: 1 + description: USART2 clock enable during Sleep mode + name: USART2LPEN + - bit_offset: 21 + bit_size: 1 + description: I2C1 clock enable during Sleep mode + name: I2C1LPEN + - bit_offset: 22 + bit_size: 1 + description: I2C2 clock enable during Sleep mode + name: I2C2LPEN + - bit_offset: 23 + bit_size: 1 + description: I2C3 clock enable during Sleep mode + name: I2C3LPEN + - bit_offset: 28 + bit_size: 1 + description: Power interface clock enable during Sleep mode + name: PWRLPEN + - bit_offset: 4 + bit_size: 1 + description: TIM6 clock enable during Sleep mode + name: TIM6LPEN + - bit_offset: 5 + bit_size: 1 + description: TIM7 clock enable during Sleep mode + name: TIM7LPEN + - bit_offset: 6 + bit_size: 1 + description: TIM12 clock enable during Sleep mode + name: TIM12LPEN + - bit_offset: 7 + bit_size: 1 + description: TIM13 clock enable during Sleep mode + name: TIM13LPEN + - bit_offset: 8 + bit_size: 1 + description: TIM14 clock enable during Sleep mode + name: TIM14LPEN + - bit_offset: 18 + bit_size: 1 + description: USART3 clock enable during Sleep mode + name: USART3LPEN + - bit_offset: 19 + bit_size: 1 + description: UART4 clock enable during Sleep mode + name: UART4LPEN + - bit_offset: 20 + bit_size: 1 + description: UART5 clock enable during Sleep mode + name: UART5LPEN + - bit_offset: 25 + bit_size: 1 + description: CAN 1 clock enable during Sleep mode + name: CAN1LPEN + - bit_offset: 26 + bit_size: 1 + description: CAN 2 clock enable during Sleep mode + name: CAN2LPEN + - bit_offset: 29 + bit_size: 1 + description: DAC interface clock enable during Sleep mode + name: DACLPEN + - bit_offset: 9 + bit_size: 1 + description: LPTIM1 clock enable during sleep mode + name: LPTIM1LPEN + - bit_offset: 10 + bit_size: 1 + description: RTC APB clock enable during sleep mode + name: RTCAPBLPEN + - bit_offset: 24 + bit_size: 1 + description: FMPI2C1 clock enable during Sleep + name: FMPI2C1LPEN + - bit_offset: 9 + bit_size: 1 + description: TIM14 clock enable during Sleep mode + name: LPTIMER1LPEN + - bit_offset: 19 + bit_size: 1 + description: USART4 clock enable during Sleep mode + name: USART4LPEN + - bit_offset: 20 + bit_size: 1 + description: USART5 clock enable during Sleep mode + name: USART5LPEN + - bit_offset: 27 + bit_size: 1 + description: CAN3 clock enable during Sleep mode + name: CAN3LPEN + - bit_offset: 30 + bit_size: 1 + description: UART7 clock enable during Sleep mode + name: UART7LPEN + - bit_offset: 31 + bit_size: 1 + description: UART8 clock enable during Sleep mode + name: UART8LPEN + - bit_offset: 16 + bit_size: 1 + description: SPDIF clock enable during Sleep mode + name: SPDIFLPEN + - bit_offset: 27 + bit_size: 1 + description: CEC clock enable during Sleep mode + name: CECLPEN +fieldset/APB1RSTR: + description: APB1 peripheral reset register + fields: + - bit_offset: 0 + bit_size: 1 + description: TIM2 reset + name: TIM2RST + - bit_offset: 1 + bit_size: 1 + description: TIM3 reset + name: TIM3RST + - bit_offset: 2 + bit_size: 1 + description: TIM4 reset + name: TIM4RST + - bit_offset: 3 + bit_size: 1 + description: TIM5 reset + name: TIM5RST + - bit_offset: 11 + bit_size: 1 + description: Window watchdog reset + name: WWDGRST + - bit_offset: 14 + bit_size: 1 + description: SPI 2 reset + name: SPI2RST + - bit_offset: 15 + bit_size: 1 + description: SPI 3 reset + name: SPI3RST + - bit_offset: 17 + bit_size: 1 + description: USART 2 reset + name: UART2RST + - bit_offset: 21 + bit_size: 1 + description: I2C 1 reset + name: I2C1RST + - bit_offset: 22 + bit_size: 1 + description: I2C 2 reset + name: I2C2RST + - bit_offset: 23 + bit_size: 1 + description: I2C3 reset + name: I2C3RST + - bit_offset: 28 + bit_size: 1 + description: Power interface reset + name: PWRRST + - bit_offset: 4 + bit_size: 1 + description: TIM6 reset + name: TIM6RST + - bit_offset: 5 + bit_size: 1 + description: TIM7 reset + name: TIM7RST + - bit_offset: 6 + bit_size: 1 + description: TIM12 reset + name: TIM12RST + - bit_offset: 7 + bit_size: 1 + description: TIM13 reset + name: TIM13RST + - bit_offset: 8 + bit_size: 1 + description: TIM14 reset + name: TIM14RST + - bit_offset: 18 + bit_size: 1 + description: USART 3 reset + name: UART3RST + - bit_offset: 19 + bit_size: 1 + description: USART 4 reset + name: UART4RST + - bit_offset: 20 + bit_size: 1 + description: USART 5 reset + name: UART5RST + - bit_offset: 25 + bit_size: 1 + description: CAN1 reset + name: CAN1RST + - bit_offset: 26 + bit_size: 1 + description: CAN2 reset + name: CAN2RST + - bit_offset: 29 + bit_size: 1 + description: DAC reset + name: DACRST + - bit_offset: 9 + bit_size: 1 + description: LPTIM1 reset + name: LPTIM1RST + - bit_offset: 24 + bit_size: 1 + description: FMPI2C1 reset + name: FMPI2C1RST + - bit_offset: 18 + bit_size: 1 + description: USART3RST + name: USART3RST + - bit_offset: 9 + bit_size: 1 + description: LPTimer1 reset + name: LPTIMER1RST + - bit_offset: 19 + bit_size: 1 + description: USART4 reset + name: USART4RST + - bit_offset: 20 + bit_size: 1 + description: USART5 reset + name: USART5RST + - bit_offset: 27 + bit_size: 1 + description: CAN 3 reset + name: CAN3RST + - bit_offset: 30 + bit_size: 1 + description: UART 7 reset + name: UART7RST + - bit_offset: 31 + bit_size: 1 + description: UART 8 reset + name: UART8RST + - bit_offset: 16 + bit_size: 1 + description: SPDIF-IN reset + name: SPDIFRST +fieldset/APB2ENR: + description: APB2 peripheral clock enable register + fields: + - bit_offset: 0 + bit_size: 1 + description: TIM1 clock enable + name: TIM1EN + - bit_offset: 4 + bit_size: 1 + description: USART1 clock enable + name: USART1EN + - bit_offset: 5 + bit_size: 1 + description: USART6 clock enable + name: USART6EN + - bit_offset: 8 + bit_size: 1 + description: ADC1 clock enable + name: ADC1EN + - bit_offset: 11 + bit_size: 1 + description: SDIO clock enable + name: SDIOEN + - bit_offset: 12 + bit_size: 1 + description: SPI1 clock enable + name: SPI1EN + - bit_offset: 13 + bit_size: 1 + description: SPI4 clock enable + name: SPI4EN + - bit_offset: 14 + bit_size: 1 + description: System configuration controller clock enable + name: SYSCFGEN + - bit_offset: 16 + bit_size: 1 + description: TIM9 clock enable + name: TIM9EN + - bit_offset: 17 + bit_size: 1 + description: TIM10 clock enable + name: TIM10EN + - bit_offset: 18 + bit_size: 1 + description: TIM11 clock enable + name: TIM11EN + - bit_offset: 1 + bit_size: 1 + description: TIM8 clock enable + name: TIM8EN + - bit_offset: 9 + bit_size: 1 + description: ADC2 clock enable + name: ADC2EN + - bit_offset: 10 + bit_size: 1 + description: ADC3 clock enable + name: ADC3EN + - bit_offset: 15 + bit_size: 1 + description: EXTI ans external IT clock enable + name: EXTITEN + - bit_offset: 20 + bit_size: 1 + description: SPI5 clock enable + name: SPI5EN + - bit_offset: 24 + bit_size: 1 + description: DFSDMEN + name: DFSDMEN + - bit_offset: 6 + bit_size: 1 + description: UART9 clock enable + name: UART9EN + - bit_offset: 7 + bit_size: 1 + description: UART10 clock enable + name: UART10EN + - bit_offset: 22 + bit_size: 1 + description: SAI 1 clock enable + name: SAI1EN + - bit_offset: 25 + bit_size: 1 + description: DFSDM2 clock enable + name: DFSDM2EN + - bit_offset: 21 + bit_size: 1 + description: SPI6 clock enable + name: SPI6EN + - bit_offset: 26 + bit_size: 1 + description: LTDC clock enable + name: LTDCEN + - bit_offset: 23 + bit_size: 1 + description: SAI2 clock enable + name: SAI2EN + - bit_offset: 27 + bit_size: 1 + description: DSI clocks enable + name: DSIEN +fieldset/APB2LPENR: + description: APB2 peripheral clock enabled in low power mode register + fields: + - bit_offset: 0 + bit_size: 1 + description: TIM1 clock enable during Sleep mode + name: TIM1LPEN + - bit_offset: 4 + bit_size: 1 + description: USART1 clock enable during Sleep mode + name: USART1LPEN + - bit_offset: 5 + bit_size: 1 + description: USART6 clock enable during Sleep mode + name: USART6LPEN + - bit_offset: 8 + bit_size: 1 + description: ADC1 clock enable during Sleep mode + name: ADC1LPEN + - bit_offset: 11 + bit_size: 1 + description: SDIO clock enable during Sleep mode + name: SDIOLPEN + - bit_offset: 12 + bit_size: 1 + description: SPI 1 clock enable during Sleep mode + name: SPI1LPEN + - bit_offset: 13 + bit_size: 1 + description: SPI4 clock enable during Sleep mode + name: SPI4LPEN + - bit_offset: 14 + bit_size: 1 + description: System configuration controller clock enable during Sleep mode + name: SYSCFGLPEN + - bit_offset: 16 + bit_size: 1 + description: TIM9 clock enable during sleep mode + name: TIM9LPEN + - bit_offset: 17 + bit_size: 1 + description: TIM10 clock enable during Sleep mode + name: TIM10LPEN + - bit_offset: 18 + bit_size: 1 + description: TIM11 clock enable during Sleep mode + name: TIM11LPEN + - bit_offset: 1 + bit_size: 1 + description: TIM8 clock enable during Sleep mode + name: TIM8LPEN + - bit_offset: 9 + bit_size: 1 + description: ADC2 clock enable during Sleep mode + name: ADC2LPEN + - bit_offset: 10 + bit_size: 1 + description: ADC 3 clock enable during Sleep mode + name: ADC3LPEN + - bit_offset: 15 + bit_size: 1 + description: EXTI and External IT clock enable during sleep mode + name: EXTITLPEN + - bit_offset: 20 + bit_size: 1 + description: SPI5 clock enable during Sleep mode + name: SPI5LPEN + - bit_offset: 24 + bit_size: 1 + description: DFSDMLPEN + name: DFSDMLPEN + - bit_offset: 6 + bit_size: 1 + description: UART9 clock enable during Sleep mode + name: UART9LPEN + - bit_offset: 6 + bit_size: 1 + description: USART9 clock enable during Sleep mode + name: USART9LPEN + - bit_offset: 7 + bit_size: 1 + description: UART10 clock enable during Sleep mode + name: UART10LPEN + - bit_offset: 7 + bit_size: 1 + description: USART10 clock enable during Sleep mode + name: USART10LPEN + - bit_offset: 22 + bit_size: 1 + description: SAI1 clock enable during Sleep mode + name: SAI1LPEN + - bit_offset: 25 + bit_size: 1 + description: DFSDM2 clock enable during Sleep mode + name: DFSDM2LPEN + - bit_offset: 21 + bit_size: 1 + description: SPI 6 clock enable during Sleep mode + name: SPI6LPEN + - bit_offset: 26 + bit_size: 1 + description: LTDC clock enable during Sleep mode + name: LTDCLPEN + - bit_offset: 23 + bit_size: 1 + description: SAI2 clock enable + name: SAI2LPEN + - bit_offset: 27 + bit_size: 1 + description: DSI clocks enable during Sleep mode + name: DSILPEN +fieldset/APB2RSTR: + description: APB2 peripheral reset register + fields: + - bit_offset: 0 + bit_size: 1 + description: TIM1 reset + name: TIM1RST + - bit_offset: 4 + bit_size: 1 + description: USART1 reset + name: USART1RST + - bit_offset: 5 + bit_size: 1 + description: USART6 reset + name: USART6RST + - bit_offset: 8 + bit_size: 1 + description: ADC interface reset (common to all ADCs) + name: ADCRST + - bit_offset: 11 + bit_size: 1 + description: SDIO reset + name: SDIORST + - bit_offset: 12 + bit_size: 1 + description: SPI 1 reset + name: SPI1RST + - bit_offset: 13 + bit_size: 1 + description: SPI4 reset + name: SPI4RST + - bit_offset: 14 + bit_size: 1 + description: System configuration controller reset + name: SYSCFGRST + - bit_offset: 16 + bit_size: 1 + description: TIM9 reset + name: TIM9RST + - bit_offset: 17 + bit_size: 1 + description: TIM10 reset + name: TIM10RST + - bit_offset: 18 + bit_size: 1 + description: TIM11 reset + name: TIM11RST + - bit_offset: 1 + bit_size: 1 + description: TIM8 reset + name: TIM8RST + - bit_offset: 20 + bit_size: 1 + description: SPI5 reset + name: SPI5RST + - bit_offset: 24 + bit_size: 1 + description: DFSDMRST + name: DFSDMRST + - bit_offset: 6 + bit_size: 1 + description: UART9 reset + name: UART9RST + - bit_offset: 6 + bit_size: 1 + description: USART9 reset + name: USART9RST + - bit_offset: 7 + bit_size: 1 + description: USART10 reset + name: SART10RST + - bit_offset: 7 + bit_size: 1 + description: UART10 reset + name: UART10RST + - bit_offset: 22 + bit_size: 1 + description: SAI1 reset + name: SAI1RST + - bit_offset: 25 + bit_size: 1 + description: DFSDM2 reset + name: DFSDM2RST + - bit_offset: 21 + bit_size: 1 + description: SPI6 reset + name: SPI6RST + - bit_offset: 26 + bit_size: 1 + description: LTDC reset + name: LTDCRST + - bit_offset: 23 + bit_size: 1 + description: SAI2 reset + name: SAI2RST + - bit_offset: 27 + bit_size: 1 + description: DSI host reset + name: DSIRST +fieldset/BDCR: + description: Backup domain control register + fields: + - bit_offset: 0 + bit_size: 1 + description: External low-speed oscillator enable + name: LSEON + - bit_offset: 1 + bit_size: 1 + description: External low-speed oscillator ready + enum_read: LSERDYR + name: LSERDY + - bit_offset: 2 + bit_size: 1 + description: External low-speed oscillator bypass + enum: LSEBYP + name: LSEBYP + - bit_offset: 8 + bit_size: 2 + description: RTC clock source selection + enum: RTCSEL + name: RTCSEL + - bit_offset: 15 + bit_size: 1 + description: RTC clock enable + name: RTCEN + - bit_offset: 16 + bit_size: 1 + description: Backup domain software reset + name: BDRST + - bit_offset: 3 + bit_size: 1 + description: External low-speed oscillator bypass + enum: LSEMOD + name: LSEMOD +fieldset/CFGR: + description: clock configuration register + fields: + - bit_offset: 0 + bit_size: 2 + description: System clock switch + enum: SW + name: SW + - bit_offset: 2 + bit_size: 2 + description: System clock switch status + enum_read: SWSR + name: SWS + - bit_offset: 4 + bit_size: 4 + description: AHB prescaler + enum: HPRE + name: HPRE + - bit_offset: 10 + bit_size: 3 + description: APB Low speed prescaler (APB1) + enum: PPRE + name: PPRE1 + - bit_offset: 13 + bit_size: 3 + description: APB high-speed prescaler (APB2) + enum: PPRE + name: PPRE2 + - bit_offset: 16 + bit_size: 5 + description: HSE division factor for RTC clock + name: RTCPRE + - bit_offset: 21 + bit_size: 2 + description: Microcontroller clock output 1 + enum: MCO1 + name: MCO1 + - bit_offset: 23 + bit_size: 1 + description: I2S clock selection + enum: ISSRC + name: I2SSRC + - bit_offset: 24 + bit_size: 3 + description: MCO1 prescaler + enum: MCOPRE + name: MCO1PRE + - bit_offset: 27 + bit_size: 3 + description: MCO2 prescaler + enum: MCOPRE + name: MCO2PRE + - bit_offset: 30 + bit_size: 2 + description: Microcontroller clock output 2 + enum: MCO2 + name: MCO2 + - bit_offset: 8 + bit_size: 1 + description: MCO output enable + name: MCO1EN + - bit_offset: 9 + bit_size: 1 + description: MCO output enable + name: MCO2EN +fieldset/CIR: + description: clock interrupt register + fields: + - bit_offset: 0 + bit_size: 1 + description: LSI ready interrupt flag + enum_read: PLLISRDYFR + name: LSIRDYF + - bit_offset: 1 + bit_size: 1 + description: LSE ready interrupt flag + enum_read: PLLISRDYFR + name: LSERDYF + - bit_offset: 2 + bit_size: 1 + description: HSI ready interrupt flag + enum_read: PLLISRDYFR + name: HSIRDYF + - bit_offset: 3 + bit_size: 1 + description: HSE ready interrupt flag + enum_read: PLLISRDYFR + name: HSERDYF + - bit_offset: 4 + bit_size: 1 + description: Main PLL (PLL) ready interrupt flag + enum_read: PLLISRDYFR + name: PLLRDYF + - bit_offset: 5 + bit_size: 1 + description: PLLI2S ready interrupt flag + enum_read: PLLISRDYFR + name: PLLI2SRDYF + - bit_offset: 7 + bit_size: 1 + description: Clock security system interrupt flag + enum_read: CSSFR + name: CSSF + - bit_offset: 8 + bit_size: 1 + description: LSI ready interrupt enable + enum: PLLISRDYIE + name: LSIRDYIE + - bit_offset: 9 + bit_size: 1 + description: LSE ready interrupt enable + enum: PLLISRDYIE + name: LSERDYIE + - bit_offset: 10 + bit_size: 1 + description: HSI ready interrupt enable + enum: PLLISRDYIE + name: HSIRDYIE + - bit_offset: 11 + bit_size: 1 + description: HSE ready interrupt enable + enum: PLLISRDYIE + name: HSERDYIE + - bit_offset: 12 + bit_size: 1 + description: Main PLL (PLL) ready interrupt enable + enum: PLLISRDYIE + name: PLLRDYIE + - bit_offset: 13 + bit_size: 1 + description: PLLI2S ready interrupt enable + enum: PLLISRDYIE + name: PLLI2SRDYIE + - bit_offset: 16 + bit_size: 1 + description: LSI ready interrupt clear + enum_write: PLLISRDYCW + name: LSIRDYC + - bit_offset: 17 + bit_size: 1 + description: LSE ready interrupt clear + enum_write: PLLISRDYCW + name: LSERDYC + - bit_offset: 18 + bit_size: 1 + description: HSI ready interrupt clear + enum_write: PLLISRDYCW + name: HSIRDYC + - bit_offset: 19 + bit_size: 1 + description: HSE ready interrupt clear + enum_write: PLLISRDYCW + name: HSERDYC + - bit_offset: 20 + bit_size: 1 + description: Main PLL(PLL) ready interrupt clear + enum_write: PLLISRDYCW + name: PLLRDYC + - bit_offset: 21 + bit_size: 1 + description: PLLI2S ready interrupt clear + enum_write: PLLISRDYCW + name: PLLI2SRDYC + - bit_offset: 23 + bit_size: 1 + description: Clock security system interrupt clear + enum_write: CSSCW + name: CSSC + - bit_offset: 6 + bit_size: 1 + description: PLLSAI ready interrupt flag + enum_read: PLLSAIRDYFR + name: PLLSAIRDYF + - bit_offset: 14 + bit_size: 1 + description: PLLSAI Ready Interrupt Enable + enum: PLLSAIRDYIE + name: PLLSAIRDYIE + - bit_offset: 22 + bit_size: 1 + description: PLLSAI Ready Interrupt Clear + enum_write: PLLSAIRDYCW + name: PLLSAIRDYC +fieldset/CKGATENR: + description: clocks gated enable register + fields: + - bit_offset: 0 + bit_size: 1 + description: AHB to APB1 Bridge clock enable + name: AHB2APB1_CKEN + - bit_offset: 1 + bit_size: 1 + description: AHB to APB2 Bridge clock enable + name: AHB2APB2_CKEN + - bit_offset: 2 + bit_size: 1 + description: Cortex M4 ETM clock enable + name: CM4DBG_CKEN + - bit_offset: 3 + bit_size: 1 + description: Spare clock enable + name: SPARE_CKEN + - bit_offset: 4 + bit_size: 1 + description: SRAM controller clock enable + name: SRAM_CKEN + - bit_offset: 5 + bit_size: 1 + description: Flash interface clock enable + name: FLITF_CKEN + - bit_offset: 6 + bit_size: 1 + description: RCC clock enable + name: RCC_CKEN + - bit_offset: 7 + bit_size: 1 + description: EVTCL clock enable + name: EVTCL_CKEN +fieldset/CR: + description: clock control register + fields: + - bit_offset: 0 + bit_size: 1 + description: Internal high-speed clock enable + name: HSION + - bit_offset: 1 + bit_size: 1 + description: Internal high-speed clock ready flag + enum_read: PLLISRDYR + name: HSIRDY + - bit_offset: 3 + bit_size: 5 + description: Internal high-speed clock trimming + name: HSITRIM + - bit_offset: 8 + bit_size: 8 + description: Internal high-speed clock calibration + name: HSICAL + - bit_offset: 16 + bit_size: 1 + description: HSE clock enable + name: HSEON + - bit_offset: 17 + bit_size: 1 + description: HSE clock ready flag + enum_read: PLLISRDYR + name: HSERDY + - bit_offset: 18 + bit_size: 1 + description: HSE clock bypass + enum: HSEBYP + name: HSEBYP + - bit_offset: 19 + bit_size: 1 + description: Clock security system enable + name: CSSON + - bit_offset: 24 + bit_size: 1 + description: Main PLL (PLL) enable + name: PLLON + - bit_offset: 25 + bit_size: 1 + description: Main PLL (PLL) clock ready flag + enum_read: PLLISRDYR + name: PLLRDY + - bit_offset: 26 + bit_size: 1 + description: PLLI2S enable + name: PLLI2SON + - bit_offset: 27 + bit_size: 1 + description: PLLI2S clock ready flag + enum_read: PLLISRDYR + name: PLLI2SRDY + - bit_offset: 28 + bit_size: 1 + description: PLLSAI enable + name: PLLSAION + - bit_offset: 29 + bit_size: 1 + description: PLLSAI clock ready flag + enum_read: PLLISRDYR + name: PLLSAIRDY +fieldset/CSR: + description: clock control & status register + fields: + - bit_offset: 0 + bit_size: 1 + description: Internal low-speed oscillator enable + name: LSION + - bit_offset: 1 + bit_size: 1 + description: Internal low-speed oscillator ready + enum_read: LSIRDYR + name: LSIRDY + - bit_offset: 24 + bit_size: 1 + description: Remove reset flag + enum_write: RMVFW + name: RMVF + - bit_offset: 25 + bit_size: 1 + description: BOR reset flag + enum_read: LPWRRSTFR + name: BORRSTF + - bit_offset: 26 + bit_size: 1 + description: PIN reset flag + enum_read: LPWRRSTFR + name: PADRSTF + - bit_offset: 27 + bit_size: 1 + description: POR/PDR reset flag + enum_read: LPWRRSTFR + name: PORRSTF + - bit_offset: 28 + bit_size: 1 + description: Software reset flag + enum_read: LPWRRSTFR + name: SFTRSTF + - bit_offset: 29 + bit_size: 1 + description: Independent watchdog reset flag + enum_read: LPWRRSTFR + name: WDGRSTF + - bit_offset: 30 + bit_size: 1 + description: Window watchdog reset flag + enum_read: LPWRRSTFR + name: WWDGRSTF + - bit_offset: 31 + bit_size: 1 + description: Low-power reset flag + enum_read: LPWRRSTFR + name: LPWRRSTF +fieldset/DCKCFGR: + description: Dedicated Clock Configuration Register + fields: + - bit_offset: 24 + bit_size: 1 + description: Timers clocks prescalers selection + enum: TIMPRE + name: TIMPRE + - bit_offset: 25 + bit_size: 2 + description: I2SSRC + enum: ISSRC + name: I2SSRC + - bit_offset: 15 + bit_size: 5 + description: DFSDM1 audio clock selection + enum: CKDFSDMASEL + name: CKDFSDM1ASEL + - bit_offset: 25 + bit_size: 2 + description: I2S APB1 clocks source selection (I2S2/3) + enum: I2S1SRC + name: I2S1SRC + - bit_offset: 27 + bit_size: 2 + description: I2S APB2 clocks source selection (I2S1/4/5) + enum: I2S1SRC + name: I2S2SRC + - bit_offset: 31 + bit_size: 1 + description: DFSDM1 Kernel clock selection + enum: CKDFSDMSEL + name: CKDFSDM1SEL + - bit_offset: 0 + bit_size: 5 + description: PLLI2S division factor for SAI1 A/B clock + enum: PLLISDIVR + name: PLLI2SDIVR + - bit_offset: 8 + bit_size: 5 + description: PLL division factor for SAI1 A/B clock + enum: PLLDIVR + name: PLLDIVR + - bit_offset: 14 + bit_size: 1 + description: DFSDM2 audio clock selection + enum: CKDFSDMASEL + name: CKDFSDM2ASEL + - bit_offset: 20 + bit_size: 2 + description: SAI1-A clock source selection + enum: SAIASRC + name: SAI1ASRC + - bit_offset: 22 + bit_size: 2 + description: SAI1-B clock source selection + enum: SAIBSRC + name: SAI1BSRC + - bit_offset: 0 + bit_size: 5 + description: PLLI2S division factor for SAI1 clock + enum: PLLISDIVQ + name: PLLI2SDIVQ + - bit_offset: 8 + bit_size: 5 + description: PLLSAI division factor for SAI1 clock + enum: PLLSAIDIVQ + name: PLLSAIDIVQ + - bit_offset: 16 + bit_size: 2 + description: division factor for LCD_CLK + enum: PLLSAIDIVR + name: PLLSAIDIVR + - bit_offset: 20 + bit_size: 2 + description: SAI1 clock source selection + enum: SAI1SRC + name: SAI1SRC + - bit_offset: 22 + bit_size: 2 + description: SAI2 clock source selection + enum: SAI2SRC + name: SAI2SRC + - bit_offset: 27 + bit_size: 1 + description: 48 MHz clock source selection + enum: CKMSEL + name: CK48MSEL + - bit_offset: 28 + bit_size: 1 + description: SDIO clock source selection + enum: SDIOSEL + name: SDIOSEL + - bit_offset: 29 + bit_size: 1 + description: DSI clock source selection + enum: DSISEL + name: DSISEL +fieldset/DCKCFGR2: + description: dedicated clocks configuration register 2 + fields: + - bit_offset: 22 + bit_size: 2 + description: FMPI2C1 kernel clock source selection + enum: FMPICSEL + name: FMPI2C1SEL + - bit_offset: 30 + bit_size: 2 + description: LPTIM1SEL + enum: LPTIMSEL + name: LPTIM1SEL + - bit_offset: 27 + bit_size: 1 + description: SDIO/USBFS clock selection + enum: CKMSEL + name: CK48MSEL + - bit_offset: 28 + bit_size: 1 + description: SDIO clock selection + enum: SDIOSEL + name: SDIOSEL + - bit_offset: 26 + bit_size: 1 + description: HDMI CEC clock source selection + enum: CECSEL + name: CECSEL + - bit_offset: 29 + bit_size: 1 + description: SPDIF clock selection + enum: SPDIFRXSEL + name: SPDIFRXSEL +fieldset/PLLCFGR: + description: PLL configuration register + fields: + - bit_offset: 0 + bit_size: 6 + description: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input + clock + name: PLLM + - bit_offset: 6 + bit_size: 9 + description: Main PLL (PLL) multiplication factor for VCO + name: PLLN + - bit_offset: 16 + bit_size: 2 + description: Main PLL (PLL) division factor for main system clock + enum: PLLP + name: PLLP + - bit_offset: 22 + bit_size: 1 + description: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source + enum: PLLSRC + name: PLLSRC + - bit_offset: 24 + bit_size: 4 + description: Main PLL (PLL) division factor for USB OTG FS, SDIO and random number + generator clocks + name: PLLQ + - bit_offset: 28 + bit_size: 3 + description: PLL division factor for I2S and System clocks + name: PLLR +fieldset/PLLI2SCFGR: + description: PLLI2S configuration register + fields: + - bit_offset: 6 + bit_size: 9 + description: PLLI2S multiplication factor for VCO + name: PLLI2SN + - bit_offset: 28 + bit_size: 3 + description: PLLI2S division factor for I2S clocks + name: PLLI2SR + - bit_offset: 0 + bit_size: 6 + description: Division factor for the audio PLL (PLLI2S) input clock + name: PLLI2SM + - bit_offset: 22 + bit_size: 1 + description: PLLI2S entry clock source + enum: PLLISSRC + name: PLLI2SSRC + - bit_offset: 24 + bit_size: 4 + description: PLLI2S division factor for USB OTG FS/SDIO/RNG clock + name: PLLI2SQ + - bit_offset: 16 + bit_size: 2 + description: PLLI2S division factor for SPDIF-IN clock + enum: PLLISP + name: PLLI2SP +fieldset/PLLSAICFGR: + description: PLL configuration register + fields: + - bit_offset: 6 + bit_size: 9 + description: PLLSAI division factor for VCO + name: PLLSAIN + - bit_offset: 24 + bit_size: 4 + description: PLLSAI division factor for SAI1 clock + name: PLLSAIQ + - bit_offset: 28 + bit_size: 3 + description: PLLSAI division factor for LCD clock + name: PLLSAIR + - bit_offset: 0 + bit_size: 6 + description: Division factor for audio PLLSAI input clock + name: PLLSAIM + - bit_offset: 16 + bit_size: 2 + description: PLLSAI division factor for 48 MHz clock + enum: PLLSAIP + name: PLLSAIP +fieldset/SSCGR: + description: spread spectrum clock generation register + fields: + - bit_offset: 0 + bit_size: 13 + description: Modulation period + name: MODPER + - bit_offset: 13 + bit_size: 15 + description: Incrementation step + name: INCSTEP + - bit_offset: 30 + bit_size: 1 + description: Spread Select + enum: SPREADSEL + name: SPREADSEL + - bit_offset: 31 + bit_size: 1 + description: Spread spectrum modulation enable + name: SSCGEN diff --git a/data/registers/rcc_h7.yaml b/data/registers/rcc_h7.yaml index 34749b4..68c6858 100644 --- a/data/registers/rcc_h7.yaml +++ b/data/registers/rcc_h7.yaml @@ -1,5232 +1,4305 @@ ---- block/RCC: description: Reset and clock control items: - - name: CR - description: clock control register - byte_offset: 0 - fieldset: CR - - name: HSICFGR - description: RCC HSI configuration register - byte_offset: 4 - fieldset: HSICFGR - - name: ICSCR - description: RCC Internal Clock Source Calibration Register - byte_offset: 4 - fieldset: ICSCR - - name: CRRCR - description: RCC Clock Recovery RC Register - byte_offset: 8 - access: Read - fieldset: CRRCR - - name: CSICFGR - description: RCC CSI configuration register - byte_offset: 12 - fieldset: CSICFGR - - name: CFGR - description: RCC Clock Configuration Register - byte_offset: 16 - fieldset: CFGR - - name: D1CFGR - description: RCC Domain 1 Clock Configuration Register - byte_offset: 24 - fieldset: D1CFGR - - name: D2CFGR - description: RCC Domain 2 Clock Configuration Register - byte_offset: 28 - fieldset: D2CFGR - - name: D3CFGR - description: RCC Domain 3 Clock Configuration Register - byte_offset: 32 - fieldset: D3CFGR - - name: PLLCKSELR - description: RCC PLLs Clock Source Selection Register - byte_offset: 40 - fieldset: PLLCKSELR - - name: PLLCFGR - description: RCC PLLs Configuration Register - byte_offset: 44 - fieldset: PLLCFGR - - name: PLLDIVR - description: RCC PLL1 Dividers Configuration Register - array: - len: 3 - stride: 8 - byte_offset: 48 - fieldset: PLL1DIVR - - name: PLLFRACR - description: RCC PLL1 Fractional Divider Register - array: - len: 3 - stride: 8 - byte_offset: 52 - fieldset: PLL1FRACR - - name: D1CCIPR - description: RCC Domain 1 Kernel Clock Configuration Register - byte_offset: 76 - fieldset: D1CCIPR - - name: D2CCIP1R - description: RCC Domain 2 Kernel Clock Configuration Register - byte_offset: 80 - fieldset: D2CCIP1R - - name: D2CCIP2R - description: RCC Domain 2 Kernel Clock Configuration Register - byte_offset: 84 - fieldset: D2CCIP2R - - name: D3CCIPR - description: RCC Domain 3 Kernel Clock Configuration Register - byte_offset: 88 - fieldset: D3CCIPR - - name: CIER - description: RCC Clock Source Interrupt Enable Register - byte_offset: 96 - fieldset: CIER - - name: CIFR - description: RCC Clock Source Interrupt Flag Register - byte_offset: 100 - access: Read - fieldset: CIFR - - name: CICR - description: RCC Clock Source Interrupt Clear Register - byte_offset: 104 - fieldset: CICR - - name: BDCR - description: RCC Backup Domain Control Register - byte_offset: 112 - fieldset: BDCR - - name: CSR - description: RCC Clock Control and Status Register - byte_offset: 116 - fieldset: CSR - - name: AHB3RSTR - description: RCC AHB3 Reset Register - byte_offset: 124 - fieldset: AHB3RSTR - - name: AHB1RSTR - description: RCC AHB1 Peripheral Reset Register - byte_offset: 128 - fieldset: AHB1RSTR - - name: AHB2RSTR - description: RCC AHB2 Peripheral Reset Register - byte_offset: 132 - fieldset: AHB2RSTR - - name: AHB4RSTR - description: RCC AHB4 Peripheral Reset Register - byte_offset: 136 - fieldset: AHB4RSTR - - name: APB3RSTR - description: RCC APB3 Peripheral Reset Register - byte_offset: 140 - fieldset: APB3RSTR - - name: APB1LRSTR - description: RCC APB1 Peripheral Reset Register - byte_offset: 144 - fieldset: APB1LRSTR - - name: APB1HRSTR - description: RCC APB1 Peripheral Reset Register - byte_offset: 148 - fieldset: APB1HRSTR - - name: APB2RSTR - description: RCC APB2 Peripheral Reset Register - byte_offset: 152 - fieldset: APB2RSTR - - name: APB4RSTR - description: RCC APB4 Peripheral Reset Register - byte_offset: 156 - fieldset: APB4RSTR - - name: GCR - description: RCC Global Control Register - byte_offset: 160 - fieldset: GCR - - name: D3AMR - description: RCC D3 Autonomous mode Register - byte_offset: 168 - fieldset: D3AMR - - name: RSR - description: RCC Reset Status Register - byte_offset: 208 - fieldset: RSR - - name: AHB3ENR - description: RCC AHB3 Clock Register - byte_offset: 212 - fieldset: AHB3ENR - - name: AHB1ENR - description: RCC AHB1 Clock Register - byte_offset: 216 - fieldset: AHB1ENR - - name: AHB2ENR - description: RCC AHB2 Clock Register - byte_offset: 220 - fieldset: AHB2ENR - - name: AHB4ENR - description: RCC AHB4 Clock Register - byte_offset: 224 - fieldset: AHB4ENR - - name: APB3ENR - description: RCC APB3 Clock Register - byte_offset: 228 - fieldset: APB3ENR - - name: APB1LENR - description: RCC APB1 Clock Register - byte_offset: 232 - fieldset: APB1LENR - - name: APB1HENR - description: RCC APB1 Clock Register - byte_offset: 236 - fieldset: APB1HENR - - name: APB2ENR - description: RCC APB2 Clock Register - byte_offset: 240 - fieldset: APB2ENR - - name: APB4ENR - description: RCC APB4 Clock Register - byte_offset: 244 - fieldset: APB4ENR - - name: AHB3LPENR - description: RCC AHB3 Sleep Clock Register - byte_offset: 252 - fieldset: AHB3LPENR - - name: AHB1LPENR - description: RCC AHB1 Sleep Clock Register - byte_offset: 256 - fieldset: AHB1LPENR - - name: AHB2LPENR - description: RCC AHB2 Sleep Clock Register - byte_offset: 260 - fieldset: AHB2LPENR - - name: AHB4LPENR - description: RCC AHB4 Sleep Clock Register - byte_offset: 264 - fieldset: AHB4LPENR - - name: APB3LPENR - description: RCC APB3 Sleep Clock Register - byte_offset: 268 - fieldset: APB3LPENR - - name: APB1LLPENR - description: RCC APB1 Low Sleep Clock Register - byte_offset: 272 - fieldset: APB1LLPENR - - name: APB1HLPENR - description: RCC APB1 High Sleep Clock Register - byte_offset: 276 - fieldset: APB1HLPENR - - name: APB2LPENR - description: RCC APB2 Sleep Clock Register - byte_offset: 280 - fieldset: APB2LPENR - - name: APB4LPENR - description: RCC APB4 Sleep Clock Register - byte_offset: 284 - fieldset: APB4LPENR - - name: C1_RSR - description: RCC Reset Status Register - byte_offset: 304 - fieldset: C1_RSR - - name: C1_AHB3ENR - description: RCC AHB3 Clock Register - byte_offset: 308 - fieldset: C1_AHB3ENR - - name: C1_AHB1ENR - description: RCC AHB1 Clock Register - byte_offset: 312 - fieldset: C1_AHB1ENR - - name: C1_AHB2ENR - description: RCC AHB2 Clock Register - byte_offset: 316 - fieldset: C1_AHB2ENR - - name: C1_AHB4ENR - description: RCC AHB4 Clock Register - byte_offset: 320 - fieldset: C1_AHB4ENR - - name: C1_APB3ENR - description: RCC APB3 Clock Register - byte_offset: 324 - fieldset: C1_APB3ENR - - name: C1_APB1LENR - description: RCC APB1 Clock Register - byte_offset: 328 - fieldset: C1_APB1LENR - - name: C1_APB1HENR - description: RCC APB1 Clock Register - byte_offset: 332 - fieldset: C1_APB1HENR - - name: C1_APB2ENR - description: RCC APB2 Clock Register - byte_offset: 336 - fieldset: C1_APB2ENR - - name: C1_APB4ENR - description: RCC APB4 Clock Register - byte_offset: 340 - fieldset: C1_APB4ENR - - name: C1_AHB3LPENR - description: RCC AHB3 Sleep Clock Register - byte_offset: 348 - fieldset: C1_AHB3LPENR - - name: C1_AHB1LPENR - description: RCC AHB1 Sleep Clock Register - byte_offset: 352 - fieldset: C1_AHB1LPENR - - name: C1_AHB2LPENR - description: RCC AHB2 Sleep Clock Register - byte_offset: 356 - fieldset: C1_AHB2LPENR - - name: C1_AHB4LPENR - description: RCC AHB4 Sleep Clock Register - byte_offset: 360 - fieldset: C1_AHB4LPENR - - name: C1_APB3LPENR - description: RCC APB3 Sleep Clock Register - byte_offset: 364 - fieldset: C1_APB3LPENR - - name: C1_APB1LLPENR - description: RCC APB1 Low Sleep Clock Register - byte_offset: 368 - fieldset: C1_APB1LLPENR - - name: C1_APB1HLPENR - description: RCC APB1 High Sleep Clock Register - byte_offset: 372 - fieldset: C1_APB1HLPENR - - name: C1_APB2LPENR - description: RCC APB2 Sleep Clock Register - byte_offset: 376 - fieldset: C1_APB2LPENR - - name: C1_APB4LPENR - description: RCC APB4 Sleep Clock Register - byte_offset: 380 - fieldset: C1_APB4LPENR -fieldset/AHB1ENR: - description: RCC AHB1 Clock Register - fields: - - name: DMA1EN - description: DMA1 Clock Enable - bit_offset: 0 - bit_size: 1 - enum: AHB1ENR_DMA1EN - - name: DMA2EN - description: DMA2 Clock Enable - bit_offset: 1 - bit_size: 1 - enum: AHB1ENR_DMA1EN - - name: ADC12EN - description: ADC1/2 Peripheral Clocks Enable - bit_offset: 5 - bit_size: 1 - enum: AHB1ENR_DMA1EN - - name: ETH1MACEN - description: Ethernet MAC bus interface Clock Enable - bit_offset: 15 - bit_size: 1 - enum: AHB1ENR_DMA1EN - - name: ETH1TXEN - description: Ethernet Transmission Clock Enable - bit_offset: 16 - bit_size: 1 - enum: AHB1ENR_DMA1EN - - name: ETH1RXEN - description: Ethernet Reception Clock Enable - bit_offset: 17 - bit_size: 1 - enum: AHB1ENR_DMA1EN - - name: USB2OTGHSULPIEN - description: " Enable USB_PHY2 clocks " - bit_offset: 18 - bit_size: 1 - enum: AHB1ENR_DMA1EN - - name: USB1OTGEN - description: USB1OTG Peripheral Clocks Enable - bit_offset: 25 - bit_size: 1 - enum: AHB1ENR_DMA1EN - - name: USB1ULPIEN - description: USB_PHY1 Clocks Enable - bit_offset: 26 - bit_size: 1 - enum: AHB1ENR_DMA1EN - - name: USB2OTGEN - description: USB2OTG Peripheral Clocks Enable - bit_offset: 27 - bit_size: 1 - enum: AHB1ENR_DMA1EN - - name: USB2ULPIEN - description: USB_PHY2 Clocks Enable - bit_offset: 28 - bit_size: 1 - enum: AHB1ENR_DMA1EN -fieldset/AHB1LPENR: - description: RCC AHB1 Sleep Clock Register - fields: - - name: DMA1LPEN - description: DMA1 Clock Enable During CSleep Mode - bit_offset: 0 - bit_size: 1 - enum: AHB1LPENR_DMA1LPEN - - name: DMA2LPEN - description: DMA2 Clock Enable During CSleep Mode - bit_offset: 1 - bit_size: 1 - enum: AHB1LPENR_DMA1LPEN - - name: ADC12LPEN - description: ADC1/2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 5 - bit_size: 1 - enum: AHB1LPENR_DMA1LPEN - - name: ETH1MACLPEN - description: Ethernet MAC bus interface Clock Enable During CSleep Mode - bit_offset: 15 - bit_size: 1 - enum: AHB1LPENR_DMA1LPEN - - name: ETH1TXLPEN - description: Ethernet Transmission Clock Enable During CSleep Mode - bit_offset: 16 - bit_size: 1 - enum: AHB1LPENR_DMA1LPEN - - name: ETH1RXLPEN - description: Ethernet Reception Clock Enable During CSleep Mode - bit_offset: 17 - bit_size: 1 - enum: AHB1LPENR_DMA1LPEN - - name: USB1OTGLPEN - description: USB1OTG peripheral clock enable during CSleep mode - bit_offset: 25 - bit_size: 1 - enum: AHB1LPENR_DMA1LPEN - - name: USB1OTGHSULPILPEN - description: USB_PHY1 clock enable during CSleep mode - bit_offset: 26 - bit_size: 1 - enum: AHB1LPENR_DMA1LPEN - - name: USB2OTGLPEN - description: USB2OTG peripheral clock enable during CSleep mode - bit_offset: 27 - bit_size: 1 - enum: AHB1LPENR_DMA1LPEN - - name: USB2OTGHSULPILPEN - description: USB_PHY2 clocks enable during CSleep mode - bit_offset: 28 - bit_size: 1 - enum: AHB1LPENR_DMA1LPEN -fieldset/AHB1RSTR: - description: RCC AHB1 Peripheral Reset Register - fields: - - name: DMA1RST - description: DMA1 block reset - bit_offset: 0 - bit_size: 1 - enum: DMA1RST - - name: DMA2RST - description: DMA2 block reset - bit_offset: 1 - bit_size: 1 - enum: DMA1RST - - name: ADC12RST - description: ADC1&2 block reset - bit_offset: 5 - bit_size: 1 - enum: DMA1RST - - name: ETH1MACRST - description: ETH1MAC block reset - bit_offset: 15 - bit_size: 1 - enum: DMA1RST - - name: USB1OTGRST - description: USB1OTG block reset - bit_offset: 25 - bit_size: 1 - enum: DMA1RST - - name: USB2OTGRST - description: USB2OTG block reset - bit_offset: 27 - bit_size: 1 - enum: DMA1RST -fieldset/AHB2ENR: - description: RCC AHB2 Clock Register - fields: - - name: DCMIEN - description: DCMI peripheral clock - bit_offset: 0 - bit_size: 1 - enum: AHB2ENR_DCMIEN - - name: CRYPTEN - description: CRYPT peripheral clock enable - bit_offset: 4 - bit_size: 1 - enum: AHB2ENR_DCMIEN - - name: HASHEN - description: HASH peripheral clock enable - bit_offset: 5 - bit_size: 1 - enum: AHB2ENR_DCMIEN - - name: RNGEN - description: RNG peripheral clocks enable - bit_offset: 6 - bit_size: 1 - enum: AHB2ENR_DCMIEN - - name: SDMMC2EN - description: SDMMC2 and SDMMC2 delay clock enable - bit_offset: 9 - bit_size: 1 - enum: AHB2ENR_DCMIEN - - name: SRAM1EN - description: SRAM1 block enable - bit_offset: 29 - bit_size: 1 - enum: AHB2ENR_DCMIEN - - name: SRAM2EN - description: SRAM2 block enable - bit_offset: 30 - bit_size: 1 - enum: AHB2ENR_DCMIEN - - name: SRAM3EN - description: SRAM3 block enable - bit_offset: 31 - bit_size: 1 - enum: AHB2ENR_DCMIEN -fieldset/AHB2LPENR: - description: RCC AHB2 Sleep Clock Register - fields: - - name: DCMILPEN - description: DCMI peripheral clock enable during csleep mode - bit_offset: 0 - bit_size: 1 - enum: AHB2LPENR_DCMILPEN - - name: CRYPTLPEN - description: CRYPT peripheral clock enable during CSleep mode - bit_offset: 4 - bit_size: 1 - enum: AHB2LPENR_DCMILPEN - - name: HASHLPEN - description: HASH peripheral clock enable during CSleep mode - bit_offset: 5 - bit_size: 1 - enum: AHB2LPENR_DCMILPEN - - name: RNGLPEN - description: RNG peripheral clock enable during CSleep mode - bit_offset: 6 - bit_size: 1 - enum: AHB2LPENR_DCMILPEN - - name: SDMMC2LPEN - description: SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode - bit_offset: 9 - bit_size: 1 - enum: AHB2LPENR_DCMILPEN - - name: SRAM1LPEN - description: SRAM1 Clock Enable During CSleep Mode - bit_offset: 29 - bit_size: 1 - enum: AHB2LPENR_DCMILPEN - - name: SRAM2LPEN - description: SRAM2 Clock Enable During CSleep Mode - bit_offset: 30 - bit_size: 1 - enum: AHB2LPENR_DCMILPEN - - name: SRAM3LPEN - description: SRAM3 Clock Enable During CSleep Mode - bit_offset: 31 - bit_size: 1 - enum: AHB2LPENR_DCMILPEN -fieldset/AHB2RSTR: - description: RCC AHB2 Peripheral Reset Register - fields: - - name: CAMITFRST - description: CAMITF block reset - bit_offset: 0 - bit_size: 1 - enum: CAMITFRST - - name: CRYPTRST - description: Cryptography block reset - bit_offset: 4 - bit_size: 1 - enum: CAMITFRST - - name: HASHRST - description: Hash block reset - bit_offset: 5 - bit_size: 1 - enum: CAMITFRST - - name: RNGRST - description: Random Number Generator block reset - bit_offset: 6 - bit_size: 1 - enum: CAMITFRST - - name: SDMMC2RST - description: SDMMC2 and SDMMC2 Delay block reset - bit_offset: 9 - bit_size: 1 - enum: CAMITFRST -fieldset/AHB3ENR: - description: RCC AHB3 Clock Register - fields: - - name: MDMAEN - description: MDMA Peripheral Clock Enable - bit_offset: 0 - bit_size: 1 - enum: AHB3ENR_MDMAEN - - name: DMA2DEN - description: DMA2D Peripheral Clock Enable - bit_offset: 4 - bit_size: 1 - enum: AHB3ENR_MDMAEN - - name: JPGDECEN - description: JPGDEC Peripheral Clock Enable - bit_offset: 5 - bit_size: 1 - enum: AHB3ENR_MDMAEN - - name: FMCEN - description: FMC Peripheral Clocks Enable - bit_offset: 12 - bit_size: 1 - enum: AHB3ENR_MDMAEN - - name: QSPIEN - description: QUADSPI and QUADSPI Delay Clock Enable - bit_offset: 14 - bit_size: 1 - enum: AHB3ENR_MDMAEN - - name: SDMMC1EN - description: SDMMC1 and SDMMC1 Delay Clock Enable - bit_offset: 16 - bit_size: 1 - enum: AHB3ENR_MDMAEN -fieldset/AHB3LPENR: - description: RCC AHB3 Sleep Clock Register - fields: - - name: MDMALPEN - description: MDMA Clock Enable During CSleep Mode - bit_offset: 0 - bit_size: 1 - enum: AHB3LPENR_MDMALPEN - - name: DMA2DLPEN - description: DMA2D Clock Enable During CSleep Mode - bit_offset: 4 - bit_size: 1 - enum: AHB3LPENR_MDMALPEN - - name: JPGDECLPEN - description: JPGDEC Clock Enable During CSleep Mode - bit_offset: 5 - bit_size: 1 - enum: AHB3LPENR_MDMALPEN - - name: FLASHLPEN - description: FLITF Clock Enable During CSleep Mode - bit_offset: 8 - bit_size: 1 - enum: AHB3LPENR_MDMALPEN - - name: FMCLPEN - description: FMC Peripheral Clocks Enable During CSleep Mode - bit_offset: 12 - bit_size: 1 - enum: AHB3LPENR_MDMALPEN - - name: QSPILPEN - description: QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode - bit_offset: 14 - bit_size: 1 - enum: AHB3LPENR_MDMALPEN - - name: SDMMC1LPEN - description: SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode - bit_offset: 16 - bit_size: 1 - enum: AHB3LPENR_MDMALPEN - - name: D1DTCM1LPEN - description: D1DTCM1 Block Clock Enable During CSleep mode - bit_offset: 28 - bit_size: 1 - enum: AHB3LPENR_MDMALPEN - - name: DTCM2LPEN - description: D1 DTCM2 Block Clock Enable During CSleep mode - bit_offset: 29 - bit_size: 1 - enum: AHB3LPENR_MDMALPEN - - name: ITCMLPEN - description: D1ITCM Block Clock Enable During CSleep mode - bit_offset: 30 - bit_size: 1 - enum: AHB3LPENR_MDMALPEN - - name: AXISRAMLPEN - description: AXISRAM Block Clock Enable During CSleep mode - bit_offset: 31 - bit_size: 1 - enum: AHB3LPENR_MDMALPEN -fieldset/AHB3RSTR: - description: RCC AHB3 Reset Register - fields: - - name: MDMARST - description: MDMA block reset - bit_offset: 0 - bit_size: 1 - enum: MDMARST - - name: DMA2DRST - description: DMA2D block reset - bit_offset: 4 - bit_size: 1 - enum: MDMARST - - name: JPGDECRST - description: JPGDEC block reset - bit_offset: 5 - bit_size: 1 - enum: MDMARST - - name: FMCRST - description: FMC block reset - bit_offset: 12 - bit_size: 1 - enum: MDMARST - - name: QSPIRST - description: QUADSPI and QUADSPI delay block reset - bit_offset: 14 - bit_size: 1 - enum: MDMARST - - name: SDMMC1RST - description: SDMMC1 and SDMMC1 delay block reset - bit_offset: 16 - bit_size: 1 - enum: MDMARST - - name: CPURST - description: CPU reset - bit_offset: 31 - bit_size: 1 - enum: MDMARST -fieldset/AHB4ENR: - description: RCC AHB4 Clock Register - fields: - - name: GPIOAEN - description: 0GPIO peripheral clock enable - bit_offset: 0 - bit_size: 1 - enum: AHB4ENR_GPIOAEN - - name: GPIOBEN - description: 0GPIO peripheral clock enable - bit_offset: 1 - bit_size: 1 - enum: AHB4ENR_GPIOAEN - - name: GPIOCEN - description: 0GPIO peripheral clock enable - bit_offset: 2 - bit_size: 1 - enum: AHB4ENR_GPIOAEN - - name: GPIODEN - description: 0GPIO peripheral clock enable - bit_offset: 3 - bit_size: 1 - enum: AHB4ENR_GPIOAEN - - name: GPIOEEN - description: 0GPIO peripheral clock enable - bit_offset: 4 - bit_size: 1 - enum: AHB4ENR_GPIOAEN - - name: GPIOFEN - description: 0GPIO peripheral clock enable - bit_offset: 5 - bit_size: 1 - enum: AHB4ENR_GPIOAEN - - name: GPIOGEN - description: 0GPIO peripheral clock enable - bit_offset: 6 - bit_size: 1 - enum: AHB4ENR_GPIOAEN - - name: GPIOHEN - description: 0GPIO peripheral clock enable - bit_offset: 7 - bit_size: 1 - enum: AHB4ENR_GPIOAEN - - name: GPIOIEN - description: 0GPIO peripheral clock enable - bit_offset: 8 - bit_size: 1 - enum: AHB4ENR_GPIOAEN - - name: GPIOJEN - description: 0GPIO peripheral clock enable - bit_offset: 9 - bit_size: 1 - enum: AHB4ENR_GPIOAEN - - name: GPIOKEN - description: 0GPIO peripheral clock enable - bit_offset: 10 - bit_size: 1 - enum: AHB4ENR_GPIOAEN - - name: CRCEN - description: CRC peripheral clock enable - bit_offset: 19 - bit_size: 1 - enum: AHB4ENR_GPIOAEN - - name: BDMAEN - description: BDMA and DMAMUX2 Clock Enable - bit_offset: 21 - bit_size: 1 - enum: AHB4ENR_GPIOAEN - - name: ADC3EN - description: ADC3 Peripheral Clocks Enable - bit_offset: 24 - bit_size: 1 - enum: AHB4ENR_GPIOAEN - - name: HSEMEN - description: HSEM peripheral clock enable - bit_offset: 25 - bit_size: 1 - enum: AHB4ENR_GPIOAEN - - name: BKPRAMEN - description: Backup RAM Clock Enable - bit_offset: 28 - bit_size: 1 - enum: AHB4ENR_GPIOAEN -fieldset/AHB4LPENR: - description: RCC AHB4 Sleep Clock Register - fields: - - name: GPIOALPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 0 - bit_size: 1 - enum: AHB4LPENR_GPIOALPEN - - name: GPIOBLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 1 - bit_size: 1 - enum: AHB4LPENR_GPIOALPEN - - name: GPIOCLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 2 - bit_size: 1 - enum: AHB4LPENR_GPIOALPEN - - name: GPIODLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 3 - bit_size: 1 - enum: AHB4LPENR_GPIOALPEN - - name: GPIOELPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 4 - bit_size: 1 - enum: AHB4LPENR_GPIOALPEN - - name: GPIOFLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 5 - bit_size: 1 - enum: AHB4LPENR_GPIOALPEN - - name: GPIOGLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 6 - bit_size: 1 - enum: AHB4LPENR_GPIOALPEN - - name: GPIOHLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 7 - bit_size: 1 - enum: AHB4LPENR_GPIOALPEN - - name: GPIOILPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 8 - bit_size: 1 - enum: AHB4LPENR_GPIOALPEN - - name: GPIOJLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 9 - bit_size: 1 - enum: AHB4LPENR_GPIOALPEN - - name: GPIOKLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 10 - bit_size: 1 - enum: AHB4LPENR_GPIOALPEN - - name: CRCLPEN - description: CRC peripheral clock enable during CSleep mode - bit_offset: 19 - bit_size: 1 - enum: AHB4LPENR_GPIOALPEN - - name: BDMALPEN - description: BDMA Clock Enable During CSleep Mode - bit_offset: 21 - bit_size: 1 - enum: AHB4LPENR_GPIOALPEN - - name: ADC3LPEN - description: ADC3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 24 - bit_size: 1 - enum: AHB4LPENR_GPIOALPEN - - name: BKPRAMLPEN - description: Backup RAM Clock Enable During CSleep Mode - bit_offset: 28 - bit_size: 1 - enum: AHB4LPENR_GPIOALPEN - - name: SRAM4LPEN - description: SRAM4 Clock Enable During CSleep Mode - bit_offset: 29 - bit_size: 1 - enum: AHB4LPENR_GPIOALPEN -fieldset/AHB4RSTR: - description: RCC AHB4 Peripheral Reset Register - fields: - - name: GPIOARST - description: GPIO block reset - bit_offset: 0 - bit_size: 1 - enum: GPIOARST - - name: GPIOBRST - description: GPIO block reset - bit_offset: 1 - bit_size: 1 - enum: GPIOARST - - name: GPIOCRST - description: GPIO block reset - bit_offset: 2 - bit_size: 1 - enum: GPIOARST - - name: GPIODRST - description: GPIO block reset - bit_offset: 3 - bit_size: 1 - enum: GPIOARST - - name: GPIOERST - description: GPIO block reset - bit_offset: 4 - bit_size: 1 - enum: GPIOARST - - name: GPIOFRST - description: GPIO block reset - bit_offset: 5 - bit_size: 1 - enum: GPIOARST - - name: GPIOGRST - description: GPIO block reset - bit_offset: 6 - bit_size: 1 - enum: GPIOARST - - name: GPIOHRST - description: GPIO block reset - bit_offset: 7 - bit_size: 1 - enum: GPIOARST - - name: GPIOIRST - description: GPIO block reset - bit_offset: 8 - bit_size: 1 - enum: GPIOARST - - name: GPIOJRST - description: GPIO block reset - bit_offset: 9 - bit_size: 1 - enum: GPIOARST - - name: GPIOKRST - description: GPIO block reset - bit_offset: 10 - bit_size: 1 - enum: GPIOARST - - name: CRCRST - description: CRC block reset - bit_offset: 19 - bit_size: 1 - enum: GPIOARST - - name: BDMARST - description: BDMA block reset - bit_offset: 21 - bit_size: 1 - enum: GPIOARST - - name: ADC3RST - description: ADC3 block reset - bit_offset: 24 - bit_size: 1 - enum: GPIOARST - - name: HSEMRST - description: HSEM block reset - bit_offset: 25 - bit_size: 1 - enum: GPIOARST -fieldset/APB1HENR: - description: RCC APB1 Clock Register - fields: - - name: CRSEN - description: Clock Recovery System peripheral clock enable - bit_offset: 1 - bit_size: 1 - enum: APB1HENR_CRSEN - - name: SWPEN - description: SWPMI Peripheral Clocks Enable - bit_offset: 2 - bit_size: 1 - enum: APB1HENR_CRSEN - - name: OPAMPEN - description: OPAMP peripheral clock enable - bit_offset: 4 - bit_size: 1 - enum: APB1HENR_CRSEN - - name: MDIOSEN - description: MDIOS peripheral clock enable - bit_offset: 5 - bit_size: 1 - enum: APB1HENR_CRSEN - - name: FDCANEN - description: FDCAN Peripheral Clocks Enable - bit_offset: 8 - bit_size: 1 - enum: APB1HENR_CRSEN -fieldset/APB1HLPENR: - description: RCC APB1 High Sleep Clock Register - fields: - - name: CRSLPEN - description: Clock Recovery System peripheral clock enable during CSleep mode - bit_offset: 1 - bit_size: 1 - enum: APB1HLPENR_CRSLPEN - - name: SWPLPEN - description: SWPMI Peripheral Clocks Enable During CSleep Mode - bit_offset: 2 - bit_size: 1 - enum: APB1HLPENR_CRSLPEN - - name: OPAMPLPEN - description: OPAMP peripheral clock enable during CSleep mode - bit_offset: 4 - bit_size: 1 - enum: APB1HLPENR_CRSLPEN - - name: MDIOSLPEN - description: MDIOS peripheral clock enable during CSleep mode - bit_offset: 5 - bit_size: 1 - enum: APB1HLPENR_CRSLPEN - - name: FDCANLPEN - description: FDCAN Peripheral Clocks Enable During CSleep Mode - bit_offset: 8 - bit_size: 1 - enum: APB1HLPENR_CRSLPEN -fieldset/APB1HRSTR: - description: RCC APB1 Peripheral Reset Register - fields: - - name: CRSRST - description: Clock Recovery System reset - bit_offset: 1 - bit_size: 1 - enum: CRSRST - - name: SWPRST - description: SWPMI block reset - bit_offset: 2 - bit_size: 1 - enum: CRSRST - - name: OPAMPRST - description: OPAMP block reset - bit_offset: 4 - bit_size: 1 - enum: CRSRST - - name: MDIOSRST - description: MDIOS block reset - bit_offset: 5 - bit_size: 1 - enum: CRSRST - - name: FDCANRST - description: FDCAN block reset - bit_offset: 8 - bit_size: 1 - enum: CRSRST -fieldset/APB1LENR: - description: RCC APB1 Clock Register - fields: - - name: TIM2EN - description: TIM peripheral clock enable - bit_offset: 0 - bit_size: 1 - enum: APB1LENR_TIM2EN - - name: TIM3EN - description: TIM peripheral clock enable - bit_offset: 1 - bit_size: 1 - enum: APB1LENR_TIM2EN - - name: TIM4EN - description: TIM peripheral clock enable - bit_offset: 2 - bit_size: 1 - enum: APB1LENR_TIM2EN - - name: TIM5EN - description: TIM peripheral clock enable - bit_offset: 3 - bit_size: 1 - enum: APB1LENR_TIM2EN - - name: TIM6EN - description: TIM peripheral clock enable - bit_offset: 4 - bit_size: 1 - enum: APB1LENR_TIM2EN - - name: TIM7EN - description: TIM peripheral clock enable - bit_offset: 5 - bit_size: 1 - enum: APB1LENR_TIM2EN - - name: TIM12EN - description: TIM peripheral clock enable - bit_offset: 6 - bit_size: 1 - enum: APB1LENR_TIM2EN - - name: TIM13EN - description: TIM peripheral clock enable - bit_offset: 7 - bit_size: 1 - enum: APB1LENR_TIM2EN - - name: TIM14EN - description: TIM peripheral clock enable - bit_offset: 8 - bit_size: 1 - enum: APB1LENR_TIM2EN - - name: LPTIM1EN - description: LPTIM1 Peripheral Clocks Enable - bit_offset: 9 - bit_size: 1 - enum: APB1LENR_TIM2EN - - name: SPI2EN - description: SPI2 Peripheral Clocks Enable - bit_offset: 14 - bit_size: 1 - enum: APB1LENR_TIM2EN - - name: SPI3EN - description: SPI3 Peripheral Clocks Enable - bit_offset: 15 - bit_size: 1 - enum: APB1LENR_TIM2EN - - name: SPDIFRXEN - description: SPDIFRX Peripheral Clocks Enable - bit_offset: 16 - bit_size: 1 - enum: APB1LENR_TIM2EN - - name: USART2EN - description: USART2 Peripheral Clocks Enable - bit_offset: 17 - bit_size: 1 - enum: APB1LENR_TIM2EN - - name: USART3EN - description: USART3 Peripheral Clocks Enable - bit_offset: 18 - bit_size: 1 - enum: APB1LENR_TIM2EN - - name: UART4EN - description: UART4 Peripheral Clocks Enable - bit_offset: 19 - bit_size: 1 - enum: APB1LENR_TIM2EN - - name: UART5EN - description: UART5 Peripheral Clocks Enable - bit_offset: 20 - bit_size: 1 - enum: APB1LENR_TIM2EN - - name: I2C1EN - description: I2C1 Peripheral Clocks Enable - bit_offset: 21 - bit_size: 1 - enum: APB1LENR_TIM2EN - - name: I2C2EN - description: I2C2 Peripheral Clocks Enable - bit_offset: 22 - bit_size: 1 - enum: APB1LENR_TIM2EN - - name: I2C3EN - description: I2C3 Peripheral Clocks Enable - bit_offset: 23 - bit_size: 1 - enum: APB1LENR_TIM2EN - - name: CECEN - description: HDMI-CEC peripheral clock enable - bit_offset: 27 - bit_size: 1 - enum: APB1LENR_TIM2EN - - name: DAC12EN - description: DAC1&2 peripheral clock enable - bit_offset: 29 - bit_size: 1 - enum: APB1LENR_TIM2EN - - name: UART7EN - description: UART7 Peripheral Clocks Enable - bit_offset: 30 - bit_size: 1 - enum: APB1LENR_TIM2EN - - name: UART8EN - description: UART8 Peripheral Clocks Enable - bit_offset: 31 - bit_size: 1 - enum: APB1LENR_TIM2EN -fieldset/APB1LLPENR: - description: RCC APB1 Low Sleep Clock Register - fields: - - name: TIM2LPEN - description: TIM2 peripheral clock enable during CSleep mode - bit_offset: 0 - bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - - name: TIM3LPEN - description: TIM3 peripheral clock enable during CSleep mode - bit_offset: 1 - bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - - name: TIM4LPEN - description: TIM4 peripheral clock enable during CSleep mode - bit_offset: 2 - bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - - name: TIM5LPEN - description: TIM5 peripheral clock enable during CSleep mode - bit_offset: 3 - bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - - name: TIM6LPEN - description: TIM6 peripheral clock enable during CSleep mode - bit_offset: 4 - bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - - name: TIM7LPEN - description: TIM7 peripheral clock enable during CSleep mode - bit_offset: 5 - bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - - name: TIM12LPEN - description: TIM12 peripheral clock enable during CSleep mode - bit_offset: 6 - bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - - name: TIM13LPEN - description: TIM13 peripheral clock enable during CSleep mode - bit_offset: 7 - bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - - name: TIM14LPEN - description: TIM14 peripheral clock enable during CSleep mode - bit_offset: 8 - bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - - name: LPTIM1LPEN - description: LPTIM1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 9 - bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - - name: SPI2LPEN - description: SPI2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 14 - bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - - name: SPI3LPEN - description: SPI3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 15 - bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - - name: SPDIFRXLPEN - description: SPDIFRX Peripheral Clocks Enable During CSleep Mode - bit_offset: 16 - bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - - name: USART2LPEN - description: USART2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 17 - bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - - name: USART3LPEN - description: USART3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 18 - bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - - name: UART4LPEN - description: UART4 Peripheral Clocks Enable During CSleep Mode - bit_offset: 19 - bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - - name: UART5LPEN - description: UART5 Peripheral Clocks Enable During CSleep Mode - bit_offset: 20 - bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - - name: I2C1LPEN - description: I2C1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 21 - bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - - name: I2C2LPEN - description: I2C2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 22 - bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - - name: I2C3LPEN - description: I2C3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 23 - bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - - name: CECLPEN - description: HDMI-CEC Peripheral Clocks Enable During CSleep Mode - bit_offset: 27 - bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - - name: DAC12LPEN - description: DAC1/2 peripheral clock enable during CSleep mode - bit_offset: 29 - bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - - name: UART7LPEN - description: UART7 Peripheral Clocks Enable During CSleep Mode - bit_offset: 30 - bit_size: 1 - enum: APB1LLPENR_TIM2LPEN - - name: UART8LPEN - description: UART8 Peripheral Clocks Enable During CSleep Mode - bit_offset: 31 - bit_size: 1 - enum: APB1LLPENR_TIM2LPEN -fieldset/APB1LRSTR: - description: RCC APB1 Peripheral Reset Register - fields: - - name: TIM2RST - description: TIM block reset - bit_offset: 0 - bit_size: 1 - enum: TIM2RST - - name: TIM3RST - description: TIM block reset - bit_offset: 1 - bit_size: 1 - enum: TIM2RST - - name: TIM4RST - description: TIM block reset - bit_offset: 2 - bit_size: 1 - enum: TIM2RST - - name: TIM5RST - description: TIM block reset - bit_offset: 3 - bit_size: 1 - enum: TIM2RST - - name: TIM6RST - description: TIM block reset - bit_offset: 4 - bit_size: 1 - enum: TIM2RST - - name: TIM7RST - description: TIM block reset - bit_offset: 5 - bit_size: 1 - enum: TIM2RST - - name: TIM12RST - description: TIM block reset - bit_offset: 6 - bit_size: 1 - enum: TIM2RST - - name: TIM13RST - description: TIM block reset - bit_offset: 7 - bit_size: 1 - enum: TIM2RST - - name: TIM14RST - description: TIM block reset - bit_offset: 8 - bit_size: 1 - enum: TIM2RST - - name: LPTIM1RST - description: TIM block reset - bit_offset: 9 - bit_size: 1 - enum: TIM2RST - - name: SPI2RST - description: SPI2 block reset - bit_offset: 14 - bit_size: 1 - enum: TIM2RST - - name: SPI3RST - description: SPI3 block reset - bit_offset: 15 - bit_size: 1 - enum: TIM2RST - - name: SPDIFRXRST - description: SPDIFRX block reset - bit_offset: 16 - bit_size: 1 - enum: TIM2RST - - name: USART2RST - description: USART2 block reset - bit_offset: 17 - bit_size: 1 - enum: TIM2RST - - name: USART3RST - description: USART3 block reset - bit_offset: 18 - bit_size: 1 - enum: TIM2RST - - name: UART4RST - description: UART4 block reset - bit_offset: 19 - bit_size: 1 - enum: TIM2RST - - name: UART5RST - description: UART5 block reset - bit_offset: 20 - bit_size: 1 - enum: TIM2RST - - name: I2C1RST - description: I2C1 block reset - bit_offset: 21 - bit_size: 1 - enum: TIM2RST - - name: I2C2RST - description: I2C2 block reset - bit_offset: 22 - bit_size: 1 - enum: TIM2RST - - name: I2C3RST - description: I2C3 block reset - bit_offset: 23 - bit_size: 1 - enum: TIM2RST - - name: CECRST - description: HDMI-CEC block reset - bit_offset: 27 - bit_size: 1 - enum: TIM2RST - - name: DAC12RST - description: DAC1 and 2 Blocks Reset - bit_offset: 29 - bit_size: 1 - enum: TIM2RST - - name: UART7RST - description: UART7 block reset - bit_offset: 30 - bit_size: 1 - enum: TIM2RST - - name: UART8RST - description: UART8 block reset - bit_offset: 31 - bit_size: 1 - enum: TIM2RST -fieldset/APB2ENR: - description: RCC APB2 Clock Register - fields: - - name: TIM1EN - description: TIM1 peripheral clock enable - bit_offset: 0 - bit_size: 1 - enum: APB2ENR_TIM1EN - - name: TIM8EN - description: TIM8 peripheral clock enable - bit_offset: 1 - bit_size: 1 - enum: APB2ENR_TIM1EN - - name: USART1EN - description: USART1 Peripheral Clocks Enable - bit_offset: 4 - bit_size: 1 - enum: APB2ENR_TIM1EN - - name: USART6EN - description: USART6 Peripheral Clocks Enable - bit_offset: 5 - bit_size: 1 - enum: APB2ENR_TIM1EN - - name: SPI1EN - description: SPI1 Peripheral Clocks Enable - bit_offset: 12 - bit_size: 1 - enum: APB2ENR_TIM1EN - - name: SPI4EN - description: SPI4 Peripheral Clocks Enable - bit_offset: 13 - bit_size: 1 - enum: APB2ENR_TIM1EN - - name: TIM15EN - description: TIM15 peripheral clock enable - bit_offset: 16 - bit_size: 1 - enum: APB2ENR_TIM1EN - - name: TIM16EN - description: TIM16 peripheral clock enable - bit_offset: 17 - bit_size: 1 - enum: APB2ENR_TIM1EN - - name: TIM17EN - description: TIM17 peripheral clock enable - bit_offset: 18 - bit_size: 1 - enum: APB2ENR_TIM1EN - - name: SPI5EN - description: SPI5 Peripheral Clocks Enable - bit_offset: 20 - bit_size: 1 - enum: APB2ENR_TIM1EN - - name: SAI1EN - description: SAI1 Peripheral Clocks Enable - bit_offset: 22 - bit_size: 1 - enum: APB2ENR_TIM1EN - - name: SAI2EN - description: SAI2 Peripheral Clocks Enable - bit_offset: 23 - bit_size: 1 - enum: APB2ENR_TIM1EN - - name: SAI3EN - description: SAI3 Peripheral Clocks Enable - bit_offset: 24 - bit_size: 1 - enum: APB2ENR_TIM1EN - - name: DFSDM1EN - description: DFSDM1 Peripheral Clocks Enable - bit_offset: 28 - bit_size: 1 - enum: APB2ENR_TIM1EN - - name: HRTIMEN - description: HRTIM peripheral clock enable - bit_offset: 29 - bit_size: 1 - enum: APB2ENR_TIM1EN -fieldset/APB2LPENR: - description: RCC APB2 Sleep Clock Register - fields: - - name: TIM1LPEN - description: TIM1 peripheral clock enable during CSleep mode - bit_offset: 0 - bit_size: 1 - enum: APB2LPENR_TIM1LPEN - - name: TIM8LPEN - description: TIM8 peripheral clock enable during CSleep mode - bit_offset: 1 - bit_size: 1 - enum: APB2LPENR_TIM1LPEN - - name: USART1LPEN - description: USART1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 4 - bit_size: 1 - enum: APB2LPENR_TIM1LPEN - - name: USART6LPEN - description: USART6 Peripheral Clocks Enable During CSleep Mode - bit_offset: 5 - bit_size: 1 - enum: APB2LPENR_TIM1LPEN - - name: SPI1LPEN - description: SPI1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 12 - bit_size: 1 - enum: APB2LPENR_TIM1LPEN - - name: SPI4LPEN - description: SPI4 Peripheral Clocks Enable During CSleep Mode - bit_offset: 13 - bit_size: 1 - enum: APB2LPENR_TIM1LPEN - - name: TIM15LPEN - description: TIM15 peripheral clock enable during CSleep mode - bit_offset: 16 - bit_size: 1 - enum: APB2LPENR_TIM1LPEN - - name: TIM16LPEN - description: TIM16 peripheral clock enable during CSleep mode - bit_offset: 17 - bit_size: 1 - enum: APB2LPENR_TIM1LPEN - - name: TIM17LPEN - description: TIM17 peripheral clock enable during CSleep mode - bit_offset: 18 - bit_size: 1 - enum: APB2LPENR_TIM1LPEN - - name: SPI5LPEN - description: SPI5 Peripheral Clocks Enable During CSleep Mode - bit_offset: 20 - bit_size: 1 - enum: APB2LPENR_TIM1LPEN - - name: SAI1LPEN - description: SAI1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 22 - bit_size: 1 - enum: APB2LPENR_TIM1LPEN - - name: SAI2LPEN - description: SAI2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 23 - bit_size: 1 - enum: APB2LPENR_TIM1LPEN - - name: SAI3LPEN - description: SAI3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 24 - bit_size: 1 - enum: APB2LPENR_TIM1LPEN - - name: DFSDM1LPEN - description: DFSDM1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 28 - bit_size: 1 - enum: APB2LPENR_TIM1LPEN - - name: HRTIMLPEN - description: HRTIM peripheral clock enable during CSleep mode - bit_offset: 29 - bit_size: 1 - enum: APB2LPENR_TIM1LPEN -fieldset/APB2RSTR: - description: RCC APB2 Peripheral Reset Register - fields: - - name: TIM1RST - description: TIM1 block reset - bit_offset: 0 - bit_size: 1 - enum: TIM1RST - - name: TIM8RST - description: TIM8 block reset - bit_offset: 1 - bit_size: 1 - enum: TIM1RST - - name: USART1RST - description: USART1 block reset - bit_offset: 4 - bit_size: 1 - enum: TIM1RST - - name: USART6RST - description: USART6 block reset - bit_offset: 5 - bit_size: 1 - enum: TIM1RST - - name: SPI1RST - description: SPI1 block reset - bit_offset: 12 - bit_size: 1 - enum: TIM1RST - - name: SPI4RST - description: SPI4 block reset - bit_offset: 13 - bit_size: 1 - enum: TIM1RST - - name: TIM15RST - description: TIM15 block reset - bit_offset: 16 - bit_size: 1 - enum: TIM1RST - - name: TIM16RST - description: TIM16 block reset - bit_offset: 17 - bit_size: 1 - enum: TIM1RST - - name: TIM17RST - description: TIM17 block reset - bit_offset: 18 - bit_size: 1 - enum: TIM1RST - - name: SPI5RST - description: SPI5 block reset - bit_offset: 20 - bit_size: 1 - enum: TIM1RST - - name: SAI1RST - description: SAI1 block reset - bit_offset: 22 - bit_size: 1 - enum: TIM1RST - - name: SAI2RST - description: SAI2 block reset - bit_offset: 23 - bit_size: 1 - enum: TIM1RST - - name: SAI3RST - description: SAI3 block reset - bit_offset: 24 - bit_size: 1 - enum: TIM1RST - - name: DFSDM1RST - description: DFSDM1 block reset - bit_offset: 28 - bit_size: 1 - enum: TIM1RST - - name: HRTIMRST - description: HRTIM block reset - bit_offset: 29 - bit_size: 1 - enum: TIM1RST -fieldset/APB3ENR: - description: RCC APB3 Clock Register - fields: - - name: LTDCEN - description: LTDC peripheral clock enable - bit_offset: 3 - bit_size: 1 - enum: APB3ENR_LTDCEN - - name: WWDG1EN - description: WWDG1 Clock Enable - bit_offset: 6 - bit_size: 1 - enum: APB3ENR_LTDCEN -fieldset/APB3LPENR: - description: RCC APB3 Sleep Clock Register - fields: - - name: LTDCLPEN - description: LTDC peripheral clock enable during CSleep mode - bit_offset: 3 - bit_size: 1 - enum: APB3LPENR_LTDCLPEN - - name: WWDG1LPEN - description: WWDG1 Clock Enable During CSleep Mode - bit_offset: 6 - bit_size: 1 - enum: APB3LPENR_LTDCLPEN -fieldset/APB3RSTR: - description: RCC APB3 Peripheral Reset Register - fields: - - name: LTDCRST - description: LTDC block reset - bit_offset: 3 - bit_size: 1 - enum: LTDCRST -fieldset/APB4ENR: - description: RCC APB4 Clock Register - fields: - - name: SYSCFGEN - description: SYSCFG peripheral clock enable - bit_offset: 1 - bit_size: 1 - enum: APB4ENR_SYSCFGEN - - name: LPUART1EN - description: LPUART1 Peripheral Clocks Enable - bit_offset: 3 - bit_size: 1 - enum: APB4ENR_SYSCFGEN - - name: SPI6EN - description: SPI6 Peripheral Clocks Enable - bit_offset: 5 - bit_size: 1 - enum: APB4ENR_SYSCFGEN - - name: I2C4EN - description: I2C4 Peripheral Clocks Enable - bit_offset: 7 - bit_size: 1 - enum: APB4ENR_SYSCFGEN - - name: LPTIM2EN - description: LPTIM2 Peripheral Clocks Enable - bit_offset: 9 - bit_size: 1 - enum: APB4ENR_SYSCFGEN - - name: LPTIM3EN - description: LPTIM3 Peripheral Clocks Enable - bit_offset: 10 - bit_size: 1 - enum: APB4ENR_SYSCFGEN - - name: LPTIM4EN - description: LPTIM4 Peripheral Clocks Enable - bit_offset: 11 - bit_size: 1 - enum: APB4ENR_SYSCFGEN - - name: LPTIM5EN - description: LPTIM5 Peripheral Clocks Enable - bit_offset: 12 - bit_size: 1 - enum: APB4ENR_SYSCFGEN - - name: COMP12EN - description: COMP1/2 peripheral clock enable - bit_offset: 14 - bit_size: 1 - enum: APB4ENR_SYSCFGEN - - name: VREFEN - description: VREF peripheral clock enable - bit_offset: 15 - bit_size: 1 - enum: APB4ENR_SYSCFGEN - - name: RTCAPBEN - description: RTC APB Clock Enable - bit_offset: 16 - bit_size: 1 - enum: APB4ENR_SYSCFGEN - - name: SAI4EN - description: SAI4 Peripheral Clocks Enable - bit_offset: 21 - bit_size: 1 - enum: APB4ENR_SYSCFGEN -fieldset/APB4LPENR: - description: RCC APB4 Sleep Clock Register - fields: - - name: SYSCFGLPEN - description: SYSCFG peripheral clock enable during CSleep mode - bit_offset: 1 - bit_size: 1 - enum: APB4LPENR_SYSCFGLPEN - - name: LPUART1LPEN - description: LPUART1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 3 - bit_size: 1 - enum: APB4LPENR_SYSCFGLPEN - - name: SPI6LPEN - description: SPI6 Peripheral Clocks Enable During CSleep Mode - bit_offset: 5 - bit_size: 1 - enum: APB4LPENR_SYSCFGLPEN - - name: I2C4LPEN - description: I2C4 Peripheral Clocks Enable During CSleep Mode - bit_offset: 7 - bit_size: 1 - enum: APB4LPENR_SYSCFGLPEN - - name: LPTIM2LPEN - description: LPTIM2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 9 - bit_size: 1 - enum: APB4LPENR_SYSCFGLPEN - - name: LPTIM3LPEN - description: LPTIM3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 10 - bit_size: 1 - enum: APB4LPENR_SYSCFGLPEN - - name: LPTIM4LPEN - description: LPTIM4 Peripheral Clocks Enable During CSleep Mode - bit_offset: 11 - bit_size: 1 - enum: APB4LPENR_SYSCFGLPEN - - name: LPTIM5LPEN - description: LPTIM5 Peripheral Clocks Enable During CSleep Mode - bit_offset: 12 - bit_size: 1 - enum: APB4LPENR_SYSCFGLPEN - - name: COMP12LPEN - description: COMP1/2 peripheral clock enable during CSleep mode - bit_offset: 14 - bit_size: 1 - enum: APB4LPENR_SYSCFGLPEN - - name: VREFLPEN - description: VREF peripheral clock enable during CSleep mode - bit_offset: 15 - bit_size: 1 - enum: APB4LPENR_SYSCFGLPEN - - name: RTCAPBLPEN - description: RTC APB Clock Enable During CSleep Mode - bit_offset: 16 - bit_size: 1 - enum: APB4LPENR_SYSCFGLPEN - - name: SAI4LPEN - description: SAI4 Peripheral Clocks Enable During CSleep Mode - bit_offset: 21 - bit_size: 1 - enum: APB4LPENR_SYSCFGLPEN -fieldset/APB4RSTR: - description: RCC APB4 Peripheral Reset Register - fields: - - name: SYSCFGRST - description: SYSCFG block reset - bit_offset: 1 - bit_size: 1 - enum: SYSCFGRST - - name: LPUART1RST - description: LPUART1 block reset - bit_offset: 3 - bit_size: 1 - enum: SYSCFGRST - - name: SPI6RST - description: SPI6 block reset - bit_offset: 5 - bit_size: 1 - enum: SYSCFGRST - - name: I2C4RST - description: I2C4 block reset - bit_offset: 7 - bit_size: 1 - enum: SYSCFGRST - - name: LPTIM2RST - description: LPTIM2 block reset - bit_offset: 9 - bit_size: 1 - enum: SYSCFGRST - - name: LPTIM3RST - description: LPTIM3 block reset - bit_offset: 10 - bit_size: 1 - enum: SYSCFGRST - - name: LPTIM4RST - description: LPTIM4 block reset - bit_offset: 11 - bit_size: 1 - enum: SYSCFGRST - - name: LPTIM5RST - description: LPTIM5 block reset - bit_offset: 12 - bit_size: 1 - enum: SYSCFGRST - - name: COMP12RST - description: COMP12 Blocks Reset - bit_offset: 14 - bit_size: 1 - enum: SYSCFGRST - - name: VREFRST - description: VREF block reset - bit_offset: 15 - bit_size: 1 - enum: SYSCFGRST - - name: SAI4RST - description: SAI4 block reset - bit_offset: 21 - bit_size: 1 - enum: SYSCFGRST -fieldset/BDCR: - description: RCC Backup Domain Control Register - fields: - - name: LSEON - description: LSE oscillator enabled - bit_offset: 0 - bit_size: 1 - enum: LSEON - - name: LSERDY - description: LSE oscillator ready - bit_offset: 1 - bit_size: 1 - enum_read: LSERDYR - - name: LSEBYP - description: LSE oscillator bypass - bit_offset: 2 - bit_size: 1 - enum: LSEBYP - - name: LSEDRV - description: LSE oscillator driving capability - bit_offset: 3 - bit_size: 2 - enum: LSEDRV - - name: LSECSSON - description: LSE clock security system enable - bit_offset: 5 - bit_size: 1 - enum: LSECSSON - - name: LSECSSD - description: LSE clock security system failure detection - bit_offset: 6 - bit_size: 1 - enum_read: LSECSSDR - - name: RTCSEL - description: RTC clock source selection - bit_offset: 8 - bit_size: 2 - enum: RTCSEL - - name: RTCEN - description: RTC clock enable - bit_offset: 15 - bit_size: 1 - enum: RTCEN - - name: BDRST - description: VSwitch domain software reset - bit_offset: 16 - bit_size: 1 - enum: BDRST -fieldset/C1_AHB1ENR: - description: RCC AHB1 Clock Register - fields: - - name: DMA1EN - description: DMA1 Clock Enable - bit_offset: 0 - bit_size: 1 - enum: C1_AHB1ENR_DMA1EN - - name: DMA2EN - description: DMA2 Clock Enable - bit_offset: 1 - bit_size: 1 - enum: C1_AHB1ENR_DMA1EN - - name: ADC12EN - description: ADC1/2 Peripheral Clocks Enable - bit_offset: 5 - bit_size: 1 - enum: C1_AHB1ENR_DMA1EN - - name: ETH1MACEN - description: Ethernet MAC bus interface Clock Enable - bit_offset: 15 - bit_size: 1 - enum: C1_AHB1ENR_DMA1EN - - name: ETH1TXEN - description: Ethernet Transmission Clock Enable - bit_offset: 16 - bit_size: 1 - enum: C1_AHB1ENR_DMA1EN - - name: ETH1RXEN - description: Ethernet Reception Clock Enable - bit_offset: 17 - bit_size: 1 - enum: C1_AHB1ENR_DMA1EN - - name: USB1OTGEN - description: USB1OTG Peripheral Clocks Enable - bit_offset: 25 - bit_size: 1 - enum: C1_AHB1ENR_DMA1EN - - name: USB1ULPIEN - description: USB_PHY1 Clocks Enable - bit_offset: 26 - bit_size: 1 - enum: C1_AHB1ENR_DMA1EN - - name: USB2OTGEN - description: USB2OTG Peripheral Clocks Enable - bit_offset: 27 - bit_size: 1 - enum: C1_AHB1ENR_DMA1EN - - name: USB2ULPIEN - description: USB_PHY2 Clocks Enable - bit_offset: 28 - bit_size: 1 - enum: C1_AHB1ENR_DMA1EN -fieldset/C1_AHB1LPENR: - description: RCC AHB1 Sleep Clock Register - fields: - - name: DMA1LPEN - description: DMA1 Clock Enable During CSleep Mode - bit_offset: 0 - bit_size: 1 - enum: C1_AHB1LPENR_DMA1LPEN - - name: DMA2LPEN - description: DMA2 Clock Enable During CSleep Mode - bit_offset: 1 - bit_size: 1 - enum: C1_AHB1LPENR_DMA1LPEN - - name: ADC12LPEN - description: ADC1/2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 5 - bit_size: 1 - enum: C1_AHB1LPENR_DMA1LPEN - - name: ETH1MACLPEN - description: Ethernet MAC bus interface Clock Enable During CSleep Mode - bit_offset: 15 - bit_size: 1 - enum: C1_AHB1LPENR_DMA1LPEN - - name: ETH1TXLPEN - description: Ethernet Transmission Clock Enable During CSleep Mode - bit_offset: 16 - bit_size: 1 - enum: C1_AHB1LPENR_DMA1LPEN - - name: ETH1RXLPEN - description: Ethernet Reception Clock Enable During CSleep Mode - bit_offset: 17 - bit_size: 1 - enum: C1_AHB1LPENR_DMA1LPEN - - name: USB1OTGLPEN - description: USB1OTG peripheral clock enable during CSleep mode - bit_offset: 25 - bit_size: 1 - enum: C1_AHB1LPENR_DMA1LPEN - - name: USB1ULPILPEN - description: USB_PHY1 clock enable during CSleep mode - bit_offset: 26 - bit_size: 1 - enum: C1_AHB1LPENR_DMA1LPEN - - name: USB2OTGLPEN - description: USB2OTG peripheral clock enable during CSleep mode - bit_offset: 27 - bit_size: 1 - enum: C1_AHB1LPENR_DMA1LPEN - - name: USB2ULPILPEN - description: USB_PHY2 clocks enable during CSleep mode - bit_offset: 28 - bit_size: 1 - enum: C1_AHB1LPENR_DMA1LPEN -fieldset/C1_AHB2ENR: - description: RCC AHB2 Clock Register - fields: - - name: DCMIEN - description: DCMI peripheral clock - bit_offset: 0 - bit_size: 1 - enum: C1_AHB2ENR_DCMIEN - - name: CRYPTEN - description: CRYPT peripheral clock enable - bit_offset: 4 - bit_size: 1 - enum: C1_AHB2ENR_DCMIEN - - name: HASHEN - description: HASH peripheral clock enable - bit_offset: 5 - bit_size: 1 - enum: C1_AHB2ENR_DCMIEN - - name: RNGEN - description: RNG peripheral clocks enable - bit_offset: 6 - bit_size: 1 - enum: C1_AHB2ENR_DCMIEN - - name: SDMMC2EN - description: SDMMC2 and SDMMC2 delay clock enable - bit_offset: 9 - bit_size: 1 - enum: C1_AHB2ENR_DCMIEN - - name: SRAM1EN - description: SRAM1 block enable - bit_offset: 29 - bit_size: 1 - enum: C1_AHB2ENR_DCMIEN - - name: SRAM2EN - description: SRAM2 block enable - bit_offset: 30 - bit_size: 1 - enum: C1_AHB2ENR_DCMIEN - - name: SRAM3EN - description: SRAM3 block enable - bit_offset: 31 - bit_size: 1 - enum: C1_AHB2ENR_DCMIEN -fieldset/C1_AHB2LPENR: - description: RCC AHB2 Sleep Clock Register - fields: - - name: DCMILPEN - description: DCMI peripheral clock enable during csleep mode - bit_offset: 0 - bit_size: 1 - enum: C1_AHB2LPENR_DCMILPEN - - name: CRYPTLPEN - description: CRYPT peripheral clock enable during CSleep mode - bit_offset: 4 - bit_size: 1 - enum: C1_AHB2LPENR_DCMILPEN - - name: HASHLPEN - description: HASH peripheral clock enable during CSleep mode - bit_offset: 5 - bit_size: 1 - enum: C1_AHB2LPENR_DCMILPEN - - name: RNGLPEN - description: RNG peripheral clock enable during CSleep mode - bit_offset: 6 - bit_size: 1 - enum: C1_AHB2LPENR_DCMILPEN - - name: SDMMC2LPEN - description: SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode - bit_offset: 9 - bit_size: 1 - enum: C1_AHB2LPENR_DCMILPEN - - name: SRAM1LPEN - description: SRAM1 Clock Enable During CSleep Mode - bit_offset: 29 - bit_size: 1 - enum: C1_AHB2LPENR_DCMILPEN - - name: SRAM2LPEN - description: SRAM2 Clock Enable During CSleep Mode - bit_offset: 30 - bit_size: 1 - enum: C1_AHB2LPENR_DCMILPEN - - name: SRAM3LPEN - description: SRAM3 Clock Enable During CSleep Mode - bit_offset: 31 - bit_size: 1 - enum: C1_AHB2LPENR_DCMILPEN -fieldset/C1_AHB3ENR: - description: RCC AHB3 Clock Register - fields: - - name: MDMAEN - description: MDMA Peripheral Clock Enable - bit_offset: 0 - bit_size: 1 - enum: C1_AHB3ENR_MDMAEN - - name: DMA2DEN - description: DMA2D Peripheral Clock Enable - bit_offset: 4 - bit_size: 1 - enum: C1_AHB3ENR_MDMAEN - - name: JPGDECEN - description: JPGDEC Peripheral Clock Enable - bit_offset: 5 - bit_size: 1 - enum: C1_AHB3ENR_MDMAEN - - name: FMCEN - description: FMC Peripheral Clocks Enable - bit_offset: 12 - bit_size: 1 - enum: C1_AHB3ENR_MDMAEN - - name: QSPIEN - description: QUADSPI and QUADSPI Delay Clock Enable - bit_offset: 14 - bit_size: 1 - enum: C1_AHB3ENR_MDMAEN - - name: SDMMC1EN - description: SDMMC1 and SDMMC1 Delay Clock Enable - bit_offset: 16 - bit_size: 1 - enum: C1_AHB3ENR_MDMAEN -fieldset/C1_AHB3LPENR: - description: RCC AHB3 Sleep Clock Register - fields: - - name: MDMALPEN - description: MDMA Clock Enable During CSleep Mode - bit_offset: 0 - bit_size: 1 - enum: C1_AHB3LPENR_MDMALPEN - - name: DMA2DLPEN - description: DMA2D Clock Enable During CSleep Mode - bit_offset: 4 - bit_size: 1 - enum: C1_AHB3LPENR_MDMALPEN - - name: JPGDECLPEN - description: JPGDEC Clock Enable During CSleep Mode - bit_offset: 5 - bit_size: 1 - enum: C1_AHB3LPENR_MDMALPEN - - name: FLASHPREN - description: Flash interface clock enable during csleep mode - bit_offset: 8 - bit_size: 1 - - name: FMCLPEN - description: FMC Peripheral Clocks Enable During CSleep Mode - bit_offset: 12 - bit_size: 1 - enum: C1_AHB3LPENR_MDMALPEN - - name: QSPILPEN - description: QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode - bit_offset: 14 - bit_size: 1 - enum: C1_AHB3LPENR_MDMALPEN - - name: SDMMC1LPEN - description: SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode - bit_offset: 16 - bit_size: 1 - enum: C1_AHB3LPENR_MDMALPEN - - name: D1DTCM1LPEN - description: D1DTCM1 Block Clock Enable During CSleep mode - bit_offset: 28 - bit_size: 1 - enum: C1_AHB3LPENR_MDMALPEN - - name: DTCM2LPEN - description: D1 DTCM2 Block Clock Enable During CSleep mode - bit_offset: 29 - bit_size: 1 - enum: C1_AHB3LPENR_MDMALPEN - - name: ITCMLPEN - description: D1ITCM Block Clock Enable During CSleep mode - bit_offset: 30 - bit_size: 1 - enum: C1_AHB3LPENR_MDMALPEN - - name: AXISRAMLPEN - description: AXISRAM Block Clock Enable During CSleep mode - bit_offset: 31 - bit_size: 1 - enum: C1_AHB3LPENR_MDMALPEN -fieldset/C1_AHB4ENR: - description: RCC AHB4 Clock Register - fields: - - name: GPIOAEN - description: 0GPIO peripheral clock enable - bit_offset: 0 - bit_size: 1 - enum: C1_AHB4ENR_GPIOAEN - - name: GPIOBEN - description: 0GPIO peripheral clock enable - bit_offset: 1 - bit_size: 1 - enum: C1_AHB4ENR_GPIOAEN - - name: GPIOCEN - description: 0GPIO peripheral clock enable - bit_offset: 2 - bit_size: 1 - enum: C1_AHB4ENR_GPIOAEN - - name: GPIODEN - description: 0GPIO peripheral clock enable - bit_offset: 3 - bit_size: 1 - enum: C1_AHB4ENR_GPIOAEN - - name: GPIOEEN - description: 0GPIO peripheral clock enable - bit_offset: 4 - bit_size: 1 - enum: C1_AHB4ENR_GPIOAEN - - name: GPIOFEN - description: 0GPIO peripheral clock enable - bit_offset: 5 - bit_size: 1 - enum: C1_AHB4ENR_GPIOAEN - - name: GPIOGEN - description: 0GPIO peripheral clock enable - bit_offset: 6 - bit_size: 1 - enum: C1_AHB4ENR_GPIOAEN - - name: GPIOHEN - description: 0GPIO peripheral clock enable - bit_offset: 7 - bit_size: 1 - enum: C1_AHB4ENR_GPIOAEN - - name: GPIOIEN - description: 0GPIO peripheral clock enable - bit_offset: 8 - bit_size: 1 - enum: C1_AHB4ENR_GPIOAEN - - name: GPIOJEN - description: 0GPIO peripheral clock enable - bit_offset: 9 - bit_size: 1 - enum: C1_AHB4ENR_GPIOAEN - - name: GPIOKEN - description: 0GPIO peripheral clock enable - bit_offset: 10 - bit_size: 1 - enum: C1_AHB4ENR_GPIOAEN - - name: CRCEN - description: CRC peripheral clock enable - bit_offset: 19 - bit_size: 1 - enum: C1_AHB4ENR_GPIOAEN - - name: BDMAEN - description: BDMA and DMAMUX2 Clock Enable - bit_offset: 21 - bit_size: 1 - enum: C1_AHB4ENR_GPIOAEN - - name: ADC3EN - description: ADC3 Peripheral Clocks Enable - bit_offset: 24 - bit_size: 1 - enum: C1_AHB4ENR_GPIOAEN - - name: HSEMEN - description: HSEM peripheral clock enable - bit_offset: 25 - bit_size: 1 - enum: C1_AHB4ENR_GPIOAEN - - name: BKPRAMEN - description: Backup RAM Clock Enable - bit_offset: 28 - bit_size: 1 - enum: C1_AHB4ENR_GPIOAEN -fieldset/C1_AHB4LPENR: - description: RCC AHB4 Sleep Clock Register - fields: - - name: GPIOALPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 0 - bit_size: 1 - enum: C1_AHB4LPENR_GPIOALPEN - - name: GPIOBLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 1 - bit_size: 1 - enum: C1_AHB4LPENR_GPIOALPEN - - name: GPIOCLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 2 - bit_size: 1 - enum: C1_AHB4LPENR_GPIOALPEN - - name: GPIODLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 3 - bit_size: 1 - enum: C1_AHB4LPENR_GPIOALPEN - - name: GPIOELPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 4 - bit_size: 1 - enum: C1_AHB4LPENR_GPIOALPEN - - name: GPIOFLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 5 - bit_size: 1 - enum: C1_AHB4LPENR_GPIOALPEN - - name: GPIOGLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 6 - bit_size: 1 - enum: C1_AHB4LPENR_GPIOALPEN - - name: GPIOHLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 7 - bit_size: 1 - enum: C1_AHB4LPENR_GPIOALPEN - - name: GPIOILPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 8 - bit_size: 1 - enum: C1_AHB4LPENR_GPIOALPEN - - name: GPIOJLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 9 - bit_size: 1 - enum: C1_AHB4LPENR_GPIOALPEN - - name: GPIOKLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 10 - bit_size: 1 - enum: C1_AHB4LPENR_GPIOALPEN - - name: CRCLPEN - description: CRC peripheral clock enable during CSleep mode - bit_offset: 19 - bit_size: 1 - enum: C1_AHB4LPENR_GPIOALPEN - - name: BDMALPEN - description: BDMA Clock Enable During CSleep Mode - bit_offset: 21 - bit_size: 1 - enum: C1_AHB4LPENR_GPIOALPEN - - name: ADC3LPEN - description: ADC3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 24 - bit_size: 1 - enum: C1_AHB4LPENR_GPIOALPEN - - name: BKPRAMLPEN - description: Backup RAM Clock Enable During CSleep Mode - bit_offset: 28 - bit_size: 1 - enum: C1_AHB4LPENR_GPIOALPEN - - name: SRAM4LPEN - description: SRAM4 Clock Enable During CSleep Mode - bit_offset: 29 - bit_size: 1 - enum: C1_AHB4LPENR_GPIOALPEN -fieldset/C1_APB1HENR: - description: RCC APB1 Clock Register - fields: - - name: CRSEN - description: Clock Recovery System peripheral clock enable - bit_offset: 1 - bit_size: 1 - enum: C1_APB1HENR_CRSEN - - name: SWPEN - description: SWPMI Peripheral Clocks Enable - bit_offset: 2 - bit_size: 1 - enum: C1_APB1HENR_CRSEN - - name: OPAMPEN - description: OPAMP peripheral clock enable - bit_offset: 4 - bit_size: 1 - enum: C1_APB1HENR_CRSEN - - name: MDIOSEN - description: MDIOS peripheral clock enable - bit_offset: 5 - bit_size: 1 - enum: C1_APB1HENR_CRSEN - - name: FDCANEN - description: FDCAN Peripheral Clocks Enable - bit_offset: 8 - bit_size: 1 - enum: C1_APB1HENR_CRSEN -fieldset/C1_APB1HLPENR: - description: RCC APB1 High Sleep Clock Register - fields: - - name: CRSLPEN - description: Clock Recovery System peripheral clock enable during CSleep mode - bit_offset: 1 - bit_size: 1 - enum: C1_APB1HLPENR_CRSLPEN - - name: SWPLPEN - description: SWPMI Peripheral Clocks Enable During CSleep Mode - bit_offset: 2 - bit_size: 1 - enum: C1_APB1HLPENR_CRSLPEN - - name: OPAMPLPEN - description: OPAMP peripheral clock enable during CSleep mode - bit_offset: 4 - bit_size: 1 - enum: C1_APB1HLPENR_CRSLPEN - - name: MDIOSLPEN - description: MDIOS peripheral clock enable during CSleep mode - bit_offset: 5 - bit_size: 1 - enum: C1_APB1HLPENR_CRSLPEN - - name: FDCANLPEN - description: FDCAN Peripheral Clocks Enable During CSleep Mode - bit_offset: 8 - bit_size: 1 - enum: C1_APB1HLPENR_CRSLPEN -fieldset/C1_APB1LENR: - description: RCC APB1 Clock Register - fields: - - name: TIM2EN - description: TIM peripheral clock enable - bit_offset: 0 - bit_size: 1 - enum: C1_APB1LENR_TIM2EN - - name: TIM3EN - description: TIM peripheral clock enable - bit_offset: 1 - bit_size: 1 - enum: C1_APB1LENR_TIM2EN - - name: TIM4EN - description: TIM peripheral clock enable - bit_offset: 2 - bit_size: 1 - enum: C1_APB1LENR_TIM2EN - - name: TIM5EN - description: TIM peripheral clock enable - bit_offset: 3 - bit_size: 1 - enum: C1_APB1LENR_TIM2EN - - name: TIM6EN - description: TIM peripheral clock enable - bit_offset: 4 - bit_size: 1 - enum: C1_APB1LENR_TIM2EN - - name: TIM7EN - description: TIM peripheral clock enable - bit_offset: 5 - bit_size: 1 - enum: C1_APB1LENR_TIM2EN - - name: TIM12EN - description: TIM peripheral clock enable - bit_offset: 6 - bit_size: 1 - enum: C1_APB1LENR_TIM2EN - - name: TIM13EN - description: TIM peripheral clock enable - bit_offset: 7 - bit_size: 1 - enum: C1_APB1LENR_TIM2EN - - name: TIM14EN - description: TIM peripheral clock enable - bit_offset: 8 - bit_size: 1 - enum: C1_APB1LENR_TIM2EN - - name: LPTIM1EN - description: LPTIM1 Peripheral Clocks Enable - bit_offset: 9 - bit_size: 1 - enum: C1_APB1LENR_TIM2EN - - name: SPI2EN - description: SPI2 Peripheral Clocks Enable - bit_offset: 14 - bit_size: 1 - enum: C1_APB1LENR_TIM2EN - - name: SPI3EN - description: SPI3 Peripheral Clocks Enable - bit_offset: 15 - bit_size: 1 - enum: C1_APB1LENR_TIM2EN - - name: SPDIFRXEN - description: SPDIFRX Peripheral Clocks Enable - bit_offset: 16 - bit_size: 1 - enum: C1_APB1LENR_TIM2EN - - name: USART2EN - description: USART2 Peripheral Clocks Enable - bit_offset: 17 - bit_size: 1 - enum: C1_APB1LENR_TIM2EN - - name: USART3EN - description: USART3 Peripheral Clocks Enable - bit_offset: 18 - bit_size: 1 - enum: C1_APB1LENR_TIM2EN - - name: UART4EN - description: UART4 Peripheral Clocks Enable - bit_offset: 19 - bit_size: 1 - enum: C1_APB1LENR_TIM2EN - - name: UART5EN - description: UART5 Peripheral Clocks Enable - bit_offset: 20 - bit_size: 1 - enum: C1_APB1LENR_TIM2EN - - name: I2C1EN - description: I2C1 Peripheral Clocks Enable - bit_offset: 21 - bit_size: 1 - enum: C1_APB1LENR_TIM2EN - - name: I2C2EN - description: I2C2 Peripheral Clocks Enable - bit_offset: 22 - bit_size: 1 - enum: C1_APB1LENR_TIM2EN - - name: I2C3EN - description: I2C3 Peripheral Clocks Enable - bit_offset: 23 - bit_size: 1 - enum: C1_APB1LENR_TIM2EN - - name: CECEN - description: HDMI-CEC peripheral clock enable - bit_offset: 27 - bit_size: 1 - enum: C1_APB1LENR_TIM2EN - - name: DAC12EN - description: DAC1&2 peripheral clock enable - bit_offset: 29 - bit_size: 1 - enum: C1_APB1LENR_TIM2EN - - name: UART7EN - description: UART7 Peripheral Clocks Enable - bit_offset: 30 - bit_size: 1 - enum: C1_APB1LENR_TIM2EN - - name: UART8EN - description: UART8 Peripheral Clocks Enable - bit_offset: 31 - bit_size: 1 - enum: C1_APB1LENR_TIM2EN -fieldset/C1_APB1LLPENR: - description: RCC APB1 Low Sleep Clock Register - fields: - - name: TIM2LPEN - description: TIM2 peripheral clock enable during CSleep mode - bit_offset: 0 - bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN - - name: TIM3LPEN - description: TIM3 peripheral clock enable during CSleep mode - bit_offset: 1 - bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN - - name: TIM4LPEN - description: TIM4 peripheral clock enable during CSleep mode - bit_offset: 2 - bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN - - name: TIM5LPEN - description: TIM5 peripheral clock enable during CSleep mode - bit_offset: 3 - bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN - - name: TIM6LPEN - description: TIM6 peripheral clock enable during CSleep mode - bit_offset: 4 - bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN - - name: TIM7LPEN - description: TIM7 peripheral clock enable during CSleep mode - bit_offset: 5 - bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN - - name: TIM12LPEN - description: TIM12 peripheral clock enable during CSleep mode - bit_offset: 6 - bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN - - name: TIM13LPEN - description: TIM13 peripheral clock enable during CSleep mode - bit_offset: 7 - bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN - - name: TIM14LPEN - description: TIM14 peripheral clock enable during CSleep mode - bit_offset: 8 - bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN - - name: LPTIM1LPEN - description: LPTIM1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 9 - bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN - - name: SPI2LPEN - description: SPI2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 14 - bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN - - name: SPI3LPEN - description: SPI3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 15 - bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN - - name: SPDIFRXLPEN - description: SPDIFRX Peripheral Clocks Enable During CSleep Mode - bit_offset: 16 - bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN - - name: USART2LPEN - description: USART2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 17 - bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN - - name: USART3LPEN - description: USART3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 18 - bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN - - name: UART4LPEN - description: UART4 Peripheral Clocks Enable During CSleep Mode - bit_offset: 19 - bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN - - name: UART5LPEN - description: UART5 Peripheral Clocks Enable During CSleep Mode - bit_offset: 20 - bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN - - name: I2C1LPEN - description: I2C1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 21 - bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN - - name: I2C2LPEN - description: I2C2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 22 - bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN - - name: I2C3LPEN - description: I2C3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 23 - bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN - - name: CECLPEN - description: HDMI-CEC Peripheral Clocks Enable During CSleep Mode - bit_offset: 27 - bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN - - name: DAC12LPEN - description: DAC1/2 peripheral clock enable during CSleep mode - bit_offset: 29 - bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN - - name: UART7LPEN - description: UART7 Peripheral Clocks Enable During CSleep Mode - bit_offset: 30 - bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN - - name: UART8LPEN - description: UART8 Peripheral Clocks Enable During CSleep Mode - bit_offset: 31 - bit_size: 1 - enum: C1_APB1LLPENR_TIM2LPEN -fieldset/C1_APB2ENR: - description: RCC APB2 Clock Register - fields: - - name: TIM1EN - description: TIM1 peripheral clock enable - bit_offset: 0 - bit_size: 1 - enum: C1_APB2ENR_TIM1EN - - name: TIM8EN - description: TIM8 peripheral clock enable - bit_offset: 1 - bit_size: 1 - enum: C1_APB2ENR_TIM1EN - - name: USART1EN - description: USART1 Peripheral Clocks Enable - bit_offset: 4 - bit_size: 1 - enum: C1_APB2ENR_TIM1EN - - name: USART6EN - description: USART6 Peripheral Clocks Enable - bit_offset: 5 - bit_size: 1 - enum: C1_APB2ENR_TIM1EN - - name: SPI1EN - description: SPI1 Peripheral Clocks Enable - bit_offset: 12 - bit_size: 1 - enum: C1_APB2ENR_TIM1EN - - name: SPI4EN - description: SPI4 Peripheral Clocks Enable - bit_offset: 13 - bit_size: 1 - enum: C1_APB2ENR_TIM1EN - - name: TIM15EN - description: TIM15 peripheral clock enable - bit_offset: 16 - bit_size: 1 - enum: C1_APB2ENR_TIM1EN - - name: TIM16EN - description: TIM16 peripheral clock enable - bit_offset: 17 - bit_size: 1 - enum: C1_APB2ENR_TIM1EN - - name: TIM17EN - description: TIM17 peripheral clock enable - bit_offset: 18 - bit_size: 1 - enum: C1_APB2ENR_TIM1EN - - name: SPI5EN - description: SPI5 Peripheral Clocks Enable - bit_offset: 20 - bit_size: 1 - enum: C1_APB2ENR_TIM1EN - - name: SAI1EN - description: SAI1 Peripheral Clocks Enable - bit_offset: 22 - bit_size: 1 - enum: C1_APB2ENR_TIM1EN - - name: SAI2EN - description: SAI2 Peripheral Clocks Enable - bit_offset: 23 - bit_size: 1 - enum: C1_APB2ENR_TIM1EN - - name: SAI3EN - description: SAI3 Peripheral Clocks Enable - bit_offset: 24 - bit_size: 1 - enum: C1_APB2ENR_TIM1EN - - name: DFSDM1EN - description: DFSDM1 Peripheral Clocks Enable - bit_offset: 28 - bit_size: 1 - enum: C1_APB2ENR_TIM1EN - - name: HRTIMEN - description: HRTIM peripheral clock enable - bit_offset: 29 - bit_size: 1 - enum: C1_APB2ENR_TIM1EN -fieldset/C1_APB2LPENR: - description: RCC APB2 Sleep Clock Register - fields: - - name: TIM1LPEN - description: TIM1 peripheral clock enable during CSleep mode - bit_offset: 0 - bit_size: 1 - enum: C1_APB2LPENR_TIM1LPEN - - name: TIM8LPEN - description: TIM8 peripheral clock enable during CSleep mode - bit_offset: 1 - bit_size: 1 - enum: C1_APB2LPENR_TIM1LPEN - - name: USART1LPEN - description: USART1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 4 - bit_size: 1 - enum: C1_APB2LPENR_TIM1LPEN - - name: USART6LPEN - description: USART6 Peripheral Clocks Enable During CSleep Mode - bit_offset: 5 - bit_size: 1 - enum: C1_APB2LPENR_TIM1LPEN - - name: SPI1LPEN - description: SPI1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 12 - bit_size: 1 - enum: C1_APB2LPENR_TIM1LPEN - - name: SPI4LPEN - description: SPI4 Peripheral Clocks Enable During CSleep Mode - bit_offset: 13 - bit_size: 1 - enum: C1_APB2LPENR_TIM1LPEN - - name: TIM15LPEN - description: TIM15 peripheral clock enable during CSleep mode - bit_offset: 16 - bit_size: 1 - enum: C1_APB2LPENR_TIM1LPEN - - name: TIM16LPEN - description: TIM16 peripheral clock enable during CSleep mode - bit_offset: 17 - bit_size: 1 - enum: C1_APB2LPENR_TIM1LPEN - - name: TIM17LPEN - description: TIM17 peripheral clock enable during CSleep mode - bit_offset: 18 - bit_size: 1 - enum: C1_APB2LPENR_TIM1LPEN - - name: SPI5LPEN - description: SPI5 Peripheral Clocks Enable During CSleep Mode - bit_offset: 20 - bit_size: 1 - enum: C1_APB2LPENR_TIM1LPEN - - name: SAI1LPEN - description: SAI1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 22 - bit_size: 1 - enum: C1_APB2LPENR_TIM1LPEN - - name: SAI2LPEN - description: SAI2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 23 - bit_size: 1 - enum: C1_APB2LPENR_TIM1LPEN - - name: SAI3LPEN - description: SAI3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 24 - bit_size: 1 - enum: C1_APB2LPENR_TIM1LPEN - - name: DFSDM1LPEN - description: DFSDM1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 28 - bit_size: 1 - enum: C1_APB2LPENR_TIM1LPEN - - name: HRTIMLPEN - description: HRTIM peripheral clock enable during CSleep mode - bit_offset: 29 - bit_size: 1 - enum: C1_APB2LPENR_TIM1LPEN -fieldset/C1_APB3ENR: - description: RCC APB3 Clock Register - fields: - - name: LTDCEN - description: LTDC peripheral clock enable - bit_offset: 3 - bit_size: 1 - enum: C1_APB3ENR_LTDCEN - - name: WWDG1EN - description: WWDG1 Clock Enable - bit_offset: 6 - bit_size: 1 - enum: C1_APB3ENR_LTDCEN -fieldset/C1_APB3LPENR: - description: RCC APB3 Sleep Clock Register - fields: - - name: LTDCLPEN - description: LTDC peripheral clock enable during CSleep mode - bit_offset: 3 - bit_size: 1 - enum: C1_APB3LPENR_LTDCLPEN - - name: WWDG1LPEN - description: WWDG1 Clock Enable During CSleep Mode - bit_offset: 6 - bit_size: 1 - enum: C1_APB3LPENR_LTDCLPEN -fieldset/C1_APB4ENR: - description: RCC APB4 Clock Register - fields: - - name: SYSCFGEN - description: SYSCFG peripheral clock enable - bit_offset: 1 - bit_size: 1 - enum: C1_APB4ENR_SYSCFGEN - - name: LPUART1EN - description: LPUART1 Peripheral Clocks Enable - bit_offset: 3 - bit_size: 1 - enum: C1_APB4ENR_SYSCFGEN - - name: SPI6EN - description: SPI6 Peripheral Clocks Enable - bit_offset: 5 - bit_size: 1 - enum: C1_APB4ENR_SYSCFGEN - - name: I2C4EN - description: I2C4 Peripheral Clocks Enable - bit_offset: 7 - bit_size: 1 - enum: C1_APB4ENR_SYSCFGEN - - name: LPTIM2EN - description: LPTIM2 Peripheral Clocks Enable - bit_offset: 9 - bit_size: 1 - enum: C1_APB4ENR_SYSCFGEN - - name: LPTIM3EN - description: LPTIM3 Peripheral Clocks Enable - bit_offset: 10 - bit_size: 1 - enum: C1_APB4ENR_SYSCFGEN - - name: LPTIM4EN - description: LPTIM4 Peripheral Clocks Enable - bit_offset: 11 - bit_size: 1 - enum: C1_APB4ENR_SYSCFGEN - - name: LPTIM5EN - description: LPTIM5 Peripheral Clocks Enable - bit_offset: 12 - bit_size: 1 - enum: C1_APB4ENR_SYSCFGEN - - name: COMP12EN - description: COMP1/2 peripheral clock enable - bit_offset: 14 - bit_size: 1 - enum: C1_APB4ENR_SYSCFGEN - - name: VREFEN - description: VREF peripheral clock enable - bit_offset: 15 - bit_size: 1 - enum: C1_APB4ENR_SYSCFGEN - - name: RTCAPBEN - description: RTC APB Clock Enable - bit_offset: 16 - bit_size: 1 - enum: C1_APB4ENR_SYSCFGEN - - name: SAI4EN - description: SAI4 Peripheral Clocks Enable - bit_offset: 21 - bit_size: 1 - enum: C1_APB4ENR_SYSCFGEN -fieldset/C1_APB4LPENR: - description: RCC APB4 Sleep Clock Register - fields: - - name: SYSCFGLPEN - description: SYSCFG peripheral clock enable during CSleep mode - bit_offset: 1 - bit_size: 1 - enum: C1_APB4LPENR_SYSCFGLPEN - - name: LPUART1LPEN - description: LPUART1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 3 - bit_size: 1 - enum: C1_APB4LPENR_SYSCFGLPEN - - name: SPI6LPEN - description: SPI6 Peripheral Clocks Enable During CSleep Mode - bit_offset: 5 - bit_size: 1 - enum: C1_APB4LPENR_SYSCFGLPEN - - name: I2C4LPEN - description: I2C4 Peripheral Clocks Enable During CSleep Mode - bit_offset: 7 - bit_size: 1 - enum: C1_APB4LPENR_SYSCFGLPEN - - name: LPTIM2LPEN - description: LPTIM2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 9 - bit_size: 1 - enum: C1_APB4LPENR_SYSCFGLPEN - - name: LPTIM3LPEN - description: LPTIM3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 10 - bit_size: 1 - enum: C1_APB4LPENR_SYSCFGLPEN - - name: LPTIM4LPEN - description: LPTIM4 Peripheral Clocks Enable During CSleep Mode - bit_offset: 11 - bit_size: 1 - enum: C1_APB4LPENR_SYSCFGLPEN - - name: LPTIM5LPEN - description: LPTIM5 Peripheral Clocks Enable During CSleep Mode - bit_offset: 12 - bit_size: 1 - enum: C1_APB4LPENR_SYSCFGLPEN - - name: COMP12LPEN - description: COMP1/2 peripheral clock enable during CSleep mode - bit_offset: 14 - bit_size: 1 - enum: C1_APB4LPENR_SYSCFGLPEN - - name: VREFLPEN - description: VREF peripheral clock enable during CSleep mode - bit_offset: 15 - bit_size: 1 - enum: C1_APB4LPENR_SYSCFGLPEN - - name: RTCAPBLPEN - description: RTC APB Clock Enable During CSleep Mode - bit_offset: 16 - bit_size: 1 - enum: C1_APB4LPENR_SYSCFGLPEN - - name: SAI4LPEN - description: SAI4 Peripheral Clocks Enable During CSleep Mode - bit_offset: 21 - bit_size: 1 - enum: C1_APB4LPENR_SYSCFGLPEN -fieldset/C1_RSR: - description: RCC Reset Status Register - fields: - - name: RMVF - description: Remove reset flag - bit_offset: 16 - bit_size: 1 - enum: C1_RSR_RMVF - - name: CPURSTF - description: CPU reset flag - bit_offset: 17 - bit_size: 1 - enum_read: C1_RSR_CPURSTFR - - name: D1RSTF - description: D1 domain power switch reset flag - bit_offset: 19 - bit_size: 1 - enum_read: C1_RSR_CPURSTFR - - name: D2RSTF - description: D2 domain power switch reset flag - bit_offset: 20 - bit_size: 1 - enum_read: C1_RSR_CPURSTFR - - name: BORRSTF - description: BOR reset flag - bit_offset: 21 - bit_size: 1 - enum_read: C1_RSR_CPURSTFR - - name: PINRSTF - description: Pin reset flag (NRST) - bit_offset: 22 - bit_size: 1 - enum_read: C1_RSR_CPURSTFR - - name: PORRSTF - description: POR/PDR reset flag - bit_offset: 23 - bit_size: 1 - enum_read: C1_RSR_CPURSTFR - - name: SFTRSTF - description: System reset from CPU reset flag - bit_offset: 24 - bit_size: 1 - enum_read: C1_RSR_CPURSTFR - - name: IWDG1RSTF - description: Independent Watchdog reset flag - bit_offset: 26 - bit_size: 1 - enum_read: C1_RSR_CPURSTFR - - name: WWDG1RSTF - description: Window Watchdog reset flag - bit_offset: 28 - bit_size: 1 - enum_read: C1_RSR_CPURSTFR - - name: LPWRRSTF - description: Reset due to illegal D1 DStandby or CPU CStop flag - bit_offset: 30 - bit_size: 1 - enum_read: C1_RSR_CPURSTFR -fieldset/CFGR: - description: RCC Clock Configuration Register - fields: - - name: SW - description: System clock switch - bit_offset: 0 - bit_size: 3 - enum: SW - - name: SWS - description: System clock switch status - bit_offset: 3 - bit_size: 3 - enum_read: SWSR - - name: STOPWUCK - description: System clock selection after a wake up from system Stop - bit_offset: 6 - bit_size: 1 - enum: STOPWUCK - - name: STOPKERWUCK - description: Kernel clock selection after a wake up from system Stop - bit_offset: 7 - bit_size: 1 - enum: STOPWUCK - - name: RTCPRE - description: HSE division factor for RTC clock - bit_offset: 8 - bit_size: 6 - - name: HRTIMSEL - description: High Resolution Timer clock prescaler selection - bit_offset: 14 - bit_size: 1 - enum: HRTIMSEL - - name: TIMPRE - description: Timers clocks prescaler selection - bit_offset: 15 - bit_size: 1 - enum: TIMPRE - - name: MCO1PRE - description: MCO1 prescaler - bit_offset: 18 - bit_size: 4 - - name: MCO1 - description: Micro-controller clock output 1 - bit_offset: 22 - bit_size: 3 - enum: MCO1 - - name: MCO2PRE - description: MCO2 prescaler - bit_offset: 25 - bit_size: 4 - - name: MCO2 - description: Micro-controller clock output 2 - bit_offset: 29 - bit_size: 3 - enum: MCO2 -fieldset/CICR: - description: RCC Clock Source Interrupt Clear Register - fields: - - name: LSIRDYC - description: LSI ready Interrupt Clear - bit_offset: 0 - bit_size: 1 - enum: LSIRDYC - - name: LSERDYC - description: LSE ready Interrupt Clear - bit_offset: 1 - bit_size: 1 - enum: LSIRDYC - - name: HSIRDYC - description: HSI ready Interrupt Clear - bit_offset: 2 - bit_size: 1 - enum: LSIRDYC - - name: HSERDYC - description: HSE ready Interrupt Clear - bit_offset: 3 - bit_size: 1 - enum: LSIRDYC - - name: HSE_ready_Interrupt_Clear - description: CSI ready Interrupt Clear - bit_offset: 4 - bit_size: 1 - - name: HSI48RDYC - description: RC48 ready Interrupt Clear - bit_offset: 5 - bit_size: 1 - enum: LSIRDYC - - name: PLLRDYC - description: PLL1 ready Interrupt Clear - bit_offset: 6 - bit_size: 1 - array: - len: 3 - stride: 1 - enum: LSIRDYC - - name: LSECSSC - description: LSE clock security system Interrupt Clear - bit_offset: 9 - bit_size: 1 - enum: LSIRDYC - - name: HSECSSC - description: HSE clock security system Interrupt Clear - bit_offset: 10 - bit_size: 1 - enum: LSIRDYC -fieldset/CIER: - description: RCC Clock Source Interrupt Enable Register - fields: - - name: LSIRDYIE - description: LSI ready Interrupt Enable - bit_offset: 0 - bit_size: 1 - enum: LSIRDYIE - - name: LSERDYIE - description: LSE ready Interrupt Enable - bit_offset: 1 - bit_size: 1 - enum: LSIRDYIE - - name: HSIRDYIE - description: HSI ready Interrupt Enable - bit_offset: 2 - bit_size: 1 - enum: LSIRDYIE - - name: HSERDYIE - description: HSE ready Interrupt Enable - bit_offset: 3 - bit_size: 1 - enum: LSIRDYIE - - name: CSIRDYIE - description: CSI ready Interrupt Enable - bit_offset: 4 - bit_size: 1 - enum: LSIRDYIE - - name: HSI48RDYIE - description: RC48 ready Interrupt Enable - bit_offset: 5 - bit_size: 1 - enum: LSIRDYIE - - name: PLLRDYIE - description: PLL1 ready Interrupt Enable - bit_offset: 6 - bit_size: 1 - array: - len: 3 - stride: 1 - enum: LSIRDYIE - - name: LSECSSIE - description: LSE clock security system Interrupt Enable - bit_offset: 9 - bit_size: 1 - enum: LSIRDYIE -fieldset/CIFR: - description: RCC Clock Source Interrupt Flag Register - fields: - - name: LSIRDYF - description: LSI ready Interrupt Flag - bit_offset: 0 - bit_size: 1 - - name: LSERDYF - description: LSE ready Interrupt Flag - bit_offset: 1 - bit_size: 1 - - name: HSIRDYF - description: HSI ready Interrupt Flag - bit_offset: 2 - bit_size: 1 - - name: HSERDYF - description: HSE ready Interrupt Flag - bit_offset: 3 - bit_size: 1 - - name: CSIRDY - description: CSI ready Interrupt Flag - bit_offset: 4 - bit_size: 1 - - name: HSI48RDYF - description: RC48 ready Interrupt Flag - bit_offset: 5 - bit_size: 1 - - name: PLLRDYF - description: PLL1 ready Interrupt Flag - bit_offset: 6 - bit_size: 1 - array: - len: 3 - stride: 1 - - name: LSECSSF - description: LSE clock security system Interrupt Flag - bit_offset: 9 - bit_size: 1 - - name: HSECSSF - description: HSE clock security system Interrupt Flag - bit_offset: 10 - bit_size: 1 -fieldset/CR: - description: clock control register - fields: - - name: HSION - description: Internal high-speed clock enable - bit_offset: 0 - bit_size: 1 - enum: HSION - - name: HSIKERON - description: High Speed Internal clock enable in Stop mode - bit_offset: 1 - bit_size: 1 - enum: HSION - - name: HSIRDY - description: HSI clock ready flag - bit_offset: 2 - bit_size: 1 - enum_read: HSIRDYR - - name: HSIDIV - description: HSI clock divider - bit_offset: 3 - bit_size: 2 - enum: HSIDIV - - name: HSIDIVF - description: HSI divider flag - bit_offset: 5 - bit_size: 1 - enum_read: HSIDIVFR - - name: CSION - description: CSI clock enable - bit_offset: 7 - bit_size: 1 - enum: HSION - - name: CSIRDY - description: CSI clock ready flag - bit_offset: 8 - bit_size: 1 - enum_read: HSIRDYR - - name: CSIKERON - description: CSI clock enable in Stop mode - bit_offset: 9 - bit_size: 1 - enum: HSION - - name: HSI48ON - description: RC48 clock enable - bit_offset: 12 - bit_size: 1 - enum: HSION - - name: HSI48RDY - description: RC48 clock ready flag - bit_offset: 13 - bit_size: 1 - enum_read: HSIRDYR - - name: D1CKRDY - description: D1 domain clocks ready flag - bit_offset: 14 - bit_size: 1 - enum_read: HSIRDYR - - name: D2CKRDY - description: D2 domain clocks ready flag - bit_offset: 15 - bit_size: 1 - enum_read: HSIRDYR - - name: HSEON - description: HSE clock enable - bit_offset: 16 - bit_size: 1 - enum: HSION - - name: HSERDY - description: HSE clock ready flag - bit_offset: 17 - bit_size: 1 - enum_read: HSIRDYR - - name: HSEBYP - description: HSE clock bypass - bit_offset: 18 - bit_size: 1 - enum: HSEBYP - - name: HSECSSON - description: HSE Clock Security System enable - bit_offset: 19 - bit_size: 1 - enum: HSION - - name: PLL1ON - description: PLL1 enable - bit_offset: 24 - bit_size: 1 - enum: HSION - - name: PLL1RDY - description: PLL1 clock ready flag - bit_offset: 25 - bit_size: 1 - enum_read: HSIRDYR - - name: PLL2ON - description: PLL2 enable - bit_offset: 26 - bit_size: 1 - enum: HSION - - name: PLL2RDY - description: PLL2 clock ready flag - bit_offset: 27 - bit_size: 1 - enum_read: HSIRDYR - - name: PLL3ON - description: PLL3 enable - bit_offset: 28 - bit_size: 1 - enum: HSION - - name: PLL3RDY - description: PLL3 clock ready flag - bit_offset: 29 - bit_size: 1 - enum_read: HSIRDYR -fieldset/CRRCR: - description: RCC Clock Recovery RC Register - fields: - - name: HSI48CAL - description: Internal RC 48 MHz clock calibration - bit_offset: 0 - bit_size: 10 -fieldset/CSICFGR: - description: RCC CSI configuration register - fields: - - name: CSICAL - description: CSI clock calibration - bit_offset: 0 - bit_size: 9 - - name: CSITRIM - description: CSI clock trimming - bit_offset: 24 - bit_size: 6 -fieldset/CSR: - description: RCC Clock Control and Status Register - fields: - - name: LSION - description: LSI oscillator enable - bit_offset: 0 - bit_size: 1 - enum: LSION - - name: LSIRDY - description: LSI oscillator ready - bit_offset: 1 - bit_size: 1 - enum_read: LSIRDYR -fieldset/D1CCIPR: - description: RCC Domain 1 Kernel Clock Configuration Register - fields: - - name: FMCSEL - description: FMC kernel clock source selection - bit_offset: 0 - bit_size: 2 - enum: FMCSEL - - name: QSPISEL - description: QUADSPI kernel clock source selection - bit_offset: 4 - bit_size: 2 - enum: FMCSEL - - name: SDMMCSEL - description: SDMMC kernel clock source selection - bit_offset: 16 - bit_size: 1 - enum: SDMMCSEL - - name: CKPERSEL - description: per_ck clock source selection - bit_offset: 28 - bit_size: 2 - enum: CKPERSEL -fieldset/D1CFGR: - description: RCC Domain 1 Clock Configuration Register - fields: - - name: HPRE - description: D1 domain AHB prescaler - bit_offset: 0 - bit_size: 4 - enum: HPRE - - name: D1PPRE - description: D1 domain APB3 prescaler - bit_offset: 4 - bit_size: 3 - enum: D1PPRE - - name: D1CPRE - description: D1 domain Core prescaler - bit_offset: 8 - bit_size: 4 - enum: HPRE -fieldset/D2CCIP1R: - description: RCC Domain 2 Kernel Clock Configuration Register - fields: - - name: SAI1SEL - description: SAI1 and DFSDM1 kernel Aclk clock source selection - bit_offset: 0 - bit_size: 3 - enum: SAI1SEL - - name: SAI23SEL - description: SAI2 and SAI3 kernel clock source selection - bit_offset: 6 - bit_size: 3 - enum: SAI1SEL - - name: SPI123SEL - description: "SPI/I2S1,2 and 3 kernel clock source selection" - bit_offset: 12 - bit_size: 3 - enum: SAI1SEL - - name: SPI45SEL - description: SPI4 and 5 kernel clock source selection - bit_offset: 16 - bit_size: 3 - enum: SPI45SEL - - name: SPDIFSEL - description: SPDIFRX kernel clock source selection - bit_offset: 20 - bit_size: 2 - enum: SPDIFSEL - - name: DFSDM1SEL - description: DFSDM1 kernel Clk clock source selection - bit_offset: 24 - bit_size: 1 - enum: DFSDM1SEL - - name: FDCANSEL - description: FDCAN kernel clock source selection - bit_offset: 28 - bit_size: 2 - enum: FDCANSEL - - name: SWPSEL - description: SWPMI kernel clock source selection - bit_offset: 31 - bit_size: 1 - enum: SWPSEL -fieldset/D2CCIP2R: - description: RCC Domain 2 Kernel Clock Configuration Register - fields: - - name: USART234578SEL - description: "USART2/3, UART4,5, 7/8 (APB1) kernel clock source selection" - bit_offset: 0 - bit_size: 3 - enum: USART234578SEL - - name: USART16SEL - description: USART1 and 6 kernel clock source selection - bit_offset: 3 - bit_size: 3 - enum: USART16SEL - - name: RNGSEL - description: RNG kernel clock source selection - bit_offset: 8 - bit_size: 2 - enum: RNGSEL - - name: I2C123SEL - description: "I2C1,2,3 kernel clock source selection" - bit_offset: 12 - bit_size: 2 - enum: I2C123SEL - - name: USBSEL - description: USBOTG 1 and 2 kernel clock source selection - bit_offset: 20 - bit_size: 2 - enum: USBSEL - - name: CECSEL - description: HDMI-CEC kernel clock source selection - bit_offset: 22 - bit_size: 2 - enum: CECSEL - - name: LPTIM1SEL - description: LPTIM1 kernel clock source selection - bit_offset: 28 - bit_size: 3 - enum: LPTIM1SEL -fieldset/D2CFGR: - description: RCC Domain 2 Clock Configuration Register - fields: - - name: D2PPRE1 - description: D2 domain APB1 prescaler - bit_offset: 4 - bit_size: 3 - enum: D2PPRE1 - - name: D2PPRE2 - description: D2 domain APB2 prescaler - bit_offset: 8 - bit_size: 3 - enum: D2PPRE1 -fieldset/D3AMR: - description: RCC D3 Autonomous mode Register - fields: - - name: BDMAAMEN - description: BDMA and DMAMUX Autonomous mode enable - bit_offset: 0 - bit_size: 1 - enum: BDMAAMEN - - name: LPUART1AMEN - description: LPUART1 Autonomous mode enable - bit_offset: 3 - bit_size: 1 - enum: BDMAAMEN - - name: SPI6AMEN - description: SPI6 Autonomous mode enable - bit_offset: 5 - bit_size: 1 - enum: BDMAAMEN - - name: I2C4AMEN - description: I2C4 Autonomous mode enable - bit_offset: 7 - bit_size: 1 - enum: BDMAAMEN - - name: LPTIM2AMEN - description: LPTIM2 Autonomous mode enable - bit_offset: 9 - bit_size: 1 - enum: BDMAAMEN - - name: LPTIM3AMEN - description: LPTIM3 Autonomous mode enable - bit_offset: 10 - bit_size: 1 - enum: BDMAAMEN - - name: LPTIM4AMEN - description: LPTIM4 Autonomous mode enable - bit_offset: 11 - bit_size: 1 - enum: BDMAAMEN - - name: LPTIM5AMEN - description: LPTIM5 Autonomous mode enable - bit_offset: 12 - bit_size: 1 - enum: BDMAAMEN - - name: COMP12AMEN - description: COMP12 Autonomous mode enable - bit_offset: 14 - bit_size: 1 - enum: BDMAAMEN - - name: VREFAMEN - description: VREF Autonomous mode enable - bit_offset: 15 - bit_size: 1 - enum: BDMAAMEN - - name: RTCAMEN - description: RTC Autonomous mode enable - bit_offset: 16 - bit_size: 1 - enum: BDMAAMEN - - name: CRCAMEN - description: CRC Autonomous mode enable - bit_offset: 19 - bit_size: 1 - enum: BDMAAMEN - - name: SAI4AMEN - description: SAI4 Autonomous mode enable - bit_offset: 21 - bit_size: 1 - enum: BDMAAMEN - - name: ADC3AMEN - description: ADC3 Autonomous mode enable - bit_offset: 24 - bit_size: 1 - enum: BDMAAMEN - - name: BKPRAMAMEN - description: Backup RAM Autonomous mode enable - bit_offset: 28 - bit_size: 1 - enum: BDMAAMEN - - name: SRAM4AMEN - description: SRAM4 Autonomous mode enable - bit_offset: 29 - bit_size: 1 - enum: BDMAAMEN -fieldset/D3CCIPR: - description: RCC Domain 3 Kernel Clock Configuration Register - fields: - - name: LPUART1SEL - description: LPUART1 kernel clock source selection - bit_offset: 0 - bit_size: 3 - enum: LPUART1SEL - - name: I2C4SEL - description: I2C4 kernel clock source selection - bit_offset: 8 - bit_size: 2 - enum: I2C4SEL - - name: LPTIM2SEL - description: LPTIM2 kernel clock source selection - bit_offset: 10 - bit_size: 3 - enum: LPTIM2SEL - - name: LPTIM345SEL - description: "LPTIM3,4,5 kernel clock source selection" - bit_offset: 13 - bit_size: 3 - enum: LPTIM2SEL - - name: ADCSEL - description: SAR ADC kernel clock source selection - bit_offset: 16 - bit_size: 2 - enum: ADCSEL - - name: SAI4ASEL - description: Sub-Block A of SAI4 kernel clock source selection - bit_offset: 21 - bit_size: 3 - enum: SAI4ASEL - - name: SAI4BSEL - description: Sub-Block B of SAI4 kernel clock source selection - bit_offset: 24 - bit_size: 3 - enum: SAI4ASEL - - name: SPI6SEL - description: SPI6 kernel clock source selection - bit_offset: 28 - bit_size: 3 - enum: SPI6SEL -fieldset/D3CFGR: - description: RCC Domain 3 Clock Configuration Register - fields: - - name: D3PPRE - description: D3 domain APB4 prescaler - bit_offset: 4 - bit_size: 3 - enum: D3PPRE -fieldset/GCR: - description: RCC Global Control Register - fields: - - name: WW1RSC - description: WWDG1 reset scope control - bit_offset: 0 - bit_size: 1 - enum: WW1RSC -fieldset/HSICFGR: - description: RCC HSI configuration register - fields: - - name: HSICAL - description: HSI clock calibration - bit_offset: 0 - bit_size: 12 - - name: HSITRIM - description: HSI clock trimming - bit_offset: 24 - bit_size: 7 -fieldset/ICSCR: - description: RCC Internal Clock Source Calibration Register - fields: - - name: HSICAL - description: HSI clock calibration - bit_offset: 0 - bit_size: 12 - - name: HSITRIM - description: HSI clock trimming - bit_offset: 12 - bit_size: 6 - - name: CSICAL - description: CSI clock calibration - bit_offset: 18 - bit_size: 8 - - name: CSITRIM - description: CSI clock trimming - bit_offset: 26 - bit_size: 5 -fieldset/PLL1DIVR: - description: RCC PLL1 Dividers Configuration Register - fields: - - name: DIVN1 - description: Multiplication factor for PLL1 VCO - bit_offset: 0 - bit_size: 9 - - name: DIVP1 - description: PLL1 DIVP division factor - bit_offset: 9 - bit_size: 7 - enum: DIVP1 - - name: DIVQ1 - description: PLL1 DIVQ division factor - bit_offset: 16 - bit_size: 7 - - name: DIVR1 - description: PLL1 DIVR division factor - bit_offset: 24 - bit_size: 7 -fieldset/PLL1FRACR: - description: RCC PLL1 Fractional Divider Register - fields: - - name: FRACN1 - description: Fractional part of the multiplication factor for PLL1 VCO - bit_offset: 3 - bit_size: 13 -fieldset/PLL2DIVR: - description: RCC PLL2 Dividers Configuration Register - fields: - - name: DIVN2 - description: Multiplication factor for PLL1 VCO - bit_offset: 0 - bit_size: 9 - - name: DIVP2 - description: PLL1 DIVP division factor - bit_offset: 9 - bit_size: 7 - - name: DIVQ2 - description: PLL1 DIVQ division factor - bit_offset: 16 - bit_size: 7 - - name: DIVR2 - description: PLL1 DIVR division factor - bit_offset: 24 - bit_size: 7 -fieldset/PLL2FRACR: - description: RCC PLL2 Fractional Divider Register - fields: - - name: FRACN2 - description: Fractional part of the multiplication factor for PLL VCO - bit_offset: 3 - bit_size: 13 -fieldset/PLL3DIVR: - description: RCC PLL3 Dividers Configuration Register - fields: - - name: DIVN3 - description: Multiplication factor for PLL1 VCO - bit_offset: 0 - bit_size: 9 - - name: DIVP3 - description: PLL DIVP division factor - bit_offset: 9 - bit_size: 7 - - name: DIVQ3 - description: PLL DIVQ division factor - bit_offset: 16 - bit_size: 7 - - name: DIVR3 - description: PLL DIVR division factor - bit_offset: 24 - bit_size: 7 -fieldset/PLL3FRACR: - description: RCC PLL3 Fractional Divider Register - fields: - - name: FRACN3 - description: Fractional part of the multiplication factor for PLL3 VCO - bit_offset: 3 - bit_size: 13 -fieldset/PLLCFGR: - description: RCC PLLs Configuration Register - fields: - - name: PLLFRACEN - description: PLL1 fractional latch enable - bit_offset: 0 - bit_size: 1 - array: - len: 3 - stride: 4 - enum: PLL1FRACEN - - name: PLLVCOSEL - description: PLL1 VCO selection - bit_offset: 1 - bit_size: 1 - array: - len: 3 - stride: 4 - enum: PLL1VCOSEL - - name: PLLRGE - description: PLL1 input frequency range - bit_offset: 2 - bit_size: 2 - array: - len: 3 - stride: 4 - enum: PLL1RGE - - name: DIVPEN - description: PLL1 DIVP divider output enable - bit_offset: 16 - bit_size: 1 - array: - len: 3 - stride: 3 - enum: DIVP1EN - - name: DIVQEN - description: PLL1 DIVQ divider output enable - bit_offset: 17 - bit_size: 1 - array: - len: 3 - stride: 3 - enum: DIVP1EN - - name: DIVREN - description: PLL1 DIVR divider output enable - bit_offset: 18 - bit_size: 1 - array: - len: 3 - stride: 3 - enum: DIVP1EN -fieldset/PLLCKSELR: - description: RCC PLLs Clock Source Selection Register - fields: - - name: PLLSRC - description: DIVMx and PLLs clock source selection - bit_offset: 0 - bit_size: 2 - enum: PLLSRC - - name: DIVM - description: Prescaler for PLL1 - bit_offset: 4 - bit_size: 6 - array: - len: 3 - stride: 8 -fieldset/RSR: - description: RCC Reset Status Register - fields: - - name: RMVF - description: Remove reset flag - bit_offset: 16 - bit_size: 1 - enum: RSR_RMVF - - name: CPURSTF - description: CPU reset flag - bit_offset: 17 - bit_size: 1 - enum_read: RSR_CPURSTFR - - name: D1RSTF - description: D1 domain power switch reset flag - bit_offset: 19 - bit_size: 1 - enum_read: RSR_CPURSTFR - - name: D2RSTF - description: D2 domain power switch reset flag - bit_offset: 20 - bit_size: 1 - enum_read: RSR_CPURSTFR - - name: BORRSTF - description: BOR reset flag - bit_offset: 21 - bit_size: 1 - enum_read: RSR_CPURSTFR - - name: PINRSTF - description: Pin reset flag (NRST) - bit_offset: 22 - bit_size: 1 - enum_read: RSR_CPURSTFR - - name: PORRSTF - description: POR/PDR reset flag - bit_offset: 23 - bit_size: 1 - enum_read: RSR_CPURSTFR - - name: SFTRSTF - description: System reset from CPU reset flag - bit_offset: 24 - bit_size: 1 - enum_read: RSR_CPURSTFR - - name: IWDG1RSTF - description: Independent Watchdog reset flag - bit_offset: 26 - bit_size: 1 - enum_read: RSR_CPURSTFR - - name: WWDG1RSTF - description: Window Watchdog reset flag - bit_offset: 28 - bit_size: 1 - enum_read: RSR_CPURSTFR - - name: LPWRRSTF - description: Reset due to illegal D1 DStandby or CPU CStop flag - bit_offset: 30 - bit_size: 1 - enum_read: RSR_CPURSTFR + - byte_offset: 0 + description: clock control register + fieldset: CR + name: CR + - byte_offset: 4 + description: RCC HSI configuration register + fieldset: HSICFGR + name: HSICFGR + - byte_offset: 4 + description: RCC Internal Clock Source Calibration Register + fieldset: ICSCR + name: ICSCR + - access: Read + byte_offset: 8 + description: RCC Clock Recovery RC Register + fieldset: CRRCR + name: CRRCR + - byte_offset: 12 + description: RCC CSI configuration register + fieldset: CSICFGR + name: CSICFGR + - byte_offset: 16 + description: RCC Clock Configuration Register + fieldset: CFGR + name: CFGR + - byte_offset: 24 + description: RCC Domain 1 Clock Configuration Register + fieldset: D1CFGR + name: D1CFGR + - byte_offset: 28 + description: RCC Domain 2 Clock Configuration Register + fieldset: D2CFGR + name: D2CFGR + - byte_offset: 32 + description: RCC Domain 3 Clock Configuration Register + fieldset: D3CFGR + name: D3CFGR + - byte_offset: 40 + description: RCC PLLs Clock Source Selection Register + fieldset: PLLCKSELR + name: PLLCKSELR + - byte_offset: 44 + description: RCC PLLs Configuration Register + fieldset: PLLCFGR + name: PLLCFGR + - array: + len: 3 + stride: 8 + byte_offset: 48 + description: RCC PLL1 Dividers Configuration Register + fieldset: PLL1DIVR + name: PLLDIVR + - array: + len: 3 + stride: 8 + byte_offset: 52 + description: RCC PLL1 Fractional Divider Register + fieldset: PLL1FRACR + name: PLLFRACR + - byte_offset: 76 + description: RCC Domain 1 Kernel Clock Configuration Register + fieldset: D1CCIPR + name: D1CCIPR + - byte_offset: 80 + description: RCC Domain 2 Kernel Clock Configuration Register + fieldset: D2CCIP1R + name: D2CCIP1R + - byte_offset: 84 + description: RCC Domain 2 Kernel Clock Configuration Register + fieldset: D2CCIP2R + name: D2CCIP2R + - byte_offset: 88 + description: RCC Domain 3 Kernel Clock Configuration Register + fieldset: D3CCIPR + name: D3CCIPR + - byte_offset: 96 + description: RCC Clock Source Interrupt Enable Register + fieldset: CIER + name: CIER + - access: Read + byte_offset: 100 + description: RCC Clock Source Interrupt Flag Register + fieldset: CIFR + name: CIFR + - byte_offset: 104 + description: RCC Clock Source Interrupt Clear Register + fieldset: CICR + name: CICR + - byte_offset: 112 + description: RCC Backup Domain Control Register + fieldset: BDCR + name: BDCR + - byte_offset: 116 + description: RCC Clock Control and Status Register + fieldset: CSR + name: CSR + - byte_offset: 124 + description: RCC AHB3 Reset Register + fieldset: AHB3RSTR + name: AHB3RSTR + - byte_offset: 128 + description: RCC AHB1 Peripheral Reset Register + fieldset: AHB1RSTR + name: AHB1RSTR + - byte_offset: 132 + description: RCC AHB2 Peripheral Reset Register + fieldset: AHB2RSTR + name: AHB2RSTR + - byte_offset: 136 + description: RCC AHB4 Peripheral Reset Register + fieldset: AHB4RSTR + name: AHB4RSTR + - byte_offset: 140 + description: RCC APB3 Peripheral Reset Register + fieldset: APB3RSTR + name: APB3RSTR + - byte_offset: 144 + description: RCC APB1 Peripheral Reset Register + fieldset: APB1LRSTR + name: APB1LRSTR + - byte_offset: 148 + description: RCC APB1 Peripheral Reset Register + fieldset: APB1HRSTR + name: APB1HRSTR + - byte_offset: 152 + description: RCC APB2 Peripheral Reset Register + fieldset: APB2RSTR + name: APB2RSTR + - byte_offset: 156 + description: RCC APB4 Peripheral Reset Register + fieldset: APB4RSTR + name: APB4RSTR + - byte_offset: 160 + description: RCC Global Control Register + fieldset: GCR + name: GCR + - byte_offset: 168 + description: RCC D3 Autonomous mode Register + fieldset: D3AMR + name: D3AMR + - byte_offset: 208 + description: RCC Reset Status Register + fieldset: RSR + name: RSR + - byte_offset: 212 + description: RCC AHB3 Clock Register + fieldset: AHB3ENR + name: AHB3ENR + - byte_offset: 216 + description: RCC AHB1 Clock Register + fieldset: AHB1ENR + name: AHB1ENR + - byte_offset: 220 + description: RCC AHB2 Clock Register + fieldset: AHB2ENR + name: AHB2ENR + - byte_offset: 224 + description: RCC AHB4 Clock Register + fieldset: AHB4ENR + name: AHB4ENR + - byte_offset: 228 + description: RCC APB3 Clock Register + fieldset: APB3ENR + name: APB3ENR + - byte_offset: 232 + description: RCC APB1 Clock Register + fieldset: APB1LENR + name: APB1LENR + - byte_offset: 236 + description: RCC APB1 Clock Register + fieldset: APB1HENR + name: APB1HENR + - byte_offset: 240 + description: RCC APB2 Clock Register + fieldset: APB2ENR + name: APB2ENR + - byte_offset: 244 + description: RCC APB4 Clock Register + fieldset: APB4ENR + name: APB4ENR + - byte_offset: 252 + description: RCC AHB3 Sleep Clock Register + fieldset: AHB3LPENR + name: AHB3LPENR + - byte_offset: 256 + description: RCC AHB1 Sleep Clock Register + fieldset: AHB1LPENR + name: AHB1LPENR + - byte_offset: 260 + description: RCC AHB2 Sleep Clock Register + fieldset: AHB2LPENR + name: AHB2LPENR + - byte_offset: 264 + description: RCC AHB4 Sleep Clock Register + fieldset: AHB4LPENR + name: AHB4LPENR + - byte_offset: 268 + description: RCC APB3 Sleep Clock Register + fieldset: APB3LPENR + name: APB3LPENR + - byte_offset: 272 + description: RCC APB1 Low Sleep Clock Register + fieldset: APB1LLPENR + name: APB1LLPENR + - byte_offset: 276 + description: RCC APB1 High Sleep Clock Register + fieldset: APB1HLPENR + name: APB1HLPENR + - byte_offset: 280 + description: RCC APB2 Sleep Clock Register + fieldset: APB2LPENR + name: APB2LPENR + - byte_offset: 284 + description: RCC APB4 Sleep Clock Register + fieldset: APB4LPENR + name: APB4LPENR + - byte_offset: 304 + description: RCC Reset Status Register + fieldset: C1_RSR + name: C1_RSR + - byte_offset: 308 + description: RCC AHB3 Clock Register + fieldset: C1_AHB3ENR + name: C1_AHB3ENR + - byte_offset: 312 + description: RCC AHB1 Clock Register + fieldset: C1_AHB1ENR + name: C1_AHB1ENR + - byte_offset: 316 + description: RCC AHB2 Clock Register + fieldset: C1_AHB2ENR + name: C1_AHB2ENR + - byte_offset: 320 + description: RCC AHB4 Clock Register + fieldset: C1_AHB4ENR + name: C1_AHB4ENR + - byte_offset: 324 + description: RCC APB3 Clock Register + fieldset: C1_APB3ENR + name: C1_APB3ENR + - byte_offset: 328 + description: RCC APB1 Clock Register + fieldset: C1_APB1LENR + name: C1_APB1LENR + - byte_offset: 332 + description: RCC APB1 Clock Register + fieldset: C1_APB1HENR + name: C1_APB1HENR + - byte_offset: 336 + description: RCC APB2 Clock Register + fieldset: C1_APB2ENR + name: C1_APB2ENR + - byte_offset: 340 + description: RCC APB4 Clock Register + fieldset: C1_APB4ENR + name: C1_APB4ENR + - byte_offset: 348 + description: RCC AHB3 Sleep Clock Register + fieldset: C1_AHB3LPENR + name: C1_AHB3LPENR + - byte_offset: 352 + description: RCC AHB1 Sleep Clock Register + fieldset: C1_AHB1LPENR + name: C1_AHB1LPENR + - byte_offset: 356 + description: RCC AHB2 Sleep Clock Register + fieldset: C1_AHB2LPENR + name: C1_AHB2LPENR + - byte_offset: 360 + description: RCC AHB4 Sleep Clock Register + fieldset: C1_AHB4LPENR + name: C1_AHB4LPENR + - byte_offset: 364 + description: RCC APB3 Sleep Clock Register + fieldset: C1_APB3LPENR + name: C1_APB3LPENR + - byte_offset: 368 + description: RCC APB1 Low Sleep Clock Register + fieldset: C1_APB1LLPENR + name: C1_APB1LLPENR + - byte_offset: 372 + description: RCC APB1 High Sleep Clock Register + fieldset: C1_APB1HLPENR + name: C1_APB1HLPENR + - byte_offset: 376 + description: RCC APB2 Sleep Clock Register + fieldset: C1_APB2LPENR + name: C1_APB2LPENR + - byte_offset: 380 + description: RCC APB4 Sleep Clock Register + fieldset: C1_APB4LPENR + name: C1_APB4LPENR enum/ADCSEL: bit_size: 2 variants: - - name: PLL2_P - description: pll2_p selected as peripheral clock - value: 0 - - name: PLL3_R - description: pll3_r selected as peripheral clock - value: 1 - - name: PER - description: PER selected as peripheral clock - value: 2 -enum/AHB1ENR_DMA1EN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled - value: 0 - - name: Enabled - description: The selected clock is enabled - value: 1 -enum/AHB1LPENR_DMA1LPEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled during csleep mode - value: 0 - - name: Enabled - description: The selected clock is enabled during csleep mode - value: 1 -enum/AHB2ENR_DCMIEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled - value: 0 - - name: Enabled - description: The selected clock is enabled - value: 1 -enum/AHB2LPENR_DCMILPEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled during csleep mode - value: 0 - - name: Enabled - description: The selected clock is enabled during csleep mode - value: 1 -enum/AHB3ENR_MDMAEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled - value: 0 - - name: Enabled - description: The selected clock is enabled - value: 1 -enum/AHB3LPENR_MDMALPEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled during csleep mode - value: 0 - - name: Enabled - description: The selected clock is enabled during csleep mode - value: 1 -enum/AHB4ENR_GPIOAEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled - value: 0 - - name: Enabled - description: The selected clock is enabled - value: 1 -enum/AHB4LPENR_GPIOALPEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled during csleep mode - value: 0 - - name: Enabled - description: The selected clock is enabled during csleep mode - value: 1 -enum/APB1HENR_CRSEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled - value: 0 - - name: Enabled - description: The selected clock is enabled - value: 1 -enum/APB1HLPENR_CRSLPEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled during csleep mode - value: 0 - - name: Enabled - description: The selected clock is enabled during csleep mode - value: 1 -enum/APB1LENR_TIM2EN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled - value: 0 - - name: Enabled - description: The selected clock is enabled - value: 1 -enum/APB1LLPENR_TIM2LPEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled during csleep mode - value: 0 - - name: Enabled - description: The selected clock is enabled during csleep mode - value: 1 -enum/APB2ENR_TIM1EN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled - value: 0 - - name: Enabled - description: The selected clock is enabled - value: 1 -enum/APB2LPENR_TIM1LPEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled during csleep mode - value: 0 - - name: Enabled - description: The selected clock is enabled during csleep mode - value: 1 -enum/APB3ENR_LTDCEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled - value: 0 - - name: Enabled - description: The selected clock is enabled - value: 1 -enum/APB3LPENR_LTDCLPEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled during csleep mode - value: 0 - - name: Enabled - description: The selected clock is enabled during csleep mode - value: 1 -enum/APB4ENR_SYSCFGEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled - value: 0 - - name: Enabled - description: The selected clock is enabled - value: 1 -enum/APB4LPENR_SYSCFGLPEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled during csleep mode - value: 0 - - name: Enabled - description: The selected clock is enabled during csleep mode - value: 1 -enum/BDMAAMEN: - bit_size: 1 - variants: - - name: Disabled - description: Clock disabled in autonomous mode - value: 0 - - name: Enabled - description: Clock enabled in autonomous mode - value: 1 -enum/BDRST: - bit_size: 1 - variants: - - name: Reset - description: Resets the entire VSW domain - value: 1 -enum/C1_AHB1ENR_DMA1EN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled - value: 0 - - name: Enabled - description: The selected clock is enabled - value: 1 -enum/C1_AHB1LPENR_DMA1LPEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled during csleep mode - value: 0 - - name: Enabled - description: The selected clock is enabled during csleep mode - value: 1 -enum/C1_AHB2ENR_DCMIEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled - value: 0 - - name: Enabled - description: The selected clock is enabled - value: 1 -enum/C1_AHB2LPENR_DCMILPEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled during csleep mode - value: 0 - - name: Enabled - description: The selected clock is enabled during csleep mode - value: 1 -enum/C1_AHB3ENR_MDMAEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled - value: 0 - - name: Enabled - description: The selected clock is enabled - value: 1 -enum/C1_AHB3LPENR_MDMALPEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled during csleep mode - value: 0 - - name: Enabled - description: The selected clock is enabled during csleep mode - value: 1 -enum/C1_AHB4ENR_GPIOAEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled - value: 0 - - name: Enabled - description: The selected clock is enabled - value: 1 -enum/C1_AHB4LPENR_GPIOALPEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled during csleep mode - value: 0 - - name: Enabled - description: The selected clock is enabled during csleep mode - value: 1 -enum/C1_APB1HENR_CRSEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled - value: 0 - - name: Enabled - description: The selected clock is enabled - value: 1 -enum/C1_APB1HLPENR_CRSLPEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled during csleep mode - value: 0 - - name: Enabled - description: The selected clock is enabled during csleep mode - value: 1 -enum/C1_APB1LENR_TIM2EN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled - value: 0 - - name: Enabled - description: The selected clock is enabled - value: 1 -enum/C1_APB1LLPENR_TIM2LPEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled during csleep mode - value: 0 - - name: Enabled - description: The selected clock is enabled during csleep mode - value: 1 -enum/C1_APB2ENR_TIM1EN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled - value: 0 - - name: Enabled - description: The selected clock is enabled - value: 1 -enum/C1_APB2LPENR_TIM1LPEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled during csleep mode - value: 0 - - name: Enabled - description: The selected clock is enabled during csleep mode - value: 1 -enum/C1_APB3ENR_LTDCEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled - value: 0 - - name: Enabled - description: The selected clock is enabled - value: 1 -enum/C1_APB3LPENR_LTDCLPEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled during csleep mode - value: 0 - - name: Enabled - description: The selected clock is enabled during csleep mode - value: 1 -enum/C1_APB4ENR_SYSCFGEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled - value: 0 - - name: Enabled - description: The selected clock is enabled - value: 1 -enum/C1_APB4LPENR_SYSCFGLPEN: - bit_size: 1 - variants: - - name: Disabled - description: The selected clock is disabled during csleep mode - value: 0 - - name: Enabled - description: The selected clock is enabled during csleep mode - value: 1 -enum/C1_RSR_CPURSTFR: - bit_size: 1 - variants: - - name: NoResetOccoured - description: No reset occoured for block - value: 0 - - name: ResetOccourred - description: Reset occoured for block - value: 1 -enum/C1_RSR_RMVF: - bit_size: 1 - variants: - - name: NotActive - description: Not clearing the the reset flags - value: 0 - - name: Clear - description: Clear the reset flags - value: 1 -enum/CAMITFRST: - bit_size: 1 - variants: - - name: Reset - description: Reset the selected module - value: 1 + - description: pll2_p selected as peripheral clock + name: PLL2_P + value: 0 + - description: pll3_r selected as peripheral clock + name: PLL3_R + value: 1 + - description: PER selected as peripheral clock + name: PER + value: 2 enum/CECSEL: bit_size: 2 variants: - - name: LSE - description: LSE selected as peripheral clock - value: 0 - - name: LSI - description: LSI selected as peripheral clock - value: 1 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 2 + - description: LSE selected as peripheral clock + name: LSE + value: 0 + - description: LSI selected as peripheral clock + name: LSI + value: 1 + - description: csi_ker selected as peripheral clock + name: CSI_KER + value: 2 enum/CKPERSEL: bit_size: 2 variants: - - name: HSI - description: HSI selected as peripheral clock - value: 0 - - name: CSI - description: CSI selected as peripheral clock - value: 1 - - name: HSE - description: HSE selected as peripheral clock - value: 2 -enum/CRSRST: + - description: HSI selected as peripheral clock + name: HSI + value: 0 + - description: CSI selected as peripheral clock + name: CSI + value: 1 + - description: HSE selected as peripheral clock + name: HSE + value: 2 +enum/C_RSR_CPURSTFR: bit_size: 1 variants: - - name: Reset - description: Reset the selected module - value: 1 -enum/D1PPRE: - bit_size: 3 - variants: - - name: Div1 - description: rcc_hclk not divided - value: 0 - - name: Div2 - description: rcc_hclk divided by 2 - value: 4 - - name: Div4 - description: rcc_hclk divided by 4 - value: 5 - - name: Div8 - description: rcc_hclk divided by 8 - value: 6 - - name: Div16 - description: rcc_hclk divided by 16 - value: 7 -enum/D2PPRE1: - bit_size: 3 - variants: - - name: Div1 - description: rcc_hclk not divided - value: 0 - - name: Div2 - description: rcc_hclk divided by 2 - value: 4 - - name: Div4 - description: rcc_hclk divided by 4 - value: 5 - - name: Div8 - description: rcc_hclk divided by 8 - value: 6 - - name: Div16 - description: rcc_hclk divided by 16 - value: 7 -enum/D3PPRE: - bit_size: 3 - variants: - - name: Div1 - description: rcc_hclk not divided - value: 0 - - name: Div2 - description: rcc_hclk divided by 2 - value: 4 - - name: Div4 - description: rcc_hclk divided by 4 - value: 5 - - name: Div8 - description: rcc_hclk divided by 8 - value: 6 - - name: Div16 - description: rcc_hclk divided by 16 - value: 7 -enum/DFSDM1SEL: + - description: No reset occoured for block + name: NoResetOccoured + value: 0 + - description: Reset occoured for block + name: ResetOccourred + value: 1 +enum/C_RSR_RMVF: bit_size: 1 variants: - - name: RCC_PCLK2 - description: rcc_pclk2 selected as peripheral clock - value: 0 - - name: SYS - description: System clock selected as peripheral clock - value: 1 -enum/DIVP1: + - description: Not clearing the the reset flags + name: NotActive + value: 0 + - description: Clear the reset flags + name: Clear + value: 1 +enum/DFSDMSEL: + bit_size: 1 + variants: + - description: rcc_pclk2 selected as peripheral clock + name: RCC_PCLK2 + value: 0 + - description: System clock selected as peripheral clock + name: SYS + value: 1 +enum/DIVP: bit_size: 7 variants: - - name: Div1 - description: pll_p_ck = vco_ck - value: 0 - - name: Div2 - description: pll_p_ck = vco_ck / 2 - value: 1 - - name: Div4 - description: pll_p_ck = vco_ck / 4 - value: 3 - - name: Div6 - description: pll_p_ck = vco_ck / 6 - value: 5 - - name: Div8 - description: pll_p_ck = vco_ck / 8 - value: 7 - - name: Div10 - description: pll_p_ck = vco_ck / 10 - value: 9 - - name: Div12 - description: pll_p_ck = vco_ck / 12 - value: 11 - - name: Div14 - description: pll_p_ck = vco_ck / 14 - value: 13 - - name: Div16 - description: pll_p_ck = vco_ck / 16 - value: 15 - - name: Div18 - description: pll_p_ck = vco_ck / 18 - value: 17 - - name: Div20 - description: pll_p_ck = vco_ck / 20 - value: 19 - - name: Div22 - description: pll_p_ck = vco_ck / 22 - value: 21 - - name: Div24 - description: pll_p_ck = vco_ck / 24 - value: 23 - - name: Div26 - description: pll_p_ck = vco_ck / 26 - value: 25 - - name: Div28 - description: pll_p_ck = vco_ck / 28 - value: 27 - - name: Div30 - description: pll_p_ck = vco_ck / 30 - value: 29 - - name: Div32 - description: pll_p_ck = vco_ck / 32 - value: 31 - - name: Div34 - description: pll_p_ck = vco_ck / 34 - value: 33 - - name: Div36 - description: pll_p_ck = vco_ck / 36 - value: 35 - - name: Div38 - description: pll_p_ck = vco_ck / 38 - value: 37 - - name: Div40 - description: pll_p_ck = vco_ck / 40 - value: 39 - - name: Div42 - description: pll_p_ck = vco_ck / 42 - value: 41 - - name: Div44 - description: pll_p_ck = vco_ck / 44 - value: 43 - - name: Div46 - description: pll_p_ck = vco_ck / 46 - value: 45 - - name: Div48 - description: pll_p_ck = vco_ck / 48 - value: 47 - - name: Div50 - description: pll_p_ck = vco_ck / 50 - value: 49 - - name: Div52 - description: pll_p_ck = vco_ck / 52 - value: 51 - - name: Div54 - description: pll_p_ck = vco_ck / 54 - value: 53 - - name: Div56 - description: pll_p_ck = vco_ck / 56 - value: 55 - - name: Div58 - description: pll_p_ck = vco_ck / 58 - value: 57 - - name: Div60 - description: pll_p_ck = vco_ck / 60 - value: 59 - - name: Div62 - description: pll_p_ck = vco_ck / 62 - value: 61 - - name: Div64 - description: pll_p_ck = vco_ck / 64 - value: 63 - - name: Div66 - description: pll_p_ck = vco_ck / 66 - value: 65 - - name: Div68 - description: pll_p_ck = vco_ck / 68 - value: 67 - - name: Div70 - description: pll_p_ck = vco_ck / 70 - value: 69 - - name: Div72 - description: pll_p_ck = vco_ck / 72 - value: 71 - - name: Div74 - description: pll_p_ck = vco_ck / 74 - value: 73 - - name: Div76 - description: pll_p_ck = vco_ck / 76 - value: 75 - - name: Div78 - description: pll_p_ck = vco_ck / 78 - value: 77 - - name: Div80 - description: pll_p_ck = vco_ck / 80 - value: 79 - - name: Div82 - description: pll_p_ck = vco_ck / 82 - value: 81 - - name: Div84 - description: pll_p_ck = vco_ck / 84 - value: 83 - - name: Div86 - description: pll_p_ck = vco_ck / 86 - value: 85 - - name: Div88 - description: pll_p_ck = vco_ck / 88 - value: 87 - - name: Div90 - description: pll_p_ck = vco_ck / 90 - value: 89 - - name: Div92 - description: pll_p_ck = vco_ck / 92 - value: 91 - - name: Div94 - description: pll_p_ck = vco_ck / 94 - value: 93 - - name: Div96 - description: pll_p_ck = vco_ck / 96 - value: 95 - - name: Div98 - description: pll_p_ck = vco_ck / 98 - value: 97 - - name: Div100 - description: pll_p_ck = vco_ck / 100 - value: 99 - - name: Div102 - description: pll_p_ck = vco_ck / 102 - value: 101 - - name: Div104 - description: pll_p_ck = vco_ck / 104 - value: 103 - - name: Div106 - description: pll_p_ck = vco_ck / 106 - value: 105 - - name: Div108 - description: pll_p_ck = vco_ck / 108 - value: 107 - - name: Div110 - description: pll_p_ck = vco_ck / 110 - value: 109 - - name: Div112 - description: pll_p_ck = vco_ck / 112 - value: 111 - - name: Div114 - description: pll_p_ck = vco_ck / 114 - value: 113 - - name: Div116 - description: pll_p_ck = vco_ck / 116 - value: 115 - - name: Div118 - description: pll_p_ck = vco_ck / 118 - value: 117 - - name: Div120 - description: pll_p_ck = vco_ck / 120 - value: 119 - - name: Div122 - description: pll_p_ck = vco_ck / 122 - value: 121 - - name: Div124 - description: pll_p_ck = vco_ck / 124 - value: 123 - - name: Div126 - description: pll_p_ck = vco_ck / 126 - value: 125 - - name: Div128 - description: pll_p_ck = vco_ck / 128 - value: 127 -enum/DIVP1EN: - bit_size: 1 + - description: pll_p_ck = vco_ck + name: Div1 + value: 0 + - description: pll_p_ck = vco_ck / 2 + name: Div2 + value: 1 + - description: pll_p_ck = vco_ck / 4 + name: Div4 + value: 3 + - description: pll_p_ck = vco_ck / 6 + name: Div6 + value: 5 + - description: pll_p_ck = vco_ck / 8 + name: Div8 + value: 7 + - description: pll_p_ck = vco_ck / 10 + name: Div10 + value: 9 + - description: pll_p_ck = vco_ck / 12 + name: Div12 + value: 11 + - description: pll_p_ck = vco_ck / 14 + name: Div14 + value: 13 + - description: pll_p_ck = vco_ck / 16 + name: Div16 + value: 15 + - description: pll_p_ck = vco_ck / 18 + name: Div18 + value: 17 + - description: pll_p_ck = vco_ck / 20 + name: Div20 + value: 19 + - description: pll_p_ck = vco_ck / 22 + name: Div22 + value: 21 + - description: pll_p_ck = vco_ck / 24 + name: Div24 + value: 23 + - description: pll_p_ck = vco_ck / 26 + name: Div26 + value: 25 + - description: pll_p_ck = vco_ck / 28 + name: Div28 + value: 27 + - description: pll_p_ck = vco_ck / 30 + name: Div30 + value: 29 + - description: pll_p_ck = vco_ck / 32 + name: Div32 + value: 31 + - description: pll_p_ck = vco_ck / 34 + name: Div34 + value: 33 + - description: pll_p_ck = vco_ck / 36 + name: Div36 + value: 35 + - description: pll_p_ck = vco_ck / 38 + name: Div38 + value: 37 + - description: pll_p_ck = vco_ck / 40 + name: Div40 + value: 39 + - description: pll_p_ck = vco_ck / 42 + name: Div42 + value: 41 + - description: pll_p_ck = vco_ck / 44 + name: Div44 + value: 43 + - description: pll_p_ck = vco_ck / 46 + name: Div46 + value: 45 + - description: pll_p_ck = vco_ck / 48 + name: Div48 + value: 47 + - description: pll_p_ck = vco_ck / 50 + name: Div50 + value: 49 + - description: pll_p_ck = vco_ck / 52 + name: Div52 + value: 51 + - description: pll_p_ck = vco_ck / 54 + name: Div54 + value: 53 + - description: pll_p_ck = vco_ck / 56 + name: Div56 + value: 55 + - description: pll_p_ck = vco_ck / 58 + name: Div58 + value: 57 + - description: pll_p_ck = vco_ck / 60 + name: Div60 + value: 59 + - description: pll_p_ck = vco_ck / 62 + name: Div62 + value: 61 + - description: pll_p_ck = vco_ck / 64 + name: Div64 + value: 63 + - description: pll_p_ck = vco_ck / 66 + name: Div66 + value: 65 + - description: pll_p_ck = vco_ck / 68 + name: Div68 + value: 67 + - description: pll_p_ck = vco_ck / 70 + name: Div70 + value: 69 + - description: pll_p_ck = vco_ck / 72 + name: Div72 + value: 71 + - description: pll_p_ck = vco_ck / 74 + name: Div74 + value: 73 + - description: pll_p_ck = vco_ck / 76 + name: Div76 + value: 75 + - description: pll_p_ck = vco_ck / 78 + name: Div78 + value: 77 + - description: pll_p_ck = vco_ck / 80 + name: Div80 + value: 79 + - description: pll_p_ck = vco_ck / 82 + name: Div82 + value: 81 + - description: pll_p_ck = vco_ck / 84 + name: Div84 + value: 83 + - description: pll_p_ck = vco_ck / 86 + name: Div86 + value: 85 + - description: pll_p_ck = vco_ck / 88 + name: Div88 + value: 87 + - description: pll_p_ck = vco_ck / 90 + name: Div90 + value: 89 + - description: pll_p_ck = vco_ck / 92 + name: Div92 + value: 91 + - description: pll_p_ck = vco_ck / 94 + name: Div94 + value: 93 + - description: pll_p_ck = vco_ck / 96 + name: Div96 + value: 95 + - description: pll_p_ck = vco_ck / 98 + name: Div98 + value: 97 + - description: pll_p_ck = vco_ck / 100 + name: Div100 + value: 99 + - description: pll_p_ck = vco_ck / 102 + name: Div102 + value: 101 + - description: pll_p_ck = vco_ck / 104 + name: Div104 + value: 103 + - description: pll_p_ck = vco_ck / 106 + name: Div106 + value: 105 + - description: pll_p_ck = vco_ck / 108 + name: Div108 + value: 107 + - description: pll_p_ck = vco_ck / 110 + name: Div110 + value: 109 + - description: pll_p_ck = vco_ck / 112 + name: Div112 + value: 111 + - description: pll_p_ck = vco_ck / 114 + name: Div114 + value: 113 + - description: pll_p_ck = vco_ck / 116 + name: Div116 + value: 115 + - description: pll_p_ck = vco_ck / 118 + name: Div118 + value: 117 + - description: pll_p_ck = vco_ck / 120 + name: Div120 + value: 119 + - description: pll_p_ck = vco_ck / 122 + name: Div122 + value: 121 + - description: pll_p_ck = vco_ck / 124 + name: Div124 + value: 123 + - description: pll_p_ck = vco_ck / 126 + name: Div126 + value: 125 + - description: pll_p_ck = vco_ck / 128 + name: Div128 + value: 127 +enum/DPPRE: + bit_size: 3 variants: - - name: Disabled - description: Clock ouput is disabled - value: 0 - - name: Enabled - description: Clock output is enabled - value: 1 -enum/DMA1RST: - bit_size: 1 - variants: - - name: Reset - description: Reset the selected module - value: 1 + - description: rcc_hclk not divided + name: Div1 + value: 0 + - description: rcc_hclk divided by 2 + name: Div2 + value: 4 + - description: rcc_hclk divided by 4 + name: Div4 + value: 5 + - description: rcc_hclk divided by 8 + name: Div8 + value: 6 + - description: rcc_hclk divided by 16 + name: Div16 + value: 7 enum/FDCANSEL: bit_size: 2 variants: - - name: HSE - description: HSE selected as peripheral clock - value: 0 - - name: PLL1_Q - description: pll1_q selected as peripheral clock - value: 1 - - name: PLL2_Q - description: pll2_q selected as peripheral clock - value: 2 + - description: HSE selected as peripheral clock + name: HSE + value: 0 + - description: pll1_q selected as peripheral clock + name: PLL1_Q + value: 1 + - description: pll2_q selected as peripheral clock + name: PLL2_Q + value: 2 enum/FMCSEL: bit_size: 2 variants: - - name: RCC_HCLK3 - description: rcc_hclk3 selected as peripheral clock - value: 0 - - name: PLL1_Q - description: pll1_q selected as peripheral clock - value: 1 - - name: PLL2_R - description: pll2_r selected as peripheral clock - value: 2 - - name: PER - description: PER selected as peripheral clock - value: 3 -enum/GPIOARST: - bit_size: 1 - variants: - - name: Reset - description: Reset the selected module - value: 1 + - description: rcc_hclk3 selected as peripheral clock + name: RCC_HCLK3 + value: 0 + - description: pll1_q selected as peripheral clock + name: PLL1_Q + value: 1 + - description: pll2_r selected as peripheral clock + name: PLL2_R + value: 2 + - description: PER selected as peripheral clock + name: PER + value: 3 enum/HPRE: bit_size: 4 variants: - - name: Div1 - description: sys_ck not divided - value: 0 - - name: Div2 - description: sys_ck divided by 2 - value: 8 - - name: Div4 - description: sys_ck divided by 4 - value: 9 - - name: Div8 - description: sys_ck divided by 8 - value: 10 - - name: Div16 - description: sys_ck divided by 16 - value: 11 - - name: Div64 - description: sys_ck divided by 64 - value: 12 - - name: Div128 - description: sys_ck divided by 128 - value: 13 - - name: Div256 - description: sys_ck divided by 256 - value: 14 - - name: Div512 - description: sys_ck divided by 512 - value: 15 + - description: sys_ck not divided + name: Div1 + value: 0 + - description: sys_ck divided by 2 + name: Div2 + value: 8 + - description: sys_ck divided by 4 + name: Div4 + value: 9 + - description: sys_ck divided by 8 + name: Div8 + value: 10 + - description: sys_ck divided by 16 + name: Div16 + value: 11 + - description: sys_ck divided by 64 + name: Div64 + value: 12 + - description: sys_ck divided by 128 + name: Div128 + value: 13 + - description: sys_ck divided by 256 + name: Div256 + value: 14 + - description: sys_ck divided by 512 + name: Div512 + value: 15 enum/HRTIMSEL: bit_size: 1 variants: - - name: TIMY_KER - description: The HRTIM prescaler clock source is the same as other timers (rcc_timy_ker_ck) - value: 0 - - name: C_CK - description: The HRTIM prescaler clock source is the CPU clock (c_ck) - value: 1 + - description: The HRTIM prescaler clock source is the same as other timers (rcc_timy_ker_ck) + name: TIMY_KER + value: 0 + - description: The HRTIM prescaler clock source is the CPU clock (c_ck) + name: C_CK + value: 1 enum/HSEBYP: bit_size: 1 variants: - - name: NotBypassed - description: HSE crystal oscillator not bypassed - value: 0 - - name: Bypassed - description: HSE crystal oscillator bypassed with external clock - value: 1 + - description: HSE crystal oscillator not bypassed + name: NotBypassed + value: 0 + - description: HSE crystal oscillator bypassed with external clock + name: Bypassed + value: 1 enum/HSIDIV: bit_size: 2 variants: - - name: Div1 - description: No division - value: 0 - - name: Div2 - description: Division by 2 - value: 1 - - name: Div4 - description: Division by 4 - value: 2 - - name: Div8 - description: Division by 8 - value: 3 + - description: No division + name: Div1 + value: 0 + - description: Division by 2 + name: Div2 + value: 1 + - description: Division by 4 + name: Div4 + value: 2 + - description: Division by 8 + name: Div8 + value: 3 enum/HSIDIVFR: bit_size: 1 variants: - - name: NotPropagated - description: New HSIDIV ratio has not yet propagated to hsi_ck - value: 0 - - name: Propagated - description: HSIDIV ratio has propagated to hsi_ck - value: 1 -enum/HSION: - bit_size: 1 - variants: - - name: "Off" - description: Clock Off - value: 0 - - name: "On" - description: Clock On - value: 1 + - description: New HSIDIV ratio has not yet propagated to hsi_ck + name: NotPropagated + value: 0 + - description: HSIDIV ratio has propagated to hsi_ck + name: Propagated + value: 1 enum/HSIRDYR: bit_size: 1 variants: - - name: NotReady - description: Clock not ready - value: 0 - - name: Ready - description: Clock ready - value: 1 + - description: Clock not ready + name: NotReady + value: 0 + - description: Clock ready + name: Ready + value: 1 enum/I2C123SEL: bit_size: 2 variants: - - name: RCC_PCLK1 - description: rcc_pclk1 selected as peripheral clock - value: 0 - - name: PLL3_R - description: pll3_r selected as peripheral clock - value: 1 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 2 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 3 + - description: rcc_pclk1 selected as peripheral clock + name: RCC_PCLK1 + value: 0 + - description: pll3_r selected as peripheral clock + name: PLL3_R + value: 1 + - description: hsi_ker selected as peripheral clock + name: HSI_KER + value: 2 + - description: csi_ker selected as peripheral clock + name: CSI_KER + value: 3 enum/I2C4SEL: bit_size: 2 variants: - - name: RCC_PCLK4 - description: rcc_pclk4 selected as peripheral clock - value: 0 - - name: PLL3_R - description: pll3_r selected as peripheral clock - value: 1 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 2 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 3 + - description: rcc_pclk4 selected as peripheral clock + name: RCC_PCLK4 + value: 0 + - description: pll3_r selected as peripheral clock + name: PLL3_R + value: 1 + - description: hsi_ker selected as peripheral clock + name: HSI_KER + value: 2 + - description: csi_ker selected as peripheral clock + name: CSI_KER + value: 3 enum/LPTIM1SEL: bit_size: 3 variants: - - name: RCC_PCLK1 - description: rcc_pclk1 selected as peripheral clock - value: 0 - - name: PLL2_P - description: pll2_p selected as peripheral clock - value: 1 - - name: PLL3_R - description: pll3_r selected as peripheral clock - value: 2 - - name: LSE - description: LSE selected as peripheral clock - value: 3 - - name: LSI - description: LSI selected as peripheral clock - value: 4 - - name: PER - description: PER selected as peripheral clock - value: 5 + - description: rcc_pclk1 selected as peripheral clock + name: RCC_PCLK1 + value: 0 + - description: pll2_p selected as peripheral clock + name: PLL2_P + value: 1 + - description: pll3_r selected as peripheral clock + name: PLL3_R + value: 2 + - description: LSE selected as peripheral clock + name: LSE + value: 3 + - description: LSI selected as peripheral clock + name: LSI + value: 4 + - description: PER selected as peripheral clock + name: PER + value: 5 enum/LPTIM2SEL: bit_size: 3 variants: - - name: RCC_PCLK4 - description: rcc_pclk4 selected as peripheral clock - value: 0 - - name: PLL2_P - description: pll2_p selected as peripheral clock - value: 1 - - name: PLL3_R - description: pll3_r selected as peripheral clock - value: 2 - - name: LSE - description: LSE selected as peripheral clock - value: 3 - - name: LSI - description: LSI selected as peripheral clock - value: 4 - - name: PER - description: PER selected as peripheral clock - value: 5 -enum/LPUART1SEL: + - description: rcc_pclk4 selected as peripheral clock + name: RCC_PCLK4 + value: 0 + - description: pll2_p selected as peripheral clock + name: PLL2_P + value: 1 + - description: pll3_r selected as peripheral clock + name: PLL3_R + value: 2 + - description: LSE selected as peripheral clock + name: LSE + value: 3 + - description: LSI selected as peripheral clock + name: LSI + value: 4 + - description: PER selected as peripheral clock + name: PER + value: 5 +enum/LPUARTSEL: bit_size: 3 variants: - - name: RCC_PCLK_D3 - description: rcc_pclk_d3 selected as peripheral clock - value: 0 - - name: PLL2_Q - description: pll2_q selected as peripheral clock - value: 1 - - name: PLL3_Q - description: pll3_q selected as peripheral clock - value: 2 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 3 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 4 - - name: LSE - description: LSE selected as peripheral clock - value: 5 + - description: rcc_pclk_d3 selected as peripheral clock + name: RCC_PCLK_D3 + value: 0 + - description: pll2_q selected as peripheral clock + name: PLL2_Q + value: 1 + - description: pll3_q selected as peripheral clock + name: PLL3_Q + value: 2 + - description: hsi_ker selected as peripheral clock + name: HSI_KER + value: 3 + - description: csi_ker selected as peripheral clock + name: CSI_KER + value: 4 + - description: LSE selected as peripheral clock + name: LSE + value: 5 enum/LSEBYP: bit_size: 1 variants: - - name: NotBypassed - description: LSE crystal oscillator not bypassed - value: 0 - - name: Bypassed - description: LSE crystal oscillator bypassed with external clock - value: 1 + - description: LSE crystal oscillator not bypassed + name: NotBypassed + value: 0 + - description: LSE crystal oscillator bypassed with external clock + name: Bypassed + value: 1 enum/LSECSSDR: bit_size: 1 variants: - - name: NoFailure - description: No failure detected on 32 kHz oscillator - value: 0 - - name: Failure - description: Failure detected on 32 kHz oscillator - value: 1 -enum/LSECSSON: - bit_size: 1 - variants: - - name: SecurityOff - description: Clock security system on 32 kHz oscillator off - value: 0 - - name: SecurityOn - description: Clock security system on 32 kHz oscillator on - value: 1 + - description: No failure detected on 32 kHz oscillator + name: NoFailure + value: 0 + - description: Failure detected on 32 kHz oscillator + name: Failure + value: 1 enum/LSEDRV: bit_size: 2 variants: - - name: Lowest - description: Lowest LSE oscillator driving capability - value: 0 - - name: MediumLow - description: Medium low LSE oscillator driving capability - value: 1 - - name: MediumHigh - description: Medium high LSE oscillator driving capability - value: 2 - - name: Highest - description: Highest LSE oscillator driving capability - value: 3 -enum/LSEON: - bit_size: 1 - variants: - - name: "Off" - description: LSE oscillator Off - value: 0 - - name: "On" - description: LSE oscillator On - value: 1 + - description: Lowest LSE oscillator driving capability + name: Lowest + value: 0 + - description: Medium low LSE oscillator driving capability + name: MediumLow + value: 1 + - description: Medium high LSE oscillator driving capability + name: MediumHigh + value: 2 + - description: Highest LSE oscillator driving capability + name: Highest + value: 3 enum/LSERDYR: bit_size: 1 variants: - - name: NotReady - description: LSE oscillator not ready - value: 0 - - name: Ready - description: LSE oscillator ready - value: 1 -enum/LSION: - bit_size: 1 - variants: - - name: "Off" - description: LSI oscillator Off - value: 0 - - name: "On" - description: LSI oscillator On - value: 1 + - description: LSE oscillator not ready + name: NotReady + value: 0 + - description: LSE oscillator ready + name: Ready + value: 1 enum/LSIRDYC: bit_size: 1 variants: - - name: Clear - description: Clear interrupt flag - value: 1 + - description: Clear interrupt flag + name: Clear + value: 1 enum/LSIRDYIE: bit_size: 1 variants: - - name: Disabled - description: Interrupt disabled - value: 0 - - name: Enabled - description: Interrupt enabled - value: 1 + - description: Interrupt disabled + name: Disabled + value: 0 + - description: Interrupt enabled + name: Enabled + value: 1 enum/LSIRDYR: bit_size: 1 variants: - - name: NotReady - description: LSI oscillator not ready - value: 0 - - name: Ready - description: LSI oscillator ready - value: 1 -enum/LTDCRST: - bit_size: 1 - variants: - - name: Reset - description: Reset the selected module - value: 1 + - description: LSI oscillator not ready + name: NotReady + value: 0 + - description: LSI oscillator ready + name: Ready + value: 1 enum/MCO1: bit_size: 3 variants: - - name: HSI - description: HSI selected for micro-controller clock output - value: 0 - - name: LSE - description: LSE selected for micro-controller clock output - value: 1 - - name: HSE - description: HSE selected for micro-controller clock output - value: 2 - - name: PLL1_Q - description: pll1_q selected for micro-controller clock output - value: 3 - - name: HSI48 - description: HSI48 selected for micro-controller clock output - value: 4 + - description: HSI selected for micro-controller clock output + name: HSI + value: 0 + - description: LSE selected for micro-controller clock output + name: LSE + value: 1 + - description: HSE selected for micro-controller clock output + name: HSE + value: 2 + - description: pll1_q selected for micro-controller clock output + name: PLL1_Q + value: 3 + - description: HSI48 selected for micro-controller clock output + name: HSI48 + value: 4 enum/MCO2: bit_size: 3 variants: - - name: SYSCLK - description: System clock selected for micro-controller clock output - value: 0 - - name: PLL2_P - description: pll2_p selected for micro-controller clock output - value: 1 - - name: HSE - description: HSE selected for micro-controller clock output - value: 2 - - name: PLL1_P - description: pll1_p selected for micro-controller clock output - value: 3 - - name: CSI - description: CSI selected for micro-controller clock output - value: 4 - - name: LSI - description: LSI selected for micro-controller clock output - value: 5 -enum/MDMARST: - bit_size: 1 - variants: - - name: Reset - description: Reset the selected module - value: 1 -enum/PLL1FRACEN: - bit_size: 1 - variants: - - name: Reset - description: Reset latch to tranfer FRACN to the Sigma-Delta modulator - value: 0 - - name: Set - description: Set latch to tranfer FRACN to the Sigma-Delta modulator - value: 1 -enum/PLL1RGE: + - description: System clock selected for micro-controller clock output + name: SYSCLK + value: 0 + - description: pll2_p selected for micro-controller clock output + name: PLL2_P + value: 1 + - description: HSE selected for micro-controller clock output + name: HSE + value: 2 + - description: pll1_p selected for micro-controller clock output + name: PLL1_P + value: 3 + - description: CSI selected for micro-controller clock output + name: CSI + value: 4 + - description: LSI selected for micro-controller clock output + name: LSI + value: 5 +enum/PLLRGE: bit_size: 2 variants: - - name: Range1 - description: Frequency is between 1 and 2 MHz - value: 0 - - name: Range2 - description: Frequency is between 2 and 4 MHz - value: 1 - - name: Range4 - description: Frequency is between 4 and 8 MHz - value: 2 - - name: Range8 - description: Frequency is between 8 and 16 MHz - value: 3 -enum/PLL1VCOSEL: - bit_size: 1 - variants: - - name: WideVCO - description: VCO frequency range 192 to 836 MHz - value: 0 - - name: MediumVCO - description: VCO frequency range 150 to 420 MHz - value: 1 + - description: Frequency is between 1 and 2 MHz + name: Range1 + value: 0 + - description: Frequency is between 2 and 4 MHz + name: Range2 + value: 1 + - description: Frequency is between 4 and 8 MHz + name: Range4 + value: 2 + - description: Frequency is between 8 and 16 MHz + name: Range8 + value: 3 enum/PLLSRC: bit_size: 2 variants: - - name: HSI - description: HSI selected as PLL clock - value: 0 - - name: CSI - description: CSI selected as PLL clock - value: 1 - - name: HSE - description: HSE selected as PLL clock - value: 2 - - name: None - description: No clock sent to DIVMx dividers and PLLs - value: 3 + - description: HSI selected as PLL clock + name: HSI + value: 0 + - description: CSI selected as PLL clock + name: CSI + value: 1 + - description: HSE selected as PLL clock + name: HSE + value: 2 + - description: No clock sent to DIVMx dividers and PLLs + name: None + value: 3 +enum/PLLVCOSEL: + bit_size: 1 + variants: + - description: VCO frequency range 192 to 836 MHz + name: WideVCO + value: 0 + - description: VCO frequency range 150 to 420 MHz + name: MediumVCO + value: 1 enum/RNGSEL: bit_size: 2 variants: - - name: HSI48 - description: HSI48 selected as peripheral clock - value: 0 - - name: PLL1_Q - description: pll1_q selected as peripheral clock - value: 1 - - name: LSE - description: LSE selected as peripheral clock - value: 2 - - name: LSI - description: LSI selected as peripheral clock - value: 3 + - description: HSI48 selected as peripheral clock + name: HSI48 + value: 0 + - description: pll1_q selected as peripheral clock + name: PLL1_Q + value: 1 + - description: LSE selected as peripheral clock + name: LSE + value: 2 + - description: LSI selected as peripheral clock + name: LSI + value: 3 enum/RSR_CPURSTFR: bit_size: 1 variants: - - name: NoResetOccoured - description: No reset occoured for block - value: 0 - - name: ResetOccourred - description: Reset occoured for block - value: 1 + - description: No reset occoured for block + name: NoResetOccoured + value: 0 + - description: Reset occoured for block + name: ResetOccourred + value: 1 enum/RSR_RMVF: bit_size: 1 variants: - - name: NotActive - description: Not clearing the the reset flags - value: 0 - - name: Clear - description: Clear the reset flags - value: 1 -enum/RTCEN: - bit_size: 1 - variants: - - name: Disabled - description: RTC clock disabled - value: 0 - - name: Enabled - description: RTC clock enabled - value: 1 + - description: Not clearing the the reset flags + name: NotActive + value: 0 + - description: Clear the reset flags + name: Clear + value: 1 enum/RTCSEL: bit_size: 2 variants: - - name: NoClock - description: No clock - value: 0 - - name: LSE - description: LSE oscillator clock used as RTC clock - value: 1 - - name: LSI - description: LSI oscillator clock used as RTC clock - value: 2 - - name: HSE - description: HSE oscillator clock divided by a prescaler used as RTC clock - value: 3 -enum/SAI1SEL: + - description: No clock + name: NoClock + value: 0 + - description: LSE oscillator clock used as RTC clock + name: LSE + value: 1 + - description: LSI oscillator clock used as RTC clock + name: LSI + value: 2 + - description: HSE oscillator clock divided by a prescaler used as RTC clock + name: HSE + value: 3 +enum/SAIASEL: bit_size: 3 variants: - - name: PLL1_Q - description: pll1_q selected as peripheral clock - value: 0 - - name: PLL2_P - description: pll2_p selected as peripheral clock - value: 1 - - name: PLL3_P - description: pll3_p selected as peripheral clock - value: 2 - - name: I2S_CKIN - description: I2S_CKIN selected as peripheral clock - value: 3 - - name: PER - description: PER selected as peripheral clock - value: 4 -enum/SAI4ASEL: + - description: pll1_q selected as peripheral clock + name: PLL1_Q + value: 0 + - description: pll2_p selected as peripheral clock + name: PLL2_P + value: 1 + - description: pll3_p selected as peripheral clock + name: PLL3_P + value: 2 + - description: i2s_ckin selected as peripheral clock + name: I2S_CKIN + value: 3 + - description: PER selected as peripheral clock + name: PER + value: 4 +enum/SAISEL: bit_size: 3 variants: - - name: PLL1_Q - description: pll1_q selected as peripheral clock - value: 0 - - name: PLL2_P - description: pll2_p selected as peripheral clock - value: 1 - - name: PLL3_P - description: pll3_p selected as peripheral clock - value: 2 - - name: I2S_CKIN - description: i2s_ckin selected as peripheral clock - value: 3 - - name: PER - description: PER selected as peripheral clock - value: 4 + - description: pll1_q selected as peripheral clock + name: PLL1_Q + value: 0 + - description: pll2_p selected as peripheral clock + name: PLL2_P + value: 1 + - description: pll3_p selected as peripheral clock + name: PLL3_P + value: 2 + - description: I2S_CKIN selected as peripheral clock + name: I2S_CKIN + value: 3 + - description: PER selected as peripheral clock + name: PER + value: 4 enum/SDMMCSEL: bit_size: 1 variants: - - name: PLL1_Q - description: pll1_q selected as peripheral clock - value: 0 - - name: PLL2_R - description: pll2_r selected as peripheral clock - value: 1 + - description: pll1_q selected as peripheral clock + name: PLL1_Q + value: 0 + - description: pll2_r selected as peripheral clock + name: PLL2_R + value: 1 enum/SPDIFSEL: bit_size: 2 variants: - - name: PLL1_Q - description: pll1_q selected as peripheral clock - value: 0 - - name: PLL2_R - description: pll2_r selected as peripheral clock - value: 1 - - name: PLL3_R - description: pll3_r selected as peripheral clock - value: 2 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 3 + - description: pll1_q selected as peripheral clock + name: PLL1_Q + value: 0 + - description: pll2_r selected as peripheral clock + name: PLL2_R + value: 1 + - description: pll3_r selected as peripheral clock + name: PLL3_R + value: 2 + - description: hsi_ker selected as peripheral clock + name: HSI_KER + value: 3 enum/SPI45SEL: bit_size: 3 variants: - - name: APB - description: APB clock selected as peripheral clock - value: 0 - - name: PLL2_Q - description: pll2_q selected as peripheral clock - value: 1 - - name: PLL3_Q - description: pll3_q selected as peripheral clock - value: 2 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 3 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 4 - - name: HSE - description: HSE selected as peripheral clock - value: 5 + - description: APB clock selected as peripheral clock + name: APB + value: 0 + - description: pll2_q selected as peripheral clock + name: PLL2_Q + value: 1 + - description: pll3_q selected as peripheral clock + name: PLL3_Q + value: 2 + - description: hsi_ker selected as peripheral clock + name: HSI_KER + value: 3 + - description: csi_ker selected as peripheral clock + name: CSI_KER + value: 4 + - description: HSE selected as peripheral clock + name: HSE + value: 5 enum/SPI6SEL: bit_size: 3 variants: - - name: RCC_PCLK4 - description: rcc_pclk4 selected as peripheral clock - value: 0 - - name: PLL2_Q - description: pll2_q selected as peripheral clock - value: 1 - - name: PLL3_Q - description: pll3_q selected as peripheral clock - value: 2 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 3 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 4 - - name: HSE - description: HSE selected as peripheral clock - value: 5 + - description: rcc_pclk4 selected as peripheral clock + name: RCC_PCLK4 + value: 0 + - description: pll2_q selected as peripheral clock + name: PLL2_Q + value: 1 + - description: pll3_q selected as peripheral clock + name: PLL3_Q + value: 2 + - description: hsi_ker selected as peripheral clock + name: HSI_KER + value: 3 + - description: csi_ker selected as peripheral clock + name: CSI_KER + value: 4 + - description: HSE selected as peripheral clock + name: HSE + value: 5 enum/STOPWUCK: bit_size: 1 variants: - - name: HSI - description: HSI selected as wake up clock from system Stop - value: 0 - - name: CSI - description: CSI selected as wake up clock from system Stop - value: 1 + - description: HSI selected as wake up clock from system Stop + name: HSI + value: 0 + - description: CSI selected as wake up clock from system Stop + name: CSI + value: 1 enum/SW: bit_size: 3 variants: - - name: HSI - description: HSI selected as system clock - value: 0 - - name: CSI - description: CSI selected as system clock - value: 1 - - name: HSE - description: HSE selected as system clock - value: 2 - - name: PLL1 - description: PLL1 selected as system clock - value: 3 + - description: HSI selected as system clock + name: HSI + value: 0 + - description: CSI selected as system clock + name: CSI + value: 1 + - description: HSE selected as system clock + name: HSE + value: 2 + - description: PLL1 selected as system clock + name: PLL1 + value: 3 enum/SWPSEL: bit_size: 1 variants: - - name: PCLK - description: pclk selected as peripheral clock - value: 0 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 1 + - description: pclk selected as peripheral clock + name: PCLK + value: 0 + - description: hsi_ker selected as peripheral clock + name: HSI_KER + value: 1 enum/SWSR: bit_size: 3 variants: - - name: HSI - description: HSI oscillator used as system clock - value: 0 - - name: CSI - description: CSI oscillator used as system clock - value: 1 - - name: HSE - description: HSE oscillator used as system clock - value: 2 - - name: PLL1 - description: PLL1 used as system clock - value: 3 -enum/SYSCFGRST: - bit_size: 1 - variants: - - name: Reset - description: Reset the selected module - value: 1 -enum/TIM1RST: - bit_size: 1 - variants: - - name: Reset - description: Reset the selected module - value: 1 -enum/TIM2RST: - bit_size: 1 - variants: - - name: Reset - description: Reset the selected module - value: 1 + - description: HSI oscillator used as system clock + name: HSI + value: 0 + - description: CSI oscillator used as system clock + name: CSI + value: 1 + - description: HSE oscillator used as system clock + name: HSE + value: 2 + - description: PLL1 used as system clock + name: PLL1 + value: 3 enum/TIMPRE: bit_size: 1 variants: - - name: DefaultX2 - description: Timer kernel clock equal to 2x pclk by default - value: 0 - - name: DefaultX4 - description: Timer kernel clock equal to 4x pclk by default - value: 1 + - description: Timer kernel clock equal to 2x pclk by default + name: DefaultX2 + value: 0 + - description: Timer kernel clock equal to 4x pclk by default + name: DefaultX4 + value: 1 enum/USART16SEL: bit_size: 3 variants: - - name: RCC_PCLK2 - description: rcc_pclk2 selected as peripheral clock - value: 0 - - name: PLL2_Q - description: pll2_q selected as peripheral clock - value: 1 - - name: PLL3_Q - description: pll3_q selected as peripheral clock - value: 2 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 3 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 4 - - name: LSE - description: LSE selected as peripheral clock - value: 5 + - description: rcc_pclk2 selected as peripheral clock + name: RCC_PCLK2 + value: 0 + - description: pll2_q selected as peripheral clock + name: PLL2_Q + value: 1 + - description: pll3_q selected as peripheral clock + name: PLL3_Q + value: 2 + - description: hsi_ker selected as peripheral clock + name: HSI_KER + value: 3 + - description: csi_ker selected as peripheral clock + name: CSI_KER + value: 4 + - description: LSE selected as peripheral clock + name: LSE + value: 5 enum/USART234578SEL: bit_size: 3 variants: - - name: RCC_PCLK1 - description: rcc_pclk1 selected as peripheral clock - value: 0 - - name: PLL2_Q - description: pll2_q selected as peripheral clock - value: 1 - - name: PLL3_Q - description: pll3_q selected as peripheral clock - value: 2 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 3 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 4 - - name: LSE - description: LSE selected as peripheral clock - value: 5 + - description: rcc_pclk1 selected as peripheral clock + name: RCC_PCLK1 + value: 0 + - description: pll2_q selected as peripheral clock + name: PLL2_Q + value: 1 + - description: pll3_q selected as peripheral clock + name: PLL3_Q + value: 2 + - description: hsi_ker selected as peripheral clock + name: HSI_KER + value: 3 + - description: csi_ker selected as peripheral clock + name: CSI_KER + value: 4 + - description: LSE selected as peripheral clock + name: LSE + value: 5 enum/USBSEL: bit_size: 2 variants: - - name: DISABLE - description: Disable the kernel clock - value: 0 - - name: PLL1_Q - description: pll1_q selected as peripheral clock - value: 1 - - name: PLL3_Q - description: pll3_q selected as peripheral clock - value: 2 - - name: HSI48 - description: HSI48 selected as peripheral clock - value: 3 -enum/WW1RSC: + - description: Disable the kernel clock + name: DISABLE + value: 0 + - description: pll1_q selected as peripheral clock + name: PLL1_Q + value: 1 + - description: pll3_q selected as peripheral clock + name: PLL3_Q + value: 2 + - description: HSI48 selected as peripheral clock + name: HSI48 + value: 3 +enum/WWRSC: bit_size: 1 variants: - - name: Clear - description: Clear WWDG1 scope control - value: 0 - - name: Set - description: Set WWDG1 scope control - value: 1 + - description: Clear WWDG1 scope control + name: Clear + value: 0 + - description: Set WWDG1 scope control + name: Set + value: 1 +fieldset/AHB1ENR: + description: RCC AHB1 Clock Register + fields: + - bit_offset: 0 + bit_size: 1 + description: DMA1 Clock Enable + name: DMA1EN + - bit_offset: 1 + bit_size: 1 + description: DMA2 Clock Enable + name: DMA2EN + - bit_offset: 5 + bit_size: 1 + description: ADC1/2 Peripheral Clocks Enable + name: ADC12EN + - bit_offset: 15 + bit_size: 1 + description: Ethernet MAC bus interface Clock Enable + name: ETH1MACEN + - bit_offset: 16 + bit_size: 1 + description: Ethernet Transmission Clock Enable + name: ETH1TXEN + - bit_offset: 17 + bit_size: 1 + description: Ethernet Reception Clock Enable + name: ETH1RXEN + - bit_offset: 18 + bit_size: 1 + description: ' Enable USB_PHY2 clocks ' + name: USB2OTGHSULPIEN + - bit_offset: 25 + bit_size: 1 + description: USB1OTG Peripheral Clocks Enable + name: USB1OTGEN + - bit_offset: 26 + bit_size: 1 + description: USB_PHY1 Clocks Enable + name: USB1ULPIEN + - bit_offset: 27 + bit_size: 1 + description: USB2OTG Peripheral Clocks Enable + name: USB2OTGEN + - bit_offset: 28 + bit_size: 1 + description: USB_PHY2 Clocks Enable + name: USB2ULPIEN + - bit_offset: 14 + bit_size: 1 + description: ART Clock Enable + name: ARTEN +fieldset/AHB1LPENR: + description: RCC AHB1 Sleep Clock Register + fields: + - bit_offset: 0 + bit_size: 1 + description: DMA1 Clock Enable During CSleep Mode + name: DMA1LPEN + - bit_offset: 1 + bit_size: 1 + description: DMA2 Clock Enable During CSleep Mode + name: DMA2LPEN + - bit_offset: 5 + bit_size: 1 + description: ADC1/2 Peripheral Clocks Enable During CSleep Mode + name: ADC12LPEN + - bit_offset: 15 + bit_size: 1 + description: Ethernet MAC bus interface Clock Enable During CSleep Mode + name: ETH1MACLPEN + - bit_offset: 16 + bit_size: 1 + description: Ethernet Transmission Clock Enable During CSleep Mode + name: ETH1TXLPEN + - bit_offset: 17 + bit_size: 1 + description: Ethernet Reception Clock Enable During CSleep Mode + name: ETH1RXLPEN + - bit_offset: 25 + bit_size: 1 + description: USB1OTG peripheral clock enable during CSleep mode + name: USB1OTGLPEN + - bit_offset: 26 + bit_size: 1 + description: USB_PHY1 clock enable during CSleep mode + name: USB1OTGHSULPILPEN + - bit_offset: 27 + bit_size: 1 + description: USB2OTG peripheral clock enable during CSleep mode + name: USB2OTGLPEN + - bit_offset: 28 + bit_size: 1 + description: USB_PHY2 clocks enable during CSleep mode + name: USB2OTGHSULPILPEN + - bit_offset: 14 + bit_size: 1 + description: ART Clock Enable During CSleep Mode + name: ARTLPEN + - bit_offset: 26 + bit_size: 1 + description: USB_PHY1 clock enable during CSleep mode + name: USB1ULPILPEN + - bit_offset: 28 + bit_size: 1 + description: USB_PHY2 clocks enable during CSleep mode + name: USB2ULPILPEN +fieldset/AHB1RSTR: + description: RCC AHB1 Peripheral Reset Register + fields: + - bit_offset: 0 + bit_size: 1 + description: DMA1 block reset + name: DMA1RST + - bit_offset: 1 + bit_size: 1 + description: DMA2 block reset + name: DMA2RST + - bit_offset: 5 + bit_size: 1 + description: ADC1&2 block reset + name: ADC12RST + - bit_offset: 15 + bit_size: 1 + description: ETH1MAC block reset + name: ETH1MACRST + - bit_offset: 25 + bit_size: 1 + description: USB1OTG block reset + name: USB1OTGRST + - bit_offset: 27 + bit_size: 1 + description: USB2OTG block reset + name: USB2OTGRST + - bit_offset: 14 + bit_size: 1 + description: ART block reset + name: ARTRST +fieldset/AHB2ENR: + description: RCC AHB2 Clock Register + fields: + - bit_offset: 0 + bit_size: 1 + description: DCMI peripheral clock + name: DCMIEN + - bit_offset: 4 + bit_size: 1 + description: CRYPT peripheral clock enable + name: CRYPTEN + - bit_offset: 5 + bit_size: 1 + description: HASH peripheral clock enable + name: HASHEN + - bit_offset: 6 + bit_size: 1 + description: RNG peripheral clocks enable + name: RNGEN + - bit_offset: 9 + bit_size: 1 + description: SDMMC2 and SDMMC2 delay clock enable + name: SDMMC2EN + - bit_offset: 29 + bit_size: 1 + description: SRAM1 block enable + name: SRAM1EN + - bit_offset: 30 + bit_size: 1 + description: SRAM2 block enable + name: SRAM2EN + - bit_offset: 31 + bit_size: 1 + description: SRAM3 block enable + name: SRAM3EN +fieldset/AHB2LPENR: + description: RCC AHB2 Sleep Clock Register + fields: + - bit_offset: 0 + bit_size: 1 + description: DCMI peripheral clock enable during csleep mode + name: DCMILPEN + - bit_offset: 4 + bit_size: 1 + description: CRYPT peripheral clock enable during CSleep mode + name: CRYPTLPEN + - bit_offset: 5 + bit_size: 1 + description: HASH peripheral clock enable during CSleep mode + name: HASHLPEN + - bit_offset: 6 + bit_size: 1 + description: RNG peripheral clock enable during CSleep mode + name: RNGLPEN + - bit_offset: 9 + bit_size: 1 + description: SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode + name: SDMMC2LPEN + - bit_offset: 29 + bit_size: 1 + description: SRAM1 Clock Enable During CSleep Mode + name: SRAM1LPEN + - bit_offset: 30 + bit_size: 1 + description: SRAM2 Clock Enable During CSleep Mode + name: SRAM2LPEN + - bit_offset: 31 + bit_size: 1 + description: SRAM3 Clock Enable During CSleep Mode + name: SRAM3LPEN +fieldset/AHB2RSTR: + description: RCC AHB2 Peripheral Reset Register + fields: + - bit_offset: 0 + bit_size: 1 + description: CAMITF block reset + name: CAMITFRST + - bit_offset: 4 + bit_size: 1 + description: Cryptography block reset + name: CRYPTRST + - bit_offset: 5 + bit_size: 1 + description: Hash block reset + name: HASHRST + - bit_offset: 6 + bit_size: 1 + description: Random Number Generator block reset + name: RNGRST + - bit_offset: 9 + bit_size: 1 + description: SDMMC2 and SDMMC2 Delay block reset + name: SDMMC2RST +fieldset/AHB3ENR: + description: RCC AHB3 Clock Register + fields: + - bit_offset: 0 + bit_size: 1 + description: MDMA Peripheral Clock Enable + name: MDMAEN + - bit_offset: 4 + bit_size: 1 + description: DMA2D Peripheral Clock Enable + name: DMA2DEN + - bit_offset: 5 + bit_size: 1 + description: JPGDEC Peripheral Clock Enable + name: JPGDECEN + - bit_offset: 12 + bit_size: 1 + description: FMC Peripheral Clocks Enable + name: FMCEN + - bit_offset: 14 + bit_size: 1 + description: QUADSPI and QUADSPI Delay Clock Enable + name: QSPIEN + - bit_offset: 16 + bit_size: 1 + description: SDMMC1 and SDMMC1 Delay Clock Enable + name: SDMMC1EN + - bit_offset: 28 + bit_size: 1 + description: D1 DTCM1 block enable + name: DTCM1EN + - bit_offset: 29 + bit_size: 1 + description: D1 DTCM2 block enable + name: DTCM2EN + - bit_offset: 30 + bit_size: 1 + description: D1 ITCM block enable + name: ITCM1EN + - bit_offset: 31 + bit_size: 1 + description: AXISRAM block enable + name: AXISRAMEN +fieldset/AHB3LPENR: + description: RCC AHB3 Sleep Clock Register + fields: + - bit_offset: 0 + bit_size: 1 + description: MDMA Clock Enable During CSleep Mode + name: MDMALPEN + - bit_offset: 4 + bit_size: 1 + description: DMA2D Clock Enable During CSleep Mode + name: DMA2DLPEN + - bit_offset: 5 + bit_size: 1 + description: JPGDEC Clock Enable During CSleep Mode + name: JPGDECLPEN + - bit_offset: 8 + bit_size: 1 + description: FLITF Clock Enable During CSleep Mode + name: FLASHLPEN + - bit_offset: 12 + bit_size: 1 + description: FMC Peripheral Clocks Enable During CSleep Mode + name: FMCLPEN + - bit_offset: 14 + bit_size: 1 + description: QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode + name: QSPILPEN + - bit_offset: 16 + bit_size: 1 + description: SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode + name: SDMMC1LPEN + - bit_offset: 28 + bit_size: 1 + description: D1DTCM1 Block Clock Enable During CSleep mode + name: D1DTCM1LPEN + - bit_offset: 29 + bit_size: 1 + description: D1 DTCM2 Block Clock Enable During CSleep mode + name: DTCM2LPEN + - bit_offset: 30 + bit_size: 1 + description: D1ITCM Block Clock Enable During CSleep mode + name: ITCMLPEN + - bit_offset: 31 + bit_size: 1 + description: AXISRAM Block Clock Enable During CSleep mode + name: AXISRAMLPEN + - bit_offset: 8 + bit_size: 1 + description: FLITF Clock Enable During CSleep Mode + name: FLITFLPEN +fieldset/AHB3RSTR: + description: RCC AHB3 Reset Register + fields: + - bit_offset: 0 + bit_size: 1 + description: MDMA block reset + name: MDMARST + - bit_offset: 4 + bit_size: 1 + description: DMA2D block reset + name: DMA2DRST + - bit_offset: 5 + bit_size: 1 + description: JPGDEC block reset + name: JPGDECRST + - bit_offset: 12 + bit_size: 1 + description: FMC block reset + name: FMCRST + - bit_offset: 14 + bit_size: 1 + description: QUADSPI and QUADSPI delay block reset + name: QSPIRST + - bit_offset: 16 + bit_size: 1 + description: SDMMC1 and SDMMC1 delay block reset + name: SDMMC1RST + - bit_offset: 31 + bit_size: 1 + description: CPU reset + name: CPURST +fieldset/AHB4ENR: + description: RCC AHB4 Clock Register + fields: + - bit_offset: 0 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOAEN + - bit_offset: 1 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOBEN + - bit_offset: 2 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOCEN + - bit_offset: 3 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIODEN + - bit_offset: 4 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOEEN + - bit_offset: 5 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOFEN + - bit_offset: 6 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOGEN + - bit_offset: 7 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOHEN + - bit_offset: 8 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOIEN + - bit_offset: 9 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOJEN + - bit_offset: 10 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOKEN + - bit_offset: 19 + bit_size: 1 + description: CRC peripheral clock enable + name: CRCEN + - bit_offset: 21 + bit_size: 1 + description: BDMA and DMAMUX2 Clock Enable + name: BDMAEN + - bit_offset: 24 + bit_size: 1 + description: ADC3 Peripheral Clocks Enable + name: ADC3EN + - bit_offset: 25 + bit_size: 1 + description: HSEM peripheral clock enable + name: HSEMEN + - bit_offset: 28 + bit_size: 1 + description: Backup RAM Clock Enable + name: BKPRAMEN +fieldset/AHB4LPENR: + description: RCC AHB4 Sleep Clock Register + fields: + - bit_offset: 0 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOALPEN + - bit_offset: 1 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOBLPEN + - bit_offset: 2 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOCLPEN + - bit_offset: 3 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIODLPEN + - bit_offset: 4 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOELPEN + - bit_offset: 5 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOFLPEN + - bit_offset: 6 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOGLPEN + - bit_offset: 7 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOHLPEN + - bit_offset: 8 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOILPEN + - bit_offset: 9 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOJLPEN + - bit_offset: 10 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOKLPEN + - bit_offset: 19 + bit_size: 1 + description: CRC peripheral clock enable during CSleep mode + name: CRCLPEN + - bit_offset: 21 + bit_size: 1 + description: BDMA Clock Enable During CSleep Mode + name: BDMALPEN + - bit_offset: 24 + bit_size: 1 + description: ADC3 Peripheral Clocks Enable During CSleep Mode + name: ADC3LPEN + - bit_offset: 28 + bit_size: 1 + description: Backup RAM Clock Enable During CSleep Mode + name: BKPRAMLPEN + - bit_offset: 29 + bit_size: 1 + description: SRAM4 Clock Enable During CSleep Mode + name: SRAM4LPEN +fieldset/AHB4RSTR: + description: RCC AHB4 Peripheral Reset Register + fields: + - bit_offset: 0 + bit_size: 1 + description: GPIO block reset + name: GPIOARST + - bit_offset: 1 + bit_size: 1 + description: GPIO block reset + name: GPIOBRST + - bit_offset: 2 + bit_size: 1 + description: GPIO block reset + name: GPIOCRST + - bit_offset: 3 + bit_size: 1 + description: GPIO block reset + name: GPIODRST + - bit_offset: 4 + bit_size: 1 + description: GPIO block reset + name: GPIOERST + - bit_offset: 5 + bit_size: 1 + description: GPIO block reset + name: GPIOFRST + - bit_offset: 6 + bit_size: 1 + description: GPIO block reset + name: GPIOGRST + - bit_offset: 7 + bit_size: 1 + description: GPIO block reset + name: GPIOHRST + - bit_offset: 8 + bit_size: 1 + description: GPIO block reset + name: GPIOIRST + - bit_offset: 9 + bit_size: 1 + description: GPIO block reset + name: GPIOJRST + - bit_offset: 10 + bit_size: 1 + description: GPIO block reset + name: GPIOKRST + - bit_offset: 19 + bit_size: 1 + description: CRC block reset + name: CRCRST + - bit_offset: 21 + bit_size: 1 + description: BDMA block reset + name: BDMARST + - bit_offset: 24 + bit_size: 1 + description: ADC3 block reset + name: ADC3RST + - bit_offset: 25 + bit_size: 1 + description: HSEM block reset + name: HSEMRST +fieldset/APB1HENR: + description: RCC APB1 Clock Register + fields: + - bit_offset: 1 + bit_size: 1 + description: Clock Recovery System peripheral clock enable + name: CRSEN + - bit_offset: 2 + bit_size: 1 + description: SWPMI Peripheral Clocks Enable + name: SWPEN + - bit_offset: 4 + bit_size: 1 + description: OPAMP peripheral clock enable + name: OPAMPEN + - bit_offset: 5 + bit_size: 1 + description: MDIOS peripheral clock enable + name: MDIOSEN + - bit_offset: 8 + bit_size: 1 + description: FDCAN Peripheral Clocks Enable + name: FDCANEN +fieldset/APB1HLPENR: + description: RCC APB1 High Sleep Clock Register + fields: + - bit_offset: 1 + bit_size: 1 + description: Clock Recovery System peripheral clock enable during CSleep mode + name: CRSLPEN + - bit_offset: 2 + bit_size: 1 + description: SWPMI Peripheral Clocks Enable During CSleep Mode + name: SWPLPEN + - bit_offset: 4 + bit_size: 1 + description: OPAMP peripheral clock enable during CSleep mode + name: OPAMPLPEN + - bit_offset: 5 + bit_size: 1 + description: MDIOS peripheral clock enable during CSleep mode + name: MDIOSLPEN + - bit_offset: 8 + bit_size: 1 + description: FDCAN Peripheral Clocks Enable During CSleep Mode + name: FDCANLPEN +fieldset/APB1HRSTR: + description: RCC APB1 Peripheral Reset Register + fields: + - bit_offset: 1 + bit_size: 1 + description: Clock Recovery System reset + name: CRSRST + - bit_offset: 2 + bit_size: 1 + description: SWPMI block reset + name: SWPRST + - bit_offset: 4 + bit_size: 1 + description: OPAMP block reset + name: OPAMPRST + - bit_offset: 5 + bit_size: 1 + description: MDIOS block reset + name: MDIOSRST + - bit_offset: 8 + bit_size: 1 + description: FDCAN block reset + name: FDCANRST +fieldset/APB1LENR: + description: RCC APB1 Clock Register + fields: + - bit_offset: 0 + bit_size: 1 + description: TIM peripheral clock enable + name: TIM2EN + - bit_offset: 1 + bit_size: 1 + description: TIM peripheral clock enable + name: TIM3EN + - bit_offset: 2 + bit_size: 1 + description: TIM peripheral clock enable + name: TIM4EN + - bit_offset: 3 + bit_size: 1 + description: TIM peripheral clock enable + name: TIM5EN + - bit_offset: 4 + bit_size: 1 + description: TIM peripheral clock enable + name: TIM6EN + - bit_offset: 5 + bit_size: 1 + description: TIM peripheral clock enable + name: TIM7EN + - bit_offset: 6 + bit_size: 1 + description: TIM peripheral clock enable + name: TIM12EN + - bit_offset: 7 + bit_size: 1 + description: TIM peripheral clock enable + name: TIM13EN + - bit_offset: 8 + bit_size: 1 + description: TIM peripheral clock enable + name: TIM14EN + - bit_offset: 9 + bit_size: 1 + description: LPTIM1 Peripheral Clocks Enable + name: LPTIM1EN + - bit_offset: 14 + bit_size: 1 + description: SPI2 Peripheral Clocks Enable + name: SPI2EN + - bit_offset: 15 + bit_size: 1 + description: SPI3 Peripheral Clocks Enable + name: SPI3EN + - bit_offset: 16 + bit_size: 1 + description: SPDIFRX Peripheral Clocks Enable + name: SPDIFRXEN + - bit_offset: 17 + bit_size: 1 + description: USART2 Peripheral Clocks Enable + name: USART2EN + - bit_offset: 18 + bit_size: 1 + description: USART3 Peripheral Clocks Enable + name: USART3EN + - bit_offset: 19 + bit_size: 1 + description: UART4 Peripheral Clocks Enable + name: UART4EN + - bit_offset: 20 + bit_size: 1 + description: UART5 Peripheral Clocks Enable + name: UART5EN + - bit_offset: 21 + bit_size: 1 + description: I2C1 Peripheral Clocks Enable + name: I2C1EN + - bit_offset: 22 + bit_size: 1 + description: I2C2 Peripheral Clocks Enable + name: I2C2EN + - bit_offset: 23 + bit_size: 1 + description: I2C3 Peripheral Clocks Enable + name: I2C3EN + - bit_offset: 27 + bit_size: 1 + description: HDMI-CEC peripheral clock enable + name: CECEN + - bit_offset: 29 + bit_size: 1 + description: DAC1&2 peripheral clock enable + name: DAC12EN + - bit_offset: 30 + bit_size: 1 + description: UART7 Peripheral Clocks Enable + name: UART7EN + - bit_offset: 31 + bit_size: 1 + description: UART8 Peripheral Clocks Enable + name: UART8EN + - bit_offset: 11 + bit_size: 1 + description: WWDG2 peripheral clock enable + name: WWDG2EN +fieldset/APB1LLPENR: + description: RCC APB1 Low Sleep Clock Register + fields: + - bit_offset: 0 + bit_size: 1 + description: TIM2 peripheral clock enable during CSleep mode + name: TIM2LPEN + - bit_offset: 1 + bit_size: 1 + description: TIM3 peripheral clock enable during CSleep mode + name: TIM3LPEN + - bit_offset: 2 + bit_size: 1 + description: TIM4 peripheral clock enable during CSleep mode + name: TIM4LPEN + - bit_offset: 3 + bit_size: 1 + description: TIM5 peripheral clock enable during CSleep mode + name: TIM5LPEN + - bit_offset: 4 + bit_size: 1 + description: TIM6 peripheral clock enable during CSleep mode + name: TIM6LPEN + - bit_offset: 5 + bit_size: 1 + description: TIM7 peripheral clock enable during CSleep mode + name: TIM7LPEN + - bit_offset: 6 + bit_size: 1 + description: TIM12 peripheral clock enable during CSleep mode + name: TIM12LPEN + - bit_offset: 7 + bit_size: 1 + description: TIM13 peripheral clock enable during CSleep mode + name: TIM13LPEN + - bit_offset: 8 + bit_size: 1 + description: TIM14 peripheral clock enable during CSleep mode + name: TIM14LPEN + - bit_offset: 9 + bit_size: 1 + description: LPTIM1 Peripheral Clocks Enable During CSleep Mode + name: LPTIM1LPEN + - bit_offset: 14 + bit_size: 1 + description: SPI2 Peripheral Clocks Enable During CSleep Mode + name: SPI2LPEN + - bit_offset: 15 + bit_size: 1 + description: SPI3 Peripheral Clocks Enable During CSleep Mode + name: SPI3LPEN + - bit_offset: 16 + bit_size: 1 + description: SPDIFRX Peripheral Clocks Enable During CSleep Mode + name: SPDIFRXLPEN + - bit_offset: 17 + bit_size: 1 + description: USART2 Peripheral Clocks Enable During CSleep Mode + name: USART2LPEN + - bit_offset: 18 + bit_size: 1 + description: USART3 Peripheral Clocks Enable During CSleep Mode + name: USART3LPEN + - bit_offset: 19 + bit_size: 1 + description: UART4 Peripheral Clocks Enable During CSleep Mode + name: UART4LPEN + - bit_offset: 20 + bit_size: 1 + description: UART5 Peripheral Clocks Enable During CSleep Mode + name: UART5LPEN + - bit_offset: 21 + bit_size: 1 + description: I2C1 Peripheral Clocks Enable During CSleep Mode + name: I2C1LPEN + - bit_offset: 22 + bit_size: 1 + description: I2C2 Peripheral Clocks Enable During CSleep Mode + name: I2C2LPEN + - bit_offset: 23 + bit_size: 1 + description: I2C3 Peripheral Clocks Enable During CSleep Mode + name: I2C3LPEN + - bit_offset: 27 + bit_size: 1 + description: HDMI-CEC Peripheral Clocks Enable During CSleep Mode + name: CECLPEN + - bit_offset: 29 + bit_size: 1 + description: DAC1/2 peripheral clock enable during CSleep mode + name: DAC12LPEN + - bit_offset: 30 + bit_size: 1 + description: UART7 Peripheral Clocks Enable During CSleep Mode + name: UART7LPEN + - bit_offset: 31 + bit_size: 1 + description: UART8 Peripheral Clocks Enable During CSleep Mode + name: UART8LPEN + - bit_offset: 11 + bit_size: 1 + description: WWDG2 peripheral Clocks Enable During CSleep Mode + name: WWDG2LPEN +fieldset/APB1LRSTR: + description: RCC APB1 Peripheral Reset Register + fields: + - bit_offset: 0 + bit_size: 1 + description: TIM block reset + name: TIM2RST + - bit_offset: 1 + bit_size: 1 + description: TIM block reset + name: TIM3RST + - bit_offset: 2 + bit_size: 1 + description: TIM block reset + name: TIM4RST + - bit_offset: 3 + bit_size: 1 + description: TIM block reset + name: TIM5RST + - bit_offset: 4 + bit_size: 1 + description: TIM block reset + name: TIM6RST + - bit_offset: 5 + bit_size: 1 + description: TIM block reset + name: TIM7RST + - bit_offset: 6 + bit_size: 1 + description: TIM block reset + name: TIM12RST + - bit_offset: 7 + bit_size: 1 + description: TIM block reset + name: TIM13RST + - bit_offset: 8 + bit_size: 1 + description: TIM block reset + name: TIM14RST + - bit_offset: 9 + bit_size: 1 + description: TIM block reset + name: LPTIM1RST + - bit_offset: 14 + bit_size: 1 + description: SPI2 block reset + name: SPI2RST + - bit_offset: 15 + bit_size: 1 + description: SPI3 block reset + name: SPI3RST + - bit_offset: 16 + bit_size: 1 + description: SPDIFRX block reset + name: SPDIFRXRST + - bit_offset: 17 + bit_size: 1 + description: USART2 block reset + name: USART2RST + - bit_offset: 18 + bit_size: 1 + description: USART3 block reset + name: USART3RST + - bit_offset: 19 + bit_size: 1 + description: UART4 block reset + name: UART4RST + - bit_offset: 20 + bit_size: 1 + description: UART5 block reset + name: UART5RST + - bit_offset: 21 + bit_size: 1 + description: I2C1 block reset + name: I2C1RST + - bit_offset: 22 + bit_size: 1 + description: I2C2 block reset + name: I2C2RST + - bit_offset: 23 + bit_size: 1 + description: I2C3 block reset + name: I2C3RST + - bit_offset: 27 + bit_size: 1 + description: HDMI-CEC block reset + name: CECRST + - bit_offset: 29 + bit_size: 1 + description: DAC1 and 2 Blocks Reset + name: DAC12RST + - bit_offset: 30 + bit_size: 1 + description: UART7 block reset + name: UART7RST + - bit_offset: 31 + bit_size: 1 + description: UART8 block reset + name: UART8RST +fieldset/APB2ENR: + description: RCC APB2 Clock Register + fields: + - bit_offset: 0 + bit_size: 1 + description: TIM1 peripheral clock enable + name: TIM1EN + - bit_offset: 1 + bit_size: 1 + description: TIM8 peripheral clock enable + name: TIM8EN + - bit_offset: 4 + bit_size: 1 + description: USART1 Peripheral Clocks Enable + name: USART1EN + - bit_offset: 5 + bit_size: 1 + description: USART6 Peripheral Clocks Enable + name: USART6EN + - bit_offset: 12 + bit_size: 1 + description: SPI1 Peripheral Clocks Enable + name: SPI1EN + - bit_offset: 13 + bit_size: 1 + description: SPI4 Peripheral Clocks Enable + name: SPI4EN + - bit_offset: 16 + bit_size: 1 + description: TIM15 peripheral clock enable + name: TIM15EN + - bit_offset: 17 + bit_size: 1 + description: TIM16 peripheral clock enable + name: TIM16EN + - bit_offset: 18 + bit_size: 1 + description: TIM17 peripheral clock enable + name: TIM17EN + - bit_offset: 20 + bit_size: 1 + description: SPI5 Peripheral Clocks Enable + name: SPI5EN + - bit_offset: 22 + bit_size: 1 + description: SAI1 Peripheral Clocks Enable + name: SAI1EN + - bit_offset: 23 + bit_size: 1 + description: SAI2 Peripheral Clocks Enable + name: SAI2EN + - bit_offset: 24 + bit_size: 1 + description: SAI3 Peripheral Clocks Enable + name: SAI3EN + - bit_offset: 28 + bit_size: 1 + description: DFSDM1 Peripheral Clocks Enable + name: DFSDM1EN + - bit_offset: 29 + bit_size: 1 + description: HRTIM peripheral clock enable + name: HRTIMEN +fieldset/APB2LPENR: + description: RCC APB2 Sleep Clock Register + fields: + - bit_offset: 0 + bit_size: 1 + description: TIM1 peripheral clock enable during CSleep mode + name: TIM1LPEN + - bit_offset: 1 + bit_size: 1 + description: TIM8 peripheral clock enable during CSleep mode + name: TIM8LPEN + - bit_offset: 4 + bit_size: 1 + description: USART1 Peripheral Clocks Enable During CSleep Mode + name: USART1LPEN + - bit_offset: 5 + bit_size: 1 + description: USART6 Peripheral Clocks Enable During CSleep Mode + name: USART6LPEN + - bit_offset: 12 + bit_size: 1 + description: SPI1 Peripheral Clocks Enable During CSleep Mode + name: SPI1LPEN + - bit_offset: 13 + bit_size: 1 + description: SPI4 Peripheral Clocks Enable During CSleep Mode + name: SPI4LPEN + - bit_offset: 16 + bit_size: 1 + description: TIM15 peripheral clock enable during CSleep mode + name: TIM15LPEN + - bit_offset: 17 + bit_size: 1 + description: TIM16 peripheral clock enable during CSleep mode + name: TIM16LPEN + - bit_offset: 18 + bit_size: 1 + description: TIM17 peripheral clock enable during CSleep mode + name: TIM17LPEN + - bit_offset: 20 + bit_size: 1 + description: SPI5 Peripheral Clocks Enable During CSleep Mode + name: SPI5LPEN + - bit_offset: 22 + bit_size: 1 + description: SAI1 Peripheral Clocks Enable During CSleep Mode + name: SAI1LPEN + - bit_offset: 23 + bit_size: 1 + description: SAI2 Peripheral Clocks Enable During CSleep Mode + name: SAI2LPEN + - bit_offset: 24 + bit_size: 1 + description: SAI3 Peripheral Clocks Enable During CSleep Mode + name: SAI3LPEN + - bit_offset: 28 + bit_size: 1 + description: DFSDM1 Peripheral Clocks Enable During CSleep Mode + name: DFSDM1LPEN + - bit_offset: 29 + bit_size: 1 + description: HRTIM peripheral clock enable during CSleep mode + name: HRTIMLPEN +fieldset/APB2RSTR: + description: RCC APB2 Peripheral Reset Register + fields: + - bit_offset: 0 + bit_size: 1 + description: TIM1 block reset + name: TIM1RST + - bit_offset: 1 + bit_size: 1 + description: TIM8 block reset + name: TIM8RST + - bit_offset: 4 + bit_size: 1 + description: USART1 block reset + name: USART1RST + - bit_offset: 5 + bit_size: 1 + description: USART6 block reset + name: USART6RST + - bit_offset: 12 + bit_size: 1 + description: SPI1 block reset + name: SPI1RST + - bit_offset: 13 + bit_size: 1 + description: SPI4 block reset + name: SPI4RST + - bit_offset: 16 + bit_size: 1 + description: TIM15 block reset + name: TIM15RST + - bit_offset: 17 + bit_size: 1 + description: TIM16 block reset + name: TIM16RST + - bit_offset: 18 + bit_size: 1 + description: TIM17 block reset + name: TIM17RST + - bit_offset: 20 + bit_size: 1 + description: SPI5 block reset + name: SPI5RST + - bit_offset: 22 + bit_size: 1 + description: SAI1 block reset + name: SAI1RST + - bit_offset: 23 + bit_size: 1 + description: SAI2 block reset + name: SAI2RST + - bit_offset: 24 + bit_size: 1 + description: SAI3 block reset + name: SAI3RST + - bit_offset: 28 + bit_size: 1 + description: DFSDM1 block reset + name: DFSDM1RST + - bit_offset: 29 + bit_size: 1 + description: HRTIM block reset + name: HRTIMRST +fieldset/APB3ENR: + description: RCC APB3 Clock Register + fields: + - bit_offset: 3 + bit_size: 1 + description: LTDC peripheral clock enable + name: LTDCEN + - bit_offset: 6 + bit_size: 1 + description: WWDG1 Clock Enable + name: WWDG1EN + - bit_offset: 4 + bit_size: 1 + description: DSI Peripheral clocks enable + name: DSIEN +fieldset/APB3LPENR: + description: RCC APB3 Sleep Clock Register + fields: + - bit_offset: 3 + bit_size: 1 + description: LTDC peripheral clock enable during CSleep mode + name: LTDCLPEN + - bit_offset: 6 + bit_size: 1 + description: WWDG1 Clock Enable During CSleep Mode + name: WWDG1LPEN + - bit_offset: 4 + bit_size: 1 + description: DSI Peripheral Clock Enable During CSleep Mode + name: DSILPEN +fieldset/APB3RSTR: + description: RCC APB3 Peripheral Reset Register + fields: + - bit_offset: 3 + bit_size: 1 + description: LTDC block reset + name: LTDCRST + - bit_offset: 4 + bit_size: 1 + description: DSI block reset + name: DSIRST +fieldset/APB4ENR: + description: RCC APB4 Clock Register + fields: + - bit_offset: 1 + bit_size: 1 + description: SYSCFG peripheral clock enable + name: SYSCFGEN + - bit_offset: 3 + bit_size: 1 + description: LPUART1 Peripheral Clocks Enable + name: LPUART1EN + - bit_offset: 5 + bit_size: 1 + description: SPI6 Peripheral Clocks Enable + name: SPI6EN + - bit_offset: 7 + bit_size: 1 + description: I2C4 Peripheral Clocks Enable + name: I2C4EN + - bit_offset: 9 + bit_size: 1 + description: LPTIM2 Peripheral Clocks Enable + name: LPTIM2EN + - bit_offset: 10 + bit_size: 1 + description: LPTIM3 Peripheral Clocks Enable + name: LPTIM3EN + - bit_offset: 11 + bit_size: 1 + description: LPTIM4 Peripheral Clocks Enable + name: LPTIM4EN + - bit_offset: 12 + bit_size: 1 + description: LPTIM5 Peripheral Clocks Enable + name: LPTIM5EN + - bit_offset: 14 + bit_size: 1 + description: COMP1/2 peripheral clock enable + name: COMP12EN + - bit_offset: 15 + bit_size: 1 + description: VREF peripheral clock enable + name: VREFEN + - bit_offset: 16 + bit_size: 1 + description: RTC APB Clock Enable + name: RTCAPBEN + - bit_offset: 21 + bit_size: 1 + description: SAI4 Peripheral Clocks Enable + name: SAI4EN +fieldset/APB4LPENR: + description: RCC APB4 Sleep Clock Register + fields: + - bit_offset: 1 + bit_size: 1 + description: SYSCFG peripheral clock enable during CSleep mode + name: SYSCFGLPEN + - bit_offset: 3 + bit_size: 1 + description: LPUART1 Peripheral Clocks Enable During CSleep Mode + name: LPUART1LPEN + - bit_offset: 5 + bit_size: 1 + description: SPI6 Peripheral Clocks Enable During CSleep Mode + name: SPI6LPEN + - bit_offset: 7 + bit_size: 1 + description: I2C4 Peripheral Clocks Enable During CSleep Mode + name: I2C4LPEN + - bit_offset: 9 + bit_size: 1 + description: LPTIM2 Peripheral Clocks Enable During CSleep Mode + name: LPTIM2LPEN + - bit_offset: 10 + bit_size: 1 + description: LPTIM3 Peripheral Clocks Enable During CSleep Mode + name: LPTIM3LPEN + - bit_offset: 11 + bit_size: 1 + description: LPTIM4 Peripheral Clocks Enable During CSleep Mode + name: LPTIM4LPEN + - bit_offset: 12 + bit_size: 1 + description: LPTIM5 Peripheral Clocks Enable During CSleep Mode + name: LPTIM5LPEN + - bit_offset: 14 + bit_size: 1 + description: COMP1/2 peripheral clock enable during CSleep mode + name: COMP12LPEN + - bit_offset: 15 + bit_size: 1 + description: VREF peripheral clock enable during CSleep mode + name: VREFLPEN + - bit_offset: 16 + bit_size: 1 + description: RTC APB Clock Enable During CSleep Mode + name: RTCAPBLPEN + - bit_offset: 21 + bit_size: 1 + description: SAI4 Peripheral Clocks Enable During CSleep Mode + name: SAI4LPEN +fieldset/APB4RSTR: + description: RCC APB4 Peripheral Reset Register + fields: + - bit_offset: 1 + bit_size: 1 + description: SYSCFG block reset + name: SYSCFGRST + - bit_offset: 3 + bit_size: 1 + description: LPUART1 block reset + name: LPUART1RST + - bit_offset: 5 + bit_size: 1 + description: SPI6 block reset + name: SPI6RST + - bit_offset: 7 + bit_size: 1 + description: I2C4 block reset + name: I2C4RST + - bit_offset: 9 + bit_size: 1 + description: LPTIM2 block reset + name: LPTIM2RST + - bit_offset: 10 + bit_size: 1 + description: LPTIM3 block reset + name: LPTIM3RST + - bit_offset: 11 + bit_size: 1 + description: LPTIM4 block reset + name: LPTIM4RST + - bit_offset: 12 + bit_size: 1 + description: LPTIM5 block reset + name: LPTIM5RST + - bit_offset: 14 + bit_size: 1 + description: COMP12 Blocks Reset + name: COMP12RST + - bit_offset: 15 + bit_size: 1 + description: VREF block reset + name: VREFRST + - bit_offset: 21 + bit_size: 1 + description: SAI4 block reset + name: SAI4RST +fieldset/BDCR: + description: RCC Backup Domain Control Register + fields: + - bit_offset: 0 + bit_size: 1 + description: LSE oscillator enabled + name: LSEON + - bit_offset: 1 + bit_size: 1 + description: LSE oscillator ready + enum_read: LSERDYR + name: LSERDY + - bit_offset: 2 + bit_size: 1 + description: LSE oscillator bypass + enum: LSEBYP + name: LSEBYP + - bit_offset: 3 + bit_size: 2 + description: LSE oscillator driving capability + enum: LSEDRV + name: LSEDRV + - bit_offset: 5 + bit_size: 1 + description: LSE clock security system enable + name: LSECSSON + - bit_offset: 6 + bit_size: 1 + description: LSE clock security system failure detection + enum_read: LSECSSDR + name: LSECSSD + - bit_offset: 8 + bit_size: 2 + description: RTC clock source selection + enum: RTCSEL + name: RTCSEL + - bit_offset: 15 + bit_size: 1 + description: RTC clock enable + name: RTCEN + - bit_offset: 16 + bit_size: 1 + description: VSwitch domain software reset + name: BDRST +fieldset/C1_AHB1ENR: + description: RCC AHB1 Clock Register + fields: + - bit_offset: 0 + bit_size: 1 + description: DMA1 Clock Enable + name: DMA1EN + - bit_offset: 1 + bit_size: 1 + description: DMA2 Clock Enable + name: DMA2EN + - bit_offset: 5 + bit_size: 1 + description: ADC1/2 Peripheral Clocks Enable + name: ADC12EN + - bit_offset: 15 + bit_size: 1 + description: Ethernet MAC bus interface Clock Enable + name: ETH1MACEN + - bit_offset: 16 + bit_size: 1 + description: Ethernet Transmission Clock Enable + name: ETH1TXEN + - bit_offset: 17 + bit_size: 1 + description: Ethernet Reception Clock Enable + name: ETH1RXEN + - bit_offset: 25 + bit_size: 1 + description: USB1OTG Peripheral Clocks Enable + name: USB1OTGEN + - bit_offset: 26 + bit_size: 1 + description: USB_PHY1 Clocks Enable + name: USB1ULPIEN + - bit_offset: 27 + bit_size: 1 + description: USB2OTG Peripheral Clocks Enable + name: USB2OTGEN + - bit_offset: 28 + bit_size: 1 + description: USB_PHY2 Clocks Enable + name: USB2ULPIEN + - bit_offset: 14 + bit_size: 1 + description: ART Clock Enable + name: ARTEN +fieldset/C1_AHB1LPENR: + description: RCC AHB1 Sleep Clock Register + fields: + - bit_offset: 0 + bit_size: 1 + description: DMA1 Clock Enable During CSleep Mode + name: DMA1LPEN + - bit_offset: 1 + bit_size: 1 + description: DMA2 Clock Enable During CSleep Mode + name: DMA2LPEN + - bit_offset: 5 + bit_size: 1 + description: ADC1/2 Peripheral Clocks Enable During CSleep Mode + name: ADC12LPEN + - bit_offset: 15 + bit_size: 1 + description: Ethernet MAC bus interface Clock Enable During CSleep Mode + name: ETH1MACLPEN + - bit_offset: 16 + bit_size: 1 + description: Ethernet Transmission Clock Enable During CSleep Mode + name: ETH1TXLPEN + - bit_offset: 17 + bit_size: 1 + description: Ethernet Reception Clock Enable During CSleep Mode + name: ETH1RXLPEN + - bit_offset: 25 + bit_size: 1 + description: USB1OTG peripheral clock enable during CSleep mode + name: USB1OTGLPEN + - bit_offset: 26 + bit_size: 1 + description: USB_PHY1 clock enable during CSleep mode + name: USB1ULPILPEN + - bit_offset: 27 + bit_size: 1 + description: USB2OTG peripheral clock enable during CSleep mode + name: USB2OTGLPEN + - bit_offset: 28 + bit_size: 1 + description: USB_PHY2 clocks enable during CSleep mode + name: USB2ULPILPEN + - bit_offset: 14 + bit_size: 1 + description: ART Clock Enable During CSleep Mode + name: ARTLPEN +fieldset/C1_AHB2ENR: + description: RCC AHB2 Clock Register + fields: + - bit_offset: 0 + bit_size: 1 + description: DCMI peripheral clock + name: DCMIEN + - bit_offset: 4 + bit_size: 1 + description: CRYPT peripheral clock enable + name: CRYPTEN + - bit_offset: 5 + bit_size: 1 + description: HASH peripheral clock enable + name: HASHEN + - bit_offset: 6 + bit_size: 1 + description: RNG peripheral clocks enable + name: RNGEN + - bit_offset: 9 + bit_size: 1 + description: SDMMC2 and SDMMC2 delay clock enable + name: SDMMC2EN + - bit_offset: 29 + bit_size: 1 + description: SRAM1 block enable + name: SRAM1EN + - bit_offset: 30 + bit_size: 1 + description: SRAM2 block enable + name: SRAM2EN + - bit_offset: 31 + bit_size: 1 + description: SRAM3 block enable + name: SRAM3EN +fieldset/C1_AHB2LPENR: + description: RCC AHB2 Sleep Clock Register + fields: + - bit_offset: 0 + bit_size: 1 + description: DCMI peripheral clock enable during csleep mode + name: DCMILPEN + - bit_offset: 4 + bit_size: 1 + description: CRYPT peripheral clock enable during CSleep mode + name: CRYPTLPEN + - bit_offset: 5 + bit_size: 1 + description: HASH peripheral clock enable during CSleep mode + name: HASHLPEN + - bit_offset: 6 + bit_size: 1 + description: RNG peripheral clock enable during CSleep mode + name: RNGLPEN + - bit_offset: 9 + bit_size: 1 + description: SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode + name: SDMMC2LPEN + - bit_offset: 29 + bit_size: 1 + description: SRAM1 Clock Enable During CSleep Mode + name: SRAM1LPEN + - bit_offset: 30 + bit_size: 1 + description: SRAM2 Clock Enable During CSleep Mode + name: SRAM2LPEN + - bit_offset: 31 + bit_size: 1 + description: SRAM3 Clock Enable During CSleep Mode + name: SRAM3LPEN +fieldset/C1_AHB3ENR: + description: RCC AHB3 Clock Register + fields: + - bit_offset: 0 + bit_size: 1 + description: MDMA Peripheral Clock Enable + name: MDMAEN + - bit_offset: 4 + bit_size: 1 + description: DMA2D Peripheral Clock Enable + name: DMA2DEN + - bit_offset: 5 + bit_size: 1 + description: JPGDEC Peripheral Clock Enable + name: JPGDECEN + - bit_offset: 12 + bit_size: 1 + description: FMC Peripheral Clocks Enable + name: FMCEN + - bit_offset: 14 + bit_size: 1 + description: QUADSPI and QUADSPI Delay Clock Enable + name: QSPIEN + - bit_offset: 16 + bit_size: 1 + description: SDMMC1 and SDMMC1 Delay Clock Enable + name: SDMMC1EN +fieldset/C1_AHB3LPENR: + description: RCC AHB3 Sleep Clock Register + fields: + - bit_offset: 0 + bit_size: 1 + description: MDMA Clock Enable During CSleep Mode + name: MDMALPEN + - bit_offset: 4 + bit_size: 1 + description: DMA2D Clock Enable During CSleep Mode + name: DMA2DLPEN + - bit_offset: 5 + bit_size: 1 + description: JPGDEC Clock Enable During CSleep Mode + name: JPGDECLPEN + - bit_offset: 8 + bit_size: 1 + description: Flash interface clock enable during csleep mode + name: FLASHPREN + - bit_offset: 12 + bit_size: 1 + description: FMC Peripheral Clocks Enable During CSleep Mode + name: FMCLPEN + - bit_offset: 14 + bit_size: 1 + description: QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode + name: QSPILPEN + - bit_offset: 16 + bit_size: 1 + description: SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode + name: SDMMC1LPEN + - bit_offset: 28 + bit_size: 1 + description: D1DTCM1 Block Clock Enable During CSleep mode + name: D1DTCM1LPEN + - bit_offset: 29 + bit_size: 1 + description: D1 DTCM2 Block Clock Enable During CSleep mode + name: DTCM2LPEN + - bit_offset: 30 + bit_size: 1 + description: D1ITCM Block Clock Enable During CSleep mode + name: ITCMLPEN + - bit_offset: 31 + bit_size: 1 + description: AXISRAM Block Clock Enable During CSleep mode + name: AXISRAMLPEN +fieldset/C1_AHB4ENR: + description: RCC AHB4 Clock Register + fields: + - bit_offset: 0 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOAEN + - bit_offset: 1 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOBEN + - bit_offset: 2 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOCEN + - bit_offset: 3 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIODEN + - bit_offset: 4 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOEEN + - bit_offset: 5 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOFEN + - bit_offset: 6 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOGEN + - bit_offset: 7 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOHEN + - bit_offset: 8 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOIEN + - bit_offset: 9 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOJEN + - bit_offset: 10 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOKEN + - bit_offset: 19 + bit_size: 1 + description: CRC peripheral clock enable + name: CRCEN + - bit_offset: 21 + bit_size: 1 + description: BDMA and DMAMUX2 Clock Enable + name: BDMAEN + - bit_offset: 24 + bit_size: 1 + description: ADC3 Peripheral Clocks Enable + name: ADC3EN + - bit_offset: 25 + bit_size: 1 + description: HSEM peripheral clock enable + name: HSEMEN + - bit_offset: 28 + bit_size: 1 + description: Backup RAM Clock Enable + name: BKPRAMEN +fieldset/C1_AHB4LPENR: + description: RCC AHB4 Sleep Clock Register + fields: + - bit_offset: 0 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOALPEN + - bit_offset: 1 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOBLPEN + - bit_offset: 2 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOCLPEN + - bit_offset: 3 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIODLPEN + - bit_offset: 4 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOELPEN + - bit_offset: 5 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOFLPEN + - bit_offset: 6 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOGLPEN + - bit_offset: 7 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOHLPEN + - bit_offset: 8 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOILPEN + - bit_offset: 9 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOJLPEN + - bit_offset: 10 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOKLPEN + - bit_offset: 19 + bit_size: 1 + description: CRC peripheral clock enable during CSleep mode + name: CRCLPEN + - bit_offset: 21 + bit_size: 1 + description: BDMA Clock Enable During CSleep Mode + name: BDMALPEN + - bit_offset: 24 + bit_size: 1 + description: ADC3 Peripheral Clocks Enable During CSleep Mode + name: ADC3LPEN + - bit_offset: 28 + bit_size: 1 + description: Backup RAM Clock Enable During CSleep Mode + name: BKPRAMLPEN + - bit_offset: 29 + bit_size: 1 + description: SRAM4 Clock Enable During CSleep Mode + name: SRAM4LPEN +fieldset/C1_APB1HENR: + description: RCC APB1 Clock Register + fields: + - bit_offset: 1 + bit_size: 1 + description: Clock Recovery System peripheral clock enable + name: CRSEN + - bit_offset: 2 + bit_size: 1 + description: SWPMI Peripheral Clocks Enable + name: SWPEN + - bit_offset: 4 + bit_size: 1 + description: OPAMP peripheral clock enable + name: OPAMPEN + - bit_offset: 5 + bit_size: 1 + description: MDIOS peripheral clock enable + name: MDIOSEN + - bit_offset: 8 + bit_size: 1 + description: FDCAN Peripheral Clocks Enable + name: FDCANEN +fieldset/C1_APB1HLPENR: + description: RCC APB1 High Sleep Clock Register + fields: + - bit_offset: 1 + bit_size: 1 + description: Clock Recovery System peripheral clock enable during CSleep mode + name: CRSLPEN + - bit_offset: 2 + bit_size: 1 + description: SWPMI Peripheral Clocks Enable During CSleep Mode + name: SWPLPEN + - bit_offset: 4 + bit_size: 1 + description: OPAMP peripheral clock enable during CSleep mode + name: OPAMPLPEN + - bit_offset: 5 + bit_size: 1 + description: MDIOS peripheral clock enable during CSleep mode + name: MDIOSLPEN + - bit_offset: 8 + bit_size: 1 + description: FDCAN Peripheral Clocks Enable During CSleep Mode + name: FDCANLPEN +fieldset/C1_APB1LENR: + description: RCC APB1 Clock Register + fields: + - bit_offset: 0 + bit_size: 1 + description: TIM peripheral clock enable + name: TIM2EN + - bit_offset: 1 + bit_size: 1 + description: TIM peripheral clock enable + name: TIM3EN + - bit_offset: 2 + bit_size: 1 + description: TIM peripheral clock enable + name: TIM4EN + - bit_offset: 3 + bit_size: 1 + description: TIM peripheral clock enable + name: TIM5EN + - bit_offset: 4 + bit_size: 1 + description: TIM peripheral clock enable + name: TIM6EN + - bit_offset: 5 + bit_size: 1 + description: TIM peripheral clock enable + name: TIM7EN + - bit_offset: 6 + bit_size: 1 + description: TIM peripheral clock enable + name: TIM12EN + - bit_offset: 7 + bit_size: 1 + description: TIM peripheral clock enable + name: TIM13EN + - bit_offset: 8 + bit_size: 1 + description: TIM peripheral clock enable + name: TIM14EN + - bit_offset: 9 + bit_size: 1 + description: LPTIM1 Peripheral Clocks Enable + name: LPTIM1EN + - bit_offset: 14 + bit_size: 1 + description: SPI2 Peripheral Clocks Enable + name: SPI2EN + - bit_offset: 15 + bit_size: 1 + description: SPI3 Peripheral Clocks Enable + name: SPI3EN + - bit_offset: 16 + bit_size: 1 + description: SPDIFRX Peripheral Clocks Enable + name: SPDIFRXEN + - bit_offset: 17 + bit_size: 1 + description: USART2 Peripheral Clocks Enable + name: USART2EN + - bit_offset: 18 + bit_size: 1 + description: USART3 Peripheral Clocks Enable + name: USART3EN + - bit_offset: 19 + bit_size: 1 + description: UART4 Peripheral Clocks Enable + name: UART4EN + - bit_offset: 20 + bit_size: 1 + description: UART5 Peripheral Clocks Enable + name: UART5EN + - bit_offset: 21 + bit_size: 1 + description: I2C1 Peripheral Clocks Enable + name: I2C1EN + - bit_offset: 22 + bit_size: 1 + description: I2C2 Peripheral Clocks Enable + name: I2C2EN + - bit_offset: 23 + bit_size: 1 + description: I2C3 Peripheral Clocks Enable + name: I2C3EN + - bit_offset: 27 + bit_size: 1 + description: HDMI-CEC peripheral clock enable + name: CECEN + - bit_offset: 29 + bit_size: 1 + description: DAC1&2 peripheral clock enable + name: DAC12EN + - bit_offset: 30 + bit_size: 1 + description: UART7 Peripheral Clocks Enable + name: UART7EN + - bit_offset: 31 + bit_size: 1 + description: UART8 Peripheral Clocks Enable + name: UART8EN + - bit_offset: 11 + bit_size: 1 + description: WWDG2 peripheral clock enable + name: WWDG2EN +fieldset/C1_APB1LLPENR: + description: RCC APB1 Low Sleep Clock Register + fields: + - bit_offset: 0 + bit_size: 1 + description: TIM2 peripheral clock enable during CSleep mode + name: TIM2LPEN + - bit_offset: 1 + bit_size: 1 + description: TIM3 peripheral clock enable during CSleep mode + name: TIM3LPEN + - bit_offset: 2 + bit_size: 1 + description: TIM4 peripheral clock enable during CSleep mode + name: TIM4LPEN + - bit_offset: 3 + bit_size: 1 + description: TIM5 peripheral clock enable during CSleep mode + name: TIM5LPEN + - bit_offset: 4 + bit_size: 1 + description: TIM6 peripheral clock enable during CSleep mode + name: TIM6LPEN + - bit_offset: 5 + bit_size: 1 + description: TIM7 peripheral clock enable during CSleep mode + name: TIM7LPEN + - bit_offset: 6 + bit_size: 1 + description: TIM12 peripheral clock enable during CSleep mode + name: TIM12LPEN + - bit_offset: 7 + bit_size: 1 + description: TIM13 peripheral clock enable during CSleep mode + name: TIM13LPEN + - bit_offset: 8 + bit_size: 1 + description: TIM14 peripheral clock enable during CSleep mode + name: TIM14LPEN + - bit_offset: 9 + bit_size: 1 + description: LPTIM1 Peripheral Clocks Enable During CSleep Mode + name: LPTIM1LPEN + - bit_offset: 14 + bit_size: 1 + description: SPI2 Peripheral Clocks Enable During CSleep Mode + name: SPI2LPEN + - bit_offset: 15 + bit_size: 1 + description: SPI3 Peripheral Clocks Enable During CSleep Mode + name: SPI3LPEN + - bit_offset: 16 + bit_size: 1 + description: SPDIFRX Peripheral Clocks Enable During CSleep Mode + name: SPDIFRXLPEN + - bit_offset: 17 + bit_size: 1 + description: USART2 Peripheral Clocks Enable During CSleep Mode + name: USART2LPEN + - bit_offset: 18 + bit_size: 1 + description: USART3 Peripheral Clocks Enable During CSleep Mode + name: USART3LPEN + - bit_offset: 19 + bit_size: 1 + description: UART4 Peripheral Clocks Enable During CSleep Mode + name: UART4LPEN + - bit_offset: 20 + bit_size: 1 + description: UART5 Peripheral Clocks Enable During CSleep Mode + name: UART5LPEN + - bit_offset: 21 + bit_size: 1 + description: I2C1 Peripheral Clocks Enable During CSleep Mode + name: I2C1LPEN + - bit_offset: 22 + bit_size: 1 + description: I2C2 Peripheral Clocks Enable During CSleep Mode + name: I2C2LPEN + - bit_offset: 23 + bit_size: 1 + description: I2C3 Peripheral Clocks Enable During CSleep Mode + name: I2C3LPEN + - bit_offset: 27 + bit_size: 1 + description: HDMI-CEC Peripheral Clocks Enable During CSleep Mode + name: CECLPEN + - bit_offset: 29 + bit_size: 1 + description: DAC1/2 peripheral clock enable during CSleep mode + name: DAC12LPEN + - bit_offset: 30 + bit_size: 1 + description: UART7 Peripheral Clocks Enable During CSleep Mode + name: UART7LPEN + - bit_offset: 31 + bit_size: 1 + description: UART8 Peripheral Clocks Enable During CSleep Mode + name: UART8LPEN + - bit_offset: 11 + bit_size: 1 + description: WWDG2 peripheral Clocks Enable During CSleep Mode + name: WWDG2LPEN +fieldset/C1_APB2ENR: + description: RCC APB2 Clock Register + fields: + - bit_offset: 0 + bit_size: 1 + description: TIM1 peripheral clock enable + name: TIM1EN + - bit_offset: 1 + bit_size: 1 + description: TIM8 peripheral clock enable + name: TIM8EN + - bit_offset: 4 + bit_size: 1 + description: USART1 Peripheral Clocks Enable + name: USART1EN + - bit_offset: 5 + bit_size: 1 + description: USART6 Peripheral Clocks Enable + name: USART6EN + - bit_offset: 12 + bit_size: 1 + description: SPI1 Peripheral Clocks Enable + name: SPI1EN + - bit_offset: 13 + bit_size: 1 + description: SPI4 Peripheral Clocks Enable + name: SPI4EN + - bit_offset: 16 + bit_size: 1 + description: TIM15 peripheral clock enable + name: TIM15EN + - bit_offset: 17 + bit_size: 1 + description: TIM16 peripheral clock enable + name: TIM16EN + - bit_offset: 18 + bit_size: 1 + description: TIM17 peripheral clock enable + name: TIM17EN + - bit_offset: 20 + bit_size: 1 + description: SPI5 Peripheral Clocks Enable + name: SPI5EN + - bit_offset: 22 + bit_size: 1 + description: SAI1 Peripheral Clocks Enable + name: SAI1EN + - bit_offset: 23 + bit_size: 1 + description: SAI2 Peripheral Clocks Enable + name: SAI2EN + - bit_offset: 24 + bit_size: 1 + description: SAI3 Peripheral Clocks Enable + name: SAI3EN + - bit_offset: 28 + bit_size: 1 + description: DFSDM1 Peripheral Clocks Enable + name: DFSDM1EN + - bit_offset: 29 + bit_size: 1 + description: HRTIM peripheral clock enable + name: HRTIMEN +fieldset/C1_APB2LPENR: + description: RCC APB2 Sleep Clock Register + fields: + - bit_offset: 0 + bit_size: 1 + description: TIM1 peripheral clock enable during CSleep mode + name: TIM1LPEN + - bit_offset: 1 + bit_size: 1 + description: TIM8 peripheral clock enable during CSleep mode + name: TIM8LPEN + - bit_offset: 4 + bit_size: 1 + description: USART1 Peripheral Clocks Enable During CSleep Mode + name: USART1LPEN + - bit_offset: 5 + bit_size: 1 + description: USART6 Peripheral Clocks Enable During CSleep Mode + name: USART6LPEN + - bit_offset: 12 + bit_size: 1 + description: SPI1 Peripheral Clocks Enable During CSleep Mode + name: SPI1LPEN + - bit_offset: 13 + bit_size: 1 + description: SPI4 Peripheral Clocks Enable During CSleep Mode + name: SPI4LPEN + - bit_offset: 16 + bit_size: 1 + description: TIM15 peripheral clock enable during CSleep mode + name: TIM15LPEN + - bit_offset: 17 + bit_size: 1 + description: TIM16 peripheral clock enable during CSleep mode + name: TIM16LPEN + - bit_offset: 18 + bit_size: 1 + description: TIM17 peripheral clock enable during CSleep mode + name: TIM17LPEN + - bit_offset: 20 + bit_size: 1 + description: SPI5 Peripheral Clocks Enable During CSleep Mode + name: SPI5LPEN + - bit_offset: 22 + bit_size: 1 + description: SAI1 Peripheral Clocks Enable During CSleep Mode + name: SAI1LPEN + - bit_offset: 23 + bit_size: 1 + description: SAI2 Peripheral Clocks Enable During CSleep Mode + name: SAI2LPEN + - bit_offset: 24 + bit_size: 1 + description: SAI3 Peripheral Clocks Enable During CSleep Mode + name: SAI3LPEN + - bit_offset: 28 + bit_size: 1 + description: DFSDM1 Peripheral Clocks Enable During CSleep Mode + name: DFSDM1LPEN + - bit_offset: 29 + bit_size: 1 + description: HRTIM peripheral clock enable during CSleep mode + name: HRTIMLPEN +fieldset/C1_APB3ENR: + description: RCC APB3 Clock Register + fields: + - bit_offset: 3 + bit_size: 1 + description: LTDC peripheral clock enable + name: LTDCEN + - bit_offset: 6 + bit_size: 1 + description: WWDG1 Clock Enable + name: WWDG1EN + - bit_offset: 4 + bit_size: 1 + description: DSI Peripheral clocks enable + name: DSIEN +fieldset/C1_APB3LPENR: + description: RCC APB3 Sleep Clock Register + fields: + - bit_offset: 3 + bit_size: 1 + description: LTDC peripheral clock enable during CSleep mode + name: LTDCLPEN + - bit_offset: 6 + bit_size: 1 + description: WWDG1 Clock Enable During CSleep Mode + name: WWDG1LPEN + - bit_offset: 4 + bit_size: 1 + description: DSI Peripheral Clock Enable During CSleep Mode + name: DSILPEN +fieldset/C1_APB4ENR: + description: RCC APB4 Clock Register + fields: + - bit_offset: 1 + bit_size: 1 + description: SYSCFG peripheral clock enable + name: SYSCFGEN + - bit_offset: 3 + bit_size: 1 + description: LPUART1 Peripheral Clocks Enable + name: LPUART1EN + - bit_offset: 5 + bit_size: 1 + description: SPI6 Peripheral Clocks Enable + name: SPI6EN + - bit_offset: 7 + bit_size: 1 + description: I2C4 Peripheral Clocks Enable + name: I2C4EN + - bit_offset: 9 + bit_size: 1 + description: LPTIM2 Peripheral Clocks Enable + name: LPTIM2EN + - bit_offset: 10 + bit_size: 1 + description: LPTIM3 Peripheral Clocks Enable + name: LPTIM3EN + - bit_offset: 11 + bit_size: 1 + description: LPTIM4 Peripheral Clocks Enable + name: LPTIM4EN + - bit_offset: 12 + bit_size: 1 + description: LPTIM5 Peripheral Clocks Enable + name: LPTIM5EN + - bit_offset: 14 + bit_size: 1 + description: COMP1/2 peripheral clock enable + name: COMP12EN + - bit_offset: 15 + bit_size: 1 + description: VREF peripheral clock enable + name: VREFEN + - bit_offset: 16 + bit_size: 1 + description: RTC APB Clock Enable + name: RTCAPBEN + - bit_offset: 21 + bit_size: 1 + description: SAI4 Peripheral Clocks Enable + name: SAI4EN +fieldset/C1_APB4LPENR: + description: RCC APB4 Sleep Clock Register + fields: + - bit_offset: 1 + bit_size: 1 + description: SYSCFG peripheral clock enable during CSleep mode + name: SYSCFGLPEN + - bit_offset: 3 + bit_size: 1 + description: LPUART1 Peripheral Clocks Enable During CSleep Mode + name: LPUART1LPEN + - bit_offset: 5 + bit_size: 1 + description: SPI6 Peripheral Clocks Enable During CSleep Mode + name: SPI6LPEN + - bit_offset: 7 + bit_size: 1 + description: I2C4 Peripheral Clocks Enable During CSleep Mode + name: I2C4LPEN + - bit_offset: 9 + bit_size: 1 + description: LPTIM2 Peripheral Clocks Enable During CSleep Mode + name: LPTIM2LPEN + - bit_offset: 10 + bit_size: 1 + description: LPTIM3 Peripheral Clocks Enable During CSleep Mode + name: LPTIM3LPEN + - bit_offset: 11 + bit_size: 1 + description: LPTIM4 Peripheral Clocks Enable During CSleep Mode + name: LPTIM4LPEN + - bit_offset: 12 + bit_size: 1 + description: LPTIM5 Peripheral Clocks Enable During CSleep Mode + name: LPTIM5LPEN + - bit_offset: 14 + bit_size: 1 + description: COMP1/2 peripheral clock enable during CSleep mode + name: COMP12LPEN + - bit_offset: 15 + bit_size: 1 + description: VREF peripheral clock enable during CSleep mode + name: VREFLPEN + - bit_offset: 16 + bit_size: 1 + description: RTC APB Clock Enable During CSleep Mode + name: RTCAPBLPEN + - bit_offset: 21 + bit_size: 1 + description: SAI4 Peripheral Clocks Enable During CSleep Mode + name: SAI4LPEN +fieldset/C1_RSR: + description: RCC Reset Status Register + fields: + - bit_offset: 16 + bit_size: 1 + description: Remove reset flag + enum: C_RSR_RMVF + name: RMVF + - bit_offset: 17 + bit_size: 1 + description: CPU reset flag + enum_read: C_RSR_CPURSTFR + name: CPURSTF + - bit_offset: 19 + bit_size: 1 + description: D1 domain power switch reset flag + enum_read: C_RSR_CPURSTFR + name: D1RSTF + - bit_offset: 20 + bit_size: 1 + description: D2 domain power switch reset flag + enum_read: C_RSR_CPURSTFR + name: D2RSTF + - bit_offset: 21 + bit_size: 1 + description: BOR reset flag + enum_read: C_RSR_CPURSTFR + name: BORRSTF + - bit_offset: 22 + bit_size: 1 + description: Pin reset flag (NRST) + enum_read: C_RSR_CPURSTFR + name: PINRSTF + - bit_offset: 23 + bit_size: 1 + description: POR/PDR reset flag + enum_read: C_RSR_CPURSTFR + name: PORRSTF + - bit_offset: 24 + bit_size: 1 + description: System reset from CPU reset flag + enum_read: C_RSR_CPURSTFR + name: SFTRSTF + - bit_offset: 26 + bit_size: 1 + description: Independent Watchdog reset flag + enum_read: C_RSR_CPURSTFR + name: IWDG1RSTF + - bit_offset: 28 + bit_size: 1 + description: Window Watchdog reset flag + enum_read: C_RSR_CPURSTFR + name: WWDG1RSTF + - bit_offset: 30 + bit_size: 1 + description: Reset due to illegal D1 DStandby or CPU CStop flag + enum_read: C_RSR_CPURSTFR + name: LPWRRSTF +fieldset/CFGR: + description: RCC Clock Configuration Register + fields: + - bit_offset: 0 + bit_size: 3 + description: System clock switch + enum: SW + name: SW + - bit_offset: 3 + bit_size: 3 + description: System clock switch status + enum_read: SWSR + name: SWS + - bit_offset: 6 + bit_size: 1 + description: System clock selection after a wake up from system Stop + enum: STOPWUCK + name: STOPWUCK + - bit_offset: 7 + bit_size: 1 + description: Kernel clock selection after a wake up from system Stop + enum: STOPWUCK + name: STOPKERWUCK + - bit_offset: 8 + bit_size: 6 + description: HSE division factor for RTC clock + name: RTCPRE + - bit_offset: 14 + bit_size: 1 + description: High Resolution Timer clock prescaler selection + enum: HRTIMSEL + name: HRTIMSEL + - bit_offset: 15 + bit_size: 1 + description: Timers clocks prescaler selection + enum: TIMPRE + name: TIMPRE + - bit_offset: 18 + bit_size: 4 + description: MCO1 prescaler + name: MCO1PRE + - bit_offset: 22 + bit_size: 3 + description: Micro-controller clock output 1 + enum: MCO1 + name: MCO1 + - bit_offset: 25 + bit_size: 4 + description: MCO2 prescaler + name: MCO2PRE + - bit_offset: 29 + bit_size: 3 + description: Micro-controller clock output 2 + enum: MCO2 + name: MCO2 +fieldset/CICR: + description: RCC Clock Source Interrupt Clear Register + fields: + - bit_offset: 0 + bit_size: 1 + description: LSI ready Interrupt Clear + enum: LSIRDYC + name: LSIRDYC + - bit_offset: 1 + bit_size: 1 + description: LSE ready Interrupt Clear + enum: LSIRDYC + name: LSERDYC + - bit_offset: 2 + bit_size: 1 + description: HSI ready Interrupt Clear + enum: LSIRDYC + name: HSIRDYC + - bit_offset: 3 + bit_size: 1 + description: HSE ready Interrupt Clear + enum: LSIRDYC + name: HSERDYC + - bit_offset: 4 + bit_size: 1 + description: CSI ready Interrupt Clear + name: HSE_ready_Interrupt_Clear + - bit_offset: 5 + bit_size: 1 + description: RC48 ready Interrupt Clear + enum: LSIRDYC + name: HSI48RDYC + - array: + len: 3 + stride: 1 + bit_offset: 6 + bit_size: 1 + description: PLL1 ready Interrupt Clear + enum: LSIRDYC + name: PLLRDYC + - bit_offset: 9 + bit_size: 1 + description: LSE clock security system Interrupt Clear + enum: LSIRDYC + name: LSECSSC + - bit_offset: 10 + bit_size: 1 + description: HSE clock security system Interrupt Clear + enum: LSIRDYC + name: HSECSSC +fieldset/CIER: + description: RCC Clock Source Interrupt Enable Register + fields: + - bit_offset: 0 + bit_size: 1 + description: LSI ready Interrupt Enable + enum: LSIRDYIE + name: LSIRDYIE + - bit_offset: 1 + bit_size: 1 + description: LSE ready Interrupt Enable + enum: LSIRDYIE + name: LSERDYIE + - bit_offset: 2 + bit_size: 1 + description: HSI ready Interrupt Enable + enum: LSIRDYIE + name: HSIRDYIE + - bit_offset: 3 + bit_size: 1 + description: HSE ready Interrupt Enable + enum: LSIRDYIE + name: HSERDYIE + - bit_offset: 4 + bit_size: 1 + description: CSI ready Interrupt Enable + enum: LSIRDYIE + name: CSIRDYIE + - bit_offset: 5 + bit_size: 1 + description: RC48 ready Interrupt Enable + enum: LSIRDYIE + name: HSI48RDYIE + - array: + len: 3 + stride: 1 + bit_offset: 6 + bit_size: 1 + description: PLL1 ready Interrupt Enable + enum: LSIRDYIE + name: PLLRDYIE + - bit_offset: 9 + bit_size: 1 + description: LSE clock security system Interrupt Enable + enum: LSIRDYIE + name: LSECSSIE +fieldset/CIFR: + description: RCC Clock Source Interrupt Flag Register + fields: + - bit_offset: 0 + bit_size: 1 + description: LSI ready Interrupt Flag + name: LSIRDYF + - bit_offset: 1 + bit_size: 1 + description: LSE ready Interrupt Flag + name: LSERDYF + - bit_offset: 2 + bit_size: 1 + description: HSI ready Interrupt Flag + name: HSIRDYF + - bit_offset: 3 + bit_size: 1 + description: HSE ready Interrupt Flag + name: HSERDYF + - bit_offset: 4 + bit_size: 1 + description: CSI ready Interrupt Flag + name: CSIRDY + - bit_offset: 5 + bit_size: 1 + description: RC48 ready Interrupt Flag + name: HSI48RDYF + - array: + len: 3 + stride: 1 + bit_offset: 6 + bit_size: 1 + description: PLL1 ready Interrupt Flag + name: PLLRDYF + - bit_offset: 9 + bit_size: 1 + description: LSE clock security system Interrupt Flag + name: LSECSSF + - bit_offset: 10 + bit_size: 1 + description: HSE clock security system Interrupt Flag + name: HSECSSF +fieldset/CR: + description: clock control register + fields: + - bit_offset: 0 + bit_size: 1 + description: Internal high-speed clock enable + name: HSION + - bit_offset: 1 + bit_size: 1 + description: High Speed Internal clock enable in Stop mode + name: HSIKERON + - bit_offset: 2 + bit_size: 1 + description: HSI clock ready flag + enum_read: HSIRDYR + name: HSIRDY + - bit_offset: 3 + bit_size: 2 + description: HSI clock divider + enum: HSIDIV + name: HSIDIV + - bit_offset: 5 + bit_size: 1 + description: HSI divider flag + enum_read: HSIDIVFR + name: HSIDIVF + - bit_offset: 7 + bit_size: 1 + description: CSI clock enable + name: CSION + - bit_offset: 8 + bit_size: 1 + description: CSI clock ready flag + enum_read: HSIRDYR + name: CSIRDY + - bit_offset: 9 + bit_size: 1 + description: CSI clock enable in Stop mode + name: CSIKERON + - bit_offset: 12 + bit_size: 1 + description: RC48 clock enable + name: HSI48ON + - bit_offset: 13 + bit_size: 1 + description: RC48 clock ready flag + enum_read: HSIRDYR + name: HSI48RDY + - bit_offset: 14 + bit_size: 1 + description: D1 domain clocks ready flag + enum_read: HSIRDYR + name: D1CKRDY + - bit_offset: 15 + bit_size: 1 + description: D2 domain clocks ready flag + enum_read: HSIRDYR + name: D2CKRDY + - bit_offset: 16 + bit_size: 1 + description: HSE clock enable + name: HSEON + - bit_offset: 17 + bit_size: 1 + description: HSE clock ready flag + enum_read: HSIRDYR + name: HSERDY + - bit_offset: 18 + bit_size: 1 + description: HSE clock bypass + enum: HSEBYP + name: HSEBYP + - bit_offset: 19 + bit_size: 1 + description: HSE Clock Security System enable + name: HSECSSON + - array: + len: 3 + stride: 2 + bit_offset: 24 + bit_size: 1 + description: PLL1 enable + name: PLLON + - array: + len: 3 + stride: 2 + bit_offset: 25 + bit_size: 1 + description: PLL1 clock ready flag + enum_read: HSIRDYR + name: PLLRDY +fieldset/CRRCR: + description: RCC Clock Recovery RC Register + fields: + - bit_offset: 0 + bit_size: 10 + description: Internal RC 48 MHz clock calibration + name: HSI48CAL +fieldset/CSICFGR: + description: RCC CSI configuration register + fields: + - bit_offset: 0 + bit_size: 9 + description: CSI clock calibration + name: CSICAL + - bit_offset: 24 + bit_size: 6 + description: CSI clock trimming + name: CSITRIM +fieldset/CSR: + description: RCC Clock Control and Status Register + fields: + - bit_offset: 0 + bit_size: 1 + description: LSI oscillator enable + name: LSION + - bit_offset: 1 + bit_size: 1 + description: LSI oscillator ready + enum_read: LSIRDYR + name: LSIRDY +fieldset/D1CCIPR: + description: RCC Domain 1 Kernel Clock Configuration Register + fields: + - bit_offset: 0 + bit_size: 2 + description: FMC kernel clock source selection + enum: FMCSEL + name: FMCSEL + - bit_offset: 4 + bit_size: 2 + description: QUADSPI kernel clock source selection + enum: FMCSEL + name: QSPISEL + - bit_offset: 16 + bit_size: 1 + description: SDMMC kernel clock source selection + enum: SDMMCSEL + name: SDMMCSEL + - bit_offset: 28 + bit_size: 2 + description: per_ck clock source selection + enum: CKPERSEL + name: CKPERSEL + - bit_offset: 8 + bit_size: 1 + description: kernel clock source selection + name: DSISEL +fieldset/D1CFGR: + description: RCC Domain 1 Clock Configuration Register + fields: + - bit_offset: 0 + bit_size: 4 + description: D1 domain AHB prescaler + enum: HPRE + name: HPRE + - bit_offset: 4 + bit_size: 3 + description: D1 domain APB3 prescaler + enum: DPPRE + name: D1PPRE + - bit_offset: 8 + bit_size: 4 + description: D1 domain Core prescaler + enum: HPRE + name: D1CPRE +fieldset/D2CCIP1R: + description: RCC Domain 2 Kernel Clock Configuration Register + fields: + - bit_offset: 0 + bit_size: 3 + description: SAI1 and DFSDM1 kernel Aclk clock source selection + enum: SAISEL + name: SAI1SEL + - bit_offset: 6 + bit_size: 3 + description: SAI2 and SAI3 kernel clock source selection + enum: SAISEL + name: SAI23SEL + - bit_offset: 12 + bit_size: 3 + description: SPI/I2S1,2 and 3 kernel clock source selection + enum: SAISEL + name: SPI123SEL + - bit_offset: 16 + bit_size: 3 + description: SPI4 and 5 kernel clock source selection + enum: SPI45SEL + name: SPI45SEL + - bit_offset: 20 + bit_size: 2 + description: SPDIFRX kernel clock source selection + enum: SPDIFSEL + name: SPDIFSEL + - bit_offset: 24 + bit_size: 1 + description: DFSDM1 kernel Clk clock source selection + enum: DFSDMSEL + name: DFSDM1SEL + - bit_offset: 28 + bit_size: 2 + description: FDCAN kernel clock source selection + enum: FDCANSEL + name: FDCANSEL + - bit_offset: 31 + bit_size: 1 + description: SWPMI kernel clock source selection + enum: SWPSEL + name: SWPSEL +fieldset/D2CCIP2R: + description: RCC Domain 2 Kernel Clock Configuration Register + fields: + - bit_offset: 0 + bit_size: 3 + description: USART2/3, UART4,5, 7/8 (APB1) kernel clock source selection + enum: USART234578SEL + name: USART234578SEL + - bit_offset: 3 + bit_size: 3 + description: USART1 and 6 kernel clock source selection + enum: USART16SEL + name: USART16SEL + - bit_offset: 8 + bit_size: 2 + description: RNG kernel clock source selection + enum: RNGSEL + name: RNGSEL + - bit_offset: 12 + bit_size: 2 + description: I2C1,2,3 kernel clock source selection + enum: I2C123SEL + name: I2C123SEL + - bit_offset: 20 + bit_size: 2 + description: USBOTG 1 and 2 kernel clock source selection + enum: USBSEL + name: USBSEL + - bit_offset: 22 + bit_size: 2 + description: HDMI-CEC kernel clock source selection + enum: CECSEL + name: CECSEL + - bit_offset: 28 + bit_size: 3 + description: LPTIM1 kernel clock source selection + enum: LPTIM1SEL + name: LPTIM1SEL +fieldset/D2CFGR: + description: RCC Domain 2 Clock Configuration Register + fields: + - bit_offset: 4 + bit_size: 3 + description: D2 domain APB1 prescaler + enum: DPPRE + name: D2PPRE1 + - bit_offset: 8 + bit_size: 3 + description: D2 domain APB2 prescaler + enum: DPPRE + name: D2PPRE2 +fieldset/D3AMR: + description: RCC D3 Autonomous mode Register + fields: + - bit_offset: 0 + bit_size: 1 + description: BDMA and DMAMUX Autonomous mode enable + name: BDMAAMEN + - bit_offset: 3 + bit_size: 1 + description: LPUART1 Autonomous mode enable + name: LPUART1AMEN + - bit_offset: 5 + bit_size: 1 + description: SPI6 Autonomous mode enable + name: SPI6AMEN + - bit_offset: 7 + bit_size: 1 + description: I2C4 Autonomous mode enable + name: I2C4AMEN + - bit_offset: 9 + bit_size: 1 + description: LPTIM2 Autonomous mode enable + name: LPTIM2AMEN + - bit_offset: 10 + bit_size: 1 + description: LPTIM3 Autonomous mode enable + name: LPTIM3AMEN + - bit_offset: 11 + bit_size: 1 + description: LPTIM4 Autonomous mode enable + name: LPTIM4AMEN + - bit_offset: 12 + bit_size: 1 + description: LPTIM5 Autonomous mode enable + name: LPTIM5AMEN + - bit_offset: 14 + bit_size: 1 + description: COMP12 Autonomous mode enable + name: COMP12AMEN + - bit_offset: 15 + bit_size: 1 + description: VREF Autonomous mode enable + name: VREFAMEN + - bit_offset: 16 + bit_size: 1 + description: RTC Autonomous mode enable + name: RTCAMEN + - bit_offset: 19 + bit_size: 1 + description: CRC Autonomous mode enable + name: CRCAMEN + - bit_offset: 21 + bit_size: 1 + description: SAI4 Autonomous mode enable + name: SAI4AMEN + - bit_offset: 24 + bit_size: 1 + description: ADC3 Autonomous mode enable + name: ADC3AMEN + - bit_offset: 28 + bit_size: 1 + description: Backup RAM Autonomous mode enable + name: BKPRAMAMEN + - bit_offset: 29 + bit_size: 1 + description: SRAM4 Autonomous mode enable + name: SRAM4AMEN + - bit_offset: 28 + bit_size: 1 + description: Backup RAM Autonomous mode enable + name: BKPSRAMAMEN +fieldset/D3CCIPR: + description: RCC Domain 3 Kernel Clock Configuration Register + fields: + - bit_offset: 0 + bit_size: 3 + description: LPUART1 kernel clock source selection + enum: LPUARTSEL + name: LPUART1SEL + - bit_offset: 8 + bit_size: 2 + description: I2C4 kernel clock source selection + enum: I2C4SEL + name: I2C4SEL + - bit_offset: 10 + bit_size: 3 + description: LPTIM2 kernel clock source selection + enum: LPTIM2SEL + name: LPTIM2SEL + - bit_offset: 13 + bit_size: 3 + description: LPTIM3,4,5 kernel clock source selection + enum: LPTIM2SEL + name: LPTIM345SEL + - bit_offset: 16 + bit_size: 2 + description: SAR ADC kernel clock source selection + enum: ADCSEL + name: ADCSEL + - bit_offset: 21 + bit_size: 3 + description: Sub-Block A of SAI4 kernel clock source selection + enum: SAIASEL + name: SAI4ASEL + - bit_offset: 24 + bit_size: 3 + description: Sub-Block B of SAI4 kernel clock source selection + enum: SAIASEL + name: SAI4BSEL + - bit_offset: 28 + bit_size: 3 + description: SPI6 kernel clock source selection + enum: SPI6SEL + name: SPI6SEL +fieldset/D3CFGR: + description: RCC Domain 3 Clock Configuration Register + fields: + - bit_offset: 4 + bit_size: 3 + description: D3 domain APB4 prescaler + enum: DPPRE + name: D3PPRE +fieldset/GCR: + description: RCC Global Control Register + fields: + - bit_offset: 0 + bit_size: 1 + description: WWDG1 reset scope control + enum: WWRSC + name: WW1RSC + - bit_offset: 1 + bit_size: 1 + description: WWDG2 reset scope control + name: WW2RSC + - bit_offset: 2 + bit_size: 1 + description: Force allow CPU1 to boot + name: BOOT_C1 + - bit_offset: 3 + bit_size: 1 + description: Force allow CPU2 to boot + name: BOOT_C2 +fieldset/HSICFGR: + description: RCC HSI configuration register + fields: + - bit_offset: 0 + bit_size: 12 + description: HSI clock calibration + name: HSICAL + - bit_offset: 24 + bit_size: 7 + description: HSI clock trimming + name: HSITRIM +fieldset/ICSCR: + description: RCC Internal Clock Source Calibration Register + fields: + - bit_offset: 0 + bit_size: 12 + description: HSI clock calibration + name: HSICAL + - bit_offset: 12 + bit_size: 6 + description: HSI clock trimming + name: HSITRIM + - bit_offset: 18 + bit_size: 8 + description: CSI clock calibration + name: CSICAL + - bit_offset: 26 + bit_size: 5 + description: CSI clock trimming + name: CSITRIM +fieldset/PLL1DIVR: + description: RCC PLL1 Dividers Configuration Register + fields: + - bit_offset: 0 + bit_size: 9 + description: Multiplication factor for PLL1 VCO + name: DIVN1 + - bit_offset: 9 + bit_size: 7 + description: PLL1 DIVP division factor + enum: DIVP + name: DIVP1 + - bit_offset: 16 + bit_size: 7 + description: PLL1 DIVQ division factor + name: DIVQ1 + - bit_offset: 24 + bit_size: 7 + description: PLL1 DIVR division factor + name: DIVR1 +fieldset/PLL1FRACR: + description: RCC PLL1 Fractional Divider Register + fields: + - bit_offset: 3 + bit_size: 13 + description: Fractional part of the multiplication factor for PLL1 VCO + name: FRACN1 +fieldset/PLL2DIVR: + description: RCC PLL2 Dividers Configuration Register + fields: + - bit_offset: 0 + bit_size: 9 + description: Multiplication factor for PLL1 VCO + name: DIVN2 + - bit_offset: 9 + bit_size: 7 + description: PLL1 DIVP division factor + name: DIVP2 + - bit_offset: 16 + bit_size: 7 + description: PLL1 DIVQ division factor + name: DIVQ2 + - bit_offset: 24 + bit_size: 7 + description: PLL1 DIVR division factor + name: DIVR2 +fieldset/PLL2FRACR: + description: RCC PLL2 Fractional Divider Register + fields: + - bit_offset: 3 + bit_size: 13 + description: Fractional part of the multiplication factor for PLL VCO + name: FRACN2 +fieldset/PLL3DIVR: + description: RCC PLL3 Dividers Configuration Register + fields: + - bit_offset: 0 + bit_size: 9 + description: Multiplication factor for PLL1 VCO + name: DIVN3 + - bit_offset: 9 + bit_size: 7 + description: PLL DIVP division factor + name: DIVP3 + - bit_offset: 16 + bit_size: 7 + description: PLL DIVQ division factor + name: DIVQ3 + - bit_offset: 24 + bit_size: 7 + description: PLL DIVR division factor + name: DIVR3 +fieldset/PLL3FRACR: + description: RCC PLL3 Fractional Divider Register + fields: + - bit_offset: 3 + bit_size: 13 + description: Fractional part of the multiplication factor for PLL3 VCO + name: FRACN3 +fieldset/PLLCFGR: + description: RCC PLLs Configuration Register + fields: + - array: + len: 3 + stride: 4 + bit_offset: 0 + bit_size: 1 + description: PLL1 fractional latch enable + name: PLLFRACEN + - array: + len: 3 + stride: 4 + bit_offset: 1 + bit_size: 1 + description: PLL1 VCO selection + enum: PLLVCOSEL + name: PLLVCOSEL + - array: + len: 3 + stride: 4 + bit_offset: 2 + bit_size: 2 + description: PLL1 input frequency range + enum: PLLRGE + name: PLLRGE + - array: + len: 3 + stride: 3 + bit_offset: 16 + bit_size: 1 + description: PLL1 DIVP divider output enable + name: DIVPEN + - array: + len: 3 + stride: 3 + bit_offset: 17 + bit_size: 1 + description: PLL1 DIVQ divider output enable + name: DIVQEN + - array: + len: 3 + stride: 3 + bit_offset: 18 + bit_size: 1 + description: PLL1 DIVR divider output enable + name: DIVREN +fieldset/PLLCKSELR: + description: RCC PLLs Clock Source Selection Register + fields: + - bit_offset: 0 + bit_size: 2 + description: DIVMx and PLLs clock source selection + enum: PLLSRC + name: PLLSRC + - array: + len: 3 + stride: 8 + bit_offset: 4 + bit_size: 6 + description: Prescaler for PLL1 + name: DIVM +fieldset/RSR: + description: RCC Reset Status Register + fields: + - bit_offset: 16 + bit_size: 1 + description: Remove reset flag + enum: RSR_RMVF + name: RMVF + - bit_offset: 17 + bit_size: 1 + description: CPU reset flag + enum_read: RSR_CPURSTFR + name: CPURSTF + - bit_offset: 19 + bit_size: 1 + description: D1 domain power switch reset flag + enum_read: RSR_CPURSTFR + name: D1RSTF + - bit_offset: 20 + bit_size: 1 + description: D2 domain power switch reset flag + enum_read: RSR_CPURSTFR + name: D2RSTF + - bit_offset: 21 + bit_size: 1 + description: BOR reset flag + enum_read: RSR_CPURSTFR + name: BORRSTF + - bit_offset: 22 + bit_size: 1 + description: Pin reset flag (NRST) + enum_read: RSR_CPURSTFR + name: PINRSTF + - bit_offset: 23 + bit_size: 1 + description: POR/PDR reset flag + enum_read: RSR_CPURSTFR + name: PORRSTF + - bit_offset: 24 + bit_size: 1 + description: System reset from CPU reset flag + enum_read: RSR_CPURSTFR + name: SFTRSTF + - bit_offset: 26 + bit_size: 1 + description: Independent Watchdog reset flag + enum_read: RSR_CPURSTFR + name: IWDG1RSTF + - bit_offset: 28 + bit_size: 1 + description: Window Watchdog reset flag + enum_read: RSR_CPURSTFR + name: WWDG1RSTF + - bit_offset: 30 + bit_size: 1 + description: Reset due to illegal D1 DStandby or CPU CStop flag + enum_read: RSR_CPURSTFR + name: LPWRRSTF diff --git a/data/registers/rcc_l0.yaml b/data/registers/rcc_l0.yaml index 75c052f..eb962d2 100644 --- a/data/registers/rcc_l0.yaml +++ b/data/registers/rcc_l0.yaml @@ -1,1494 +1,1582 @@ ---- block/RCC: description: Reset and clock control items: - - name: CR - description: Clock control register - byte_offset: 0 - fieldset: CR - - name: ICSCR - description: Internal clock sources calibration register - byte_offset: 4 - fieldset: ICSCR - - name: CRRCR - description: Clock recovery RC register - byte_offset: 8 - fieldset: CRRCR - - name: CFGR - description: Clock configuration register - byte_offset: 12 - fieldset: CFGR - - name: CIER - description: Clock interrupt enable register - byte_offset: 16 - access: Read - fieldset: CIER - - name: CIFR - description: Clock interrupt flag register - byte_offset: 20 - access: Read - fieldset: CIFR - - name: CICR - description: Clock interrupt clear register - byte_offset: 24 - access: Read - fieldset: CICR - - name: IOPRSTR - description: GPIO reset register - byte_offset: 28 - fieldset: IOPRSTR - - name: AHBRSTR - description: AHB peripheral reset register - byte_offset: 32 - fieldset: AHBRSTR - - name: APB2RSTR - description: APB2 peripheral reset register - byte_offset: 36 - fieldset: APB2RSTR - - name: APB1RSTR - description: APB1 peripheral reset register - byte_offset: 40 - fieldset: APB1RSTR - - name: IOPENR - description: GPIO clock enable register - byte_offset: 44 - fieldset: IOPENR - - name: AHBENR - description: AHB peripheral clock enable register - byte_offset: 48 - fieldset: AHBENR - - name: APB2ENR - description: APB2 peripheral clock enable register - byte_offset: 52 - fieldset: APB2ENR - - name: APB1ENR - description: APB1 peripheral clock enable register - byte_offset: 56 - fieldset: APB1ENR - - name: IOPSMEN - description: GPIO clock enable in sleep mode register - byte_offset: 60 - fieldset: IOPSMEN - - name: AHBSMENR - description: AHB peripheral clock enable in sleep mode register - byte_offset: 64 - fieldset: AHBSMENR - - name: APB2SMENR - description: APB2 peripheral clock enable in sleep mode register - byte_offset: 68 - fieldset: APB2SMENR - - name: APB1SMENR - description: APB1 peripheral clock enable in sleep mode register - byte_offset: 72 - fieldset: APB1SMENR - - name: CCIPR - description: Clock configuration register - byte_offset: 76 - fieldset: CCIPR - - name: CSR - description: Control and status register - byte_offset: 80 - fieldset: CSR -fieldset/AHBENR: - description: AHB peripheral clock enable register - fields: - - name: DMAEN - description: DMA clock enable bit - bit_offset: 0 - bit_size: 1 - - name: MIFEN - description: NVM interface clock enable bit - bit_offset: 8 - bit_size: 1 - - name: CRCEN - description: CRC clock enable bit - bit_offset: 12 - bit_size: 1 - - name: TOUCHEN - description: Touch Sensing clock enable bit - bit_offset: 16 - bit_size: 1 - - name: RNGEN - description: Random Number Generator clock enable bit - bit_offset: 20 - bit_size: 1 - - name: CRYPEN - description: Crypto clock enable bit - bit_offset: 24 - bit_size: 1 -fieldset/AHBRSTR: - description: AHB peripheral reset register - fields: - - name: DMARST - description: DMA reset - bit_offset: 0 - bit_size: 1 - enum_write: CRYPRSTW - - name: MIFRST - description: Memory interface reset - bit_offset: 8 - bit_size: 1 - enum_write: CRYPRSTW - - name: CRCRST - description: Test integration module reset - bit_offset: 12 - bit_size: 1 - enum_write: CRYPRSTW - - name: TOUCHRST - description: Touch Sensing reset - bit_offset: 16 - bit_size: 1 - enum_write: CRYPRSTW - - name: RNGRST - description: Random Number Generator module reset - bit_offset: 20 - bit_size: 1 - enum_write: CRYPRSTW - - name: CRYPRST - description: Crypto module reset - bit_offset: 24 - bit_size: 1 - enum_write: CRYPRSTW -fieldset/AHBSMENR: - description: AHB peripheral clock enable in sleep mode register - fields: - - name: DMASMEN - description: DMA clock enable during sleep mode bit - bit_offset: 0 - bit_size: 1 - - name: MIFSMEN - description: NVM interface clock enable during sleep mode bit - bit_offset: 8 - bit_size: 1 - - name: SRAMSMEN - description: SRAM interface clock enable during sleep mode bit - bit_offset: 9 - bit_size: 1 - - name: CRCSMEN - description: CRC clock enable during sleep mode bit - bit_offset: 12 - bit_size: 1 - - name: TOUCHSMEN - description: Touch Sensing clock enable during sleep mode bit - bit_offset: 16 - bit_size: 1 - - name: RNGSMEN - description: Random Number Generator clock enable during sleep mode bit - bit_offset: 20 - bit_size: 1 - - name: CRYPSMEN - description: Crypto clock enable during sleep mode bit - bit_offset: 24 - bit_size: 1 -fieldset/APB1ENR: - description: APB1 peripheral clock enable register - fields: - - name: TIM2EN - description: Timer2 clock enable bit - bit_offset: 0 - bit_size: 1 - - name: TIM3EN - description: Timer3 clock enable bit - bit_offset: 1 - bit_size: 1 - - name: TIM6EN - description: Timer 6 clock enable bit - bit_offset: 4 - bit_size: 1 - - name: TIM7EN - description: Timer 7 clock enable bit - bit_offset: 5 - bit_size: 1 - - name: WWDGEN - description: Window watchdog clock enable bit - bit_offset: 11 - bit_size: 1 - - name: SPI2EN - description: SPI2 clock enable bit - bit_offset: 14 - bit_size: 1 - - name: USART2EN - description: UART2 clock enable bit - bit_offset: 17 - bit_size: 1 - - name: LPUART1EN - description: LPUART1 clock enable bit - bit_offset: 18 - bit_size: 1 - - name: USART4EN - description: USART4 clock enable bit - bit_offset: 19 - bit_size: 1 - - name: USART5EN - description: USART5 clock enable bit - bit_offset: 20 - bit_size: 1 - - name: I2C1EN - description: I2C1 clock enable bit - bit_offset: 21 - bit_size: 1 - - name: I2C2EN - description: I2C2 clock enable bit - bit_offset: 22 - bit_size: 1 - - name: USBEN - description: USB clock enable bit - bit_offset: 23 - bit_size: 1 - - name: CRSEN - description: Clock recovery system clock enable bit - bit_offset: 27 - bit_size: 1 - - name: PWREN - description: Power interface clock enable bit - bit_offset: 28 - bit_size: 1 - - name: DACEN - description: DAC interface clock enable bit - bit_offset: 29 - bit_size: 1 - - name: I2C3EN - description: I2C3 clock enable bit - bit_offset: 30 - bit_size: 1 - - name: LPTIM1EN - description: Low power timer clock enable bit - bit_offset: 31 - bit_size: 1 -fieldset/APB1RSTR: - description: APB1 peripheral reset register - fields: - - name: TIM2RST - description: Timer2 reset - bit_offset: 0 - bit_size: 1 - enum_write: LPTIMRSTW - - name: TIM3RST - description: Timer3 reset - bit_offset: 1 - bit_size: 1 - enum_write: LPTIMRSTW - - name: TIM6RST - description: Timer 6 reset - bit_offset: 4 - bit_size: 1 - enum_write: LPTIMRSTW - - name: TIM7RST - description: Timer 7 reset - bit_offset: 5 - bit_size: 1 - enum_write: LPTIMRSTW - - name: WWDRST - description: Window watchdog reset - bit_offset: 11 - bit_size: 1 - enum_write: LPTIMRSTW - - name: SPI2RST - description: SPI2 reset - bit_offset: 14 - bit_size: 1 - enum_write: LPTIMRSTW - - name: LPUART12RST - description: UART2 reset - bit_offset: 17 - bit_size: 1 - enum_write: LPTIMRSTW - - name: LPUART1RST - description: LPUART1 reset - bit_offset: 18 - bit_size: 1 - enum_write: LPTIMRSTW - - name: USART4RST - description: USART4 reset - bit_offset: 19 - bit_size: 1 - enum_write: LPTIMRSTW - - name: USART5RST - description: USART5 reset - bit_offset: 20 - bit_size: 1 - enum_write: LPTIMRSTW - - name: I2C1RST - description: I2C1 reset - bit_offset: 21 - bit_size: 1 - enum_write: LPTIMRSTW - - name: I2C2RST - description: I2C2 reset - bit_offset: 22 - bit_size: 1 - enum_write: LPTIMRSTW - - name: USBRST - description: USB reset - bit_offset: 23 - bit_size: 1 - enum_write: LPTIMRSTW - - name: CRSRST - description: Clock recovery system reset - bit_offset: 27 - bit_size: 1 - enum_write: LPTIMRSTW - - name: PWRRST - description: Power interface reset - bit_offset: 28 - bit_size: 1 - enum_write: LPTIMRSTW - - name: DACRST - description: DAC interface reset - bit_offset: 29 - bit_size: 1 - enum_write: LPTIMRSTW - - name: I2C3RST - description: I2C3 reset - bit_offset: 30 - bit_size: 1 - enum_write: LPTIMRSTW - - name: LPTIM1RST - description: Low power timer reset - bit_offset: 31 - bit_size: 1 - enum_write: LPTIMRSTW -fieldset/APB1SMENR: - description: APB1 peripheral clock enable in sleep mode register - fields: - - name: TIM2SMEN - description: Timer2 clock enable during sleep mode bit - bit_offset: 0 - bit_size: 1 - - name: TIM3SMEN - description: Timer3 clock enable during Sleep mode bit - bit_offset: 1 - bit_size: 1 - - name: TIM6SMEN - description: Timer 6 clock enable during sleep mode bit - bit_offset: 4 - bit_size: 1 - - name: TIM7SMEN - description: Timer 7 clock enable during Sleep mode bit - bit_offset: 5 - bit_size: 1 - - name: WWDGSMEN - description: Window watchdog clock enable during sleep mode bit - bit_offset: 11 - bit_size: 1 - - name: SPI2SMEN - description: SPI2 clock enable during sleep mode bit - bit_offset: 14 - bit_size: 1 - - name: USART2SMEN - description: UART2 clock enable during sleep mode bit - bit_offset: 17 - bit_size: 1 - - name: LPUART1SMEN - description: LPUART1 clock enable during sleep mode bit - bit_offset: 18 - bit_size: 1 - - name: USART4SMEN - description: USART4 clock enable during Sleep mode bit - bit_offset: 19 - bit_size: 1 - - name: USART5SMEN - description: USART5 clock enable during Sleep mode bit - bit_offset: 20 - bit_size: 1 - - name: I2C1SMEN - description: I2C1 clock enable during sleep mode bit - bit_offset: 21 - bit_size: 1 - - name: I2C2SMEN - description: I2C2 clock enable during sleep mode bit - bit_offset: 22 - bit_size: 1 - - name: USBSMEN - description: USB clock enable during sleep mode bit - bit_offset: 23 - bit_size: 1 - - name: CRSSMEN - description: Clock recovery system clock enable during sleep mode bit - bit_offset: 27 - bit_size: 1 - - name: PWRSMEN - description: Power interface clock enable during sleep mode bit - bit_offset: 28 - bit_size: 1 - - name: DACSMEN - description: DAC interface clock enable during sleep mode bit - bit_offset: 29 - bit_size: 1 - - name: I2C3SMEN - description: 2C3 clock enable during Sleep mode bit - bit_offset: 30 - bit_size: 1 - - name: LPTIM1SMEN - description: Low power timer clock enable during sleep mode bit - bit_offset: 31 - bit_size: 1 -fieldset/APB2ENR: - description: APB2 peripheral clock enable register - fields: - - name: SYSCFGEN - description: System configuration controller clock enable bit - bit_offset: 0 - bit_size: 1 - - name: TIM21EN - description: TIM21 timer clock enable bit - bit_offset: 2 - bit_size: 1 - - name: TIM22EN - description: TIM22 timer clock enable bit - bit_offset: 5 - bit_size: 1 - - name: MIFIEN - description: MiFaRe Firewall clock enable bit - bit_offset: 7 - bit_size: 1 - - name: ADCEN - description: ADC clock enable bit - bit_offset: 9 - bit_size: 1 - - name: SPI1EN - description: SPI1 clock enable bit - bit_offset: 12 - bit_size: 1 - - name: USART1EN - description: USART1 clock enable bit - bit_offset: 14 - bit_size: 1 - - name: DBGEN - description: DBG clock enable bit - bit_offset: 22 - bit_size: 1 -fieldset/APB2RSTR: - description: APB2 peripheral reset register - fields: - - name: SYSCFGRST - description: System configuration controller reset - bit_offset: 0 - bit_size: 1 - enum_write: DBGRSTW - - name: TIM21RST - description: TIM21 timer reset - bit_offset: 2 - bit_size: 1 - enum_write: DBGRSTW - - name: TIM22RST - description: TIM22 timer reset - bit_offset: 5 - bit_size: 1 - enum_write: DBGRSTW - - name: ADCRST - description: ADC interface reset - bit_offset: 9 - bit_size: 1 - enum_write: DBGRSTW - - name: SPI1RST - description: SPI 1 reset - bit_offset: 12 - bit_size: 1 - enum_write: DBGRSTW - - name: USART1RST - description: USART1 reset - bit_offset: 14 - bit_size: 1 - enum_write: DBGRSTW - - name: DBGRST - description: DBG reset - bit_offset: 22 - bit_size: 1 - enum_write: DBGRSTW -fieldset/APB2SMENR: - description: APB2 peripheral clock enable in sleep mode register - fields: - - name: SYSCFGSMEN - description: System configuration controller clock enable during sleep mode bit - bit_offset: 0 - bit_size: 1 - - name: TIM21SMEN - description: TIM21 timer clock enable during sleep mode bit - bit_offset: 2 - bit_size: 1 - - name: TIM22SMEN - description: TIM22 timer clock enable during sleep mode bit - bit_offset: 5 - bit_size: 1 - - name: ADCSMEN - description: ADC clock enable during sleep mode bit - bit_offset: 9 - bit_size: 1 - - name: SPI1SMEN - description: SPI1 clock enable during sleep mode bit - bit_offset: 12 - bit_size: 1 - - name: USART1SMEN - description: USART1 clock enable during sleep mode bit - bit_offset: 14 - bit_size: 1 - - name: DBGSMEN - description: DBG clock enable during sleep mode bit - bit_offset: 22 - bit_size: 1 -fieldset/CCIPR: - description: Clock configuration register - fields: - - name: USART1SEL - description: USART1 clock source selection bits - bit_offset: 0 - bit_size: 2 - enum: LPUARTSEL - - name: USART2SEL - description: USART2 clock source selection bits - bit_offset: 2 - bit_size: 2 - enum: LPUARTSEL - - name: LPUART1SEL - description: LPUART1 clock source selection bits - bit_offset: 10 - bit_size: 2 - enum: LPUARTSEL - - name: I2C1SEL - description: I2C1 clock source selection bits - bit_offset: 12 - bit_size: 2 - enum: ICSEL - - name: I2C3SEL - description: I2C3 clock source selection bits - bit_offset: 16 - bit_size: 2 - enum: ICSEL - - name: LPTIM1SEL - description: Low Power Timer clock source selection bits - bit_offset: 18 - bit_size: 2 - enum: LPTIMSEL - - name: HSI48MSEL - description: 48 MHz HSI48 clock source selection bit - bit_offset: 26 - bit_size: 1 -fieldset/CFGR: - description: Clock configuration register - fields: - - name: SW - description: System clock switch - bit_offset: 0 - bit_size: 2 - enum: SW - - name: SWS - description: System clock switch status - bit_offset: 2 - bit_size: 2 - enum: SWS - - name: HPRE - description: AHB prescaler - bit_offset: 4 - bit_size: 4 - enum: HPRE - - name: PPRE - description: APB low-speed prescaler (APB1) - bit_offset: 8 - bit_size: 3 - array: - len: 2 - stride: 3 - enum: PPRE - - name: STOPWUCK - description: Wake-up from stop clock selection - bit_offset: 15 - bit_size: 1 - enum: STOPWUCK - - name: PLLSRC - description: PLL entry clock source - bit_offset: 16 - bit_size: 1 - enum: PLLSRC - - name: PLLMUL - description: PLL multiplication factor - bit_offset: 18 - bit_size: 4 - enum: PLLMUL - - name: PLLDIV - description: PLL output division - bit_offset: 22 - bit_size: 2 - enum: PLLDIV - - name: MCOSEL - description: Microcontroller clock output selection - bit_offset: 24 - bit_size: 4 - enum: MCOSEL - - name: MCOPRE - description: Microcontroller clock output prescaler - bit_offset: 28 - bit_size: 3 - enum: MCOPRE -fieldset/CICR: - description: Clock interrupt clear register - fields: - - name: LSIRDYC - description: LSI ready Interrupt clear - bit_offset: 0 - bit_size: 1 - enum_write: CSSHSECW - - name: LSERDYC - description: LSE ready Interrupt clear - bit_offset: 1 - bit_size: 1 - enum_write: CSSHSECW - - name: HSI16RDYC - description: HSI16 ready Interrupt clear - bit_offset: 2 - bit_size: 1 - enum_write: CSSHSECW - - name: HSERDYC - description: HSE ready Interrupt clear - bit_offset: 3 - bit_size: 1 - enum_write: CSSHSECW - - name: PLLRDYC - description: PLL ready Interrupt clear - bit_offset: 4 - bit_size: 1 - enum_write: CSSHSECW - - name: MSIRDYC - description: MSI ready Interrupt clear - bit_offset: 5 - bit_size: 1 - enum_write: CSSHSECW - - name: HSI48RDYC - description: HSI48 ready Interrupt clear - bit_offset: 6 - bit_size: 1 - enum_write: CSSHSECW - - name: CSSLSEC - description: LSE Clock Security System Interrupt clear - bit_offset: 7 - bit_size: 1 - enum_write: CSSHSECW - - name: CSSHSEC - description: Clock Security System Interrupt clear - bit_offset: 8 - bit_size: 1 - enum_write: CSSHSECW -fieldset/CIER: - description: Clock interrupt enable register - fields: - - name: LSIRDYIE - description: LSI ready interrupt flag - bit_offset: 0 - bit_size: 1 - - name: LSERDYIE - description: LSE ready interrupt flag - bit_offset: 1 - bit_size: 1 - - name: HSI16RDYIE - description: HSI16 ready interrupt flag - bit_offset: 2 - bit_size: 1 - - name: HSERDYIE - description: HSE ready interrupt flag - bit_offset: 3 - bit_size: 1 - - name: PLLRDYIE - description: PLL ready interrupt flag - bit_offset: 4 - bit_size: 1 - - name: MSIRDYIE - description: MSI ready interrupt flag - bit_offset: 5 - bit_size: 1 - - name: HSI48RDYIE - description: HSI48 ready interrupt flag - bit_offset: 6 - bit_size: 1 - - name: CSSLSE - description: LSE CSS interrupt flag - bit_offset: 7 - bit_size: 1 -fieldset/CIFR: - description: Clock interrupt flag register - fields: - - name: LSIRDYF - description: LSI ready interrupt flag - bit_offset: 0 - bit_size: 1 - enum_read: HSI48RDYFR - - name: LSERDYF - description: LSE ready interrupt flag - bit_offset: 1 - bit_size: 1 - enum_read: HSI48RDYFR - - name: HSI16RDYF - description: HSI16 ready interrupt flag - bit_offset: 2 - bit_size: 1 - enum_read: HSI48RDYFR - - name: HSERDYF - description: HSE ready interrupt flag - bit_offset: 3 - bit_size: 1 - enum_read: HSI48RDYFR - - name: PLLRDYF - description: PLL ready interrupt flag - bit_offset: 4 - bit_size: 1 - enum_read: HSI48RDYFR - - name: MSIRDYF - description: MSI ready interrupt flag - bit_offset: 5 - bit_size: 1 - enum_read: HSI48RDYFR - - name: HSI48RDYF - description: HSI48 ready interrupt flag - bit_offset: 6 - bit_size: 1 - enum_read: HSI48RDYFR - - name: CSSLSEF - description: LSE Clock Security System Interrupt flag - bit_offset: 7 - bit_size: 1 - enum: CSSLSEF - - name: CSSHSEF - description: Clock Security System Interrupt flag - bit_offset: 8 - bit_size: 1 - enum: CSSHSEF -fieldset/CR: - description: Clock control register - fields: - - name: HSI16ON - description: 16 MHz high-speed internal clock enable - bit_offset: 0 - bit_size: 1 - - name: HSI16KERON - description: High-speed internal clock enable bit for some IP kernels - bit_offset: 1 - bit_size: 1 - - name: HSI16RDYF - description: Internal high-speed clock ready flag - bit_offset: 2 - bit_size: 1 - enum_read: HSI16RDYFR - - name: HSI16DIVEN - description: HSI16DIVEN - bit_offset: 3 - bit_size: 1 - - name: HSI16DIVF - description: HSI16DIVF - bit_offset: 4 - bit_size: 1 - enum_read: HSIDIVFR - - name: HSI16OUTEN - description: 16 MHz high-speed internal clock output enable - bit_offset: 5 - bit_size: 1 - - name: MSION - description: MSI clock enable bit - bit_offset: 8 - bit_size: 1 - - name: MSIRDY - description: MSI clock ready flag - bit_offset: 9 - bit_size: 1 - enum_read: HSERDYR - - name: HSEON - description: HSE clock enable bit - bit_offset: 16 - bit_size: 1 - - name: HSERDY - description: HSE clock ready flag - bit_offset: 17 - bit_size: 1 - enum_read: HSERDYR - - name: HSEBYP - description: HSE clock bypass bit - bit_offset: 18 - bit_size: 1 - enum: HSEBYP - - name: CSSHSEON - description: Clock security system on HSE enable bit - bit_offset: 19 - bit_size: 1 - - name: RTCPRE - description: TC/LCD prescaler - bit_offset: 20 - bit_size: 2 - enum: RTCPRE - - name: PLLON - description: PLL enable bit - bit_offset: 24 - bit_size: 1 - - name: PLLRDY - description: PLL clock ready flag - bit_offset: 25 - bit_size: 1 - enum_read: PLLRDYR -fieldset/CRRCR: - description: Clock recovery RC register - fields: - - name: HSI48ON - description: 48MHz HSI clock enable bit - bit_offset: 0 - bit_size: 1 - - name: HSI48RDY - description: 48MHz HSI clock ready flag - bit_offset: 1 - bit_size: 1 - - name: HSI48DIV6EN - description: 48 MHz HSI clock divided by 6 output enable - bit_offset: 2 - bit_size: 1 - - name: HSI48CAL - description: 48 MHz HSI clock calibration - bit_offset: 8 - bit_size: 8 -fieldset/CSR: - description: Control and status register - fields: - - name: LSION - description: Internal low-speed oscillator enable - bit_offset: 0 - bit_size: 1 - - name: LSIRDY - description: Internal low-speed oscillator ready bit - bit_offset: 1 - bit_size: 1 - enum: LSERDY - - name: LSEON - description: External low-speed oscillator enable bit - bit_offset: 8 - bit_size: 1 - - name: LSERDY - description: External low-speed oscillator ready bit - bit_offset: 9 - bit_size: 1 - enum: LSERDY - - name: LSEBYP - description: External low-speed oscillator bypass bit - bit_offset: 10 - bit_size: 1 - enum: LSEBYP - - name: LSEDRV - description: LSEDRV - bit_offset: 11 - bit_size: 2 - enum: LSEDRV - - name: CSSLSEON - description: CSSLSEON - bit_offset: 13 - bit_size: 1 - - name: CSSLSED - description: CSS on LSE failure detection flag - bit_offset: 14 - bit_size: 1 - enum: CSSLSED - - name: RTCSEL - description: RTC and LCD clock source selection bits - bit_offset: 16 - bit_size: 2 - enum: RTCSEL - - name: RTCEN - description: RTC clock enable bit - bit_offset: 18 - bit_size: 1 - - name: RTCRST - description: RTC software reset bit - bit_offset: 19 - bit_size: 1 - enum_write: RTCRSTW - - name: RMVF - description: Remove reset flag - bit_offset: 24 - bit_size: 1 - enum_write: RMVFW - - name: OBLRSTF - description: OBLRSTF - bit_offset: 25 - bit_size: 1 - enum_read: LPWRRSTFR - - name: PINRSTF - description: PIN reset flag - bit_offset: 26 - bit_size: 1 - enum_read: LPWRRSTFR - - name: PORRSTF - description: POR/PDR reset flag - bit_offset: 27 - bit_size: 1 - enum_read: LPWRRSTFR - - name: SFTRSTF - description: Software reset flag - bit_offset: 28 - bit_size: 1 - enum_read: LPWRRSTFR - - name: IWDGRSTF - description: Independent watchdog reset flag - bit_offset: 29 - bit_size: 1 - enum_read: LPWRRSTFR - - name: WWDGRSTF - description: Window watchdog reset flag - bit_offset: 30 - bit_size: 1 - enum_read: LPWRRSTFR - - name: LPWRRSTF - description: Low-power reset flag - bit_offset: 31 - bit_size: 1 - enum_read: LPWRRSTFR -fieldset/ICSCR: - description: Internal clock sources calibration register - fields: - - name: HSI16CAL - description: nternal high speed clock calibration - bit_offset: 0 - bit_size: 8 - - name: HSI16TRIM - description: High speed internal clock trimming - bit_offset: 8 - bit_size: 5 - - name: MSIRANGE - description: MSI clock ranges - bit_offset: 13 - bit_size: 3 - enum: MSIRANGE - - name: MSICAL - description: MSI clock calibration - bit_offset: 16 - bit_size: 8 - - name: MSITRIM - description: MSI clock trimming - bit_offset: 24 - bit_size: 8 -fieldset/IOPENR: - description: GPIO clock enable register - fields: - - name: IOPAEN - description: IO port A clock enable bit - bit_offset: 0 - bit_size: 1 - - name: IOPBEN - description: IO port B clock enable bit - bit_offset: 1 - bit_size: 1 - - name: IOPCEN - description: IO port A clock enable bit - bit_offset: 2 - bit_size: 1 - - name: IOPDEN - description: I/O port D clock enable bit - bit_offset: 3 - bit_size: 1 - - name: IOPEEN - description: I/O port E clock enable bit - bit_offset: 4 - bit_size: 1 - - name: IOPHEN - description: I/O port H clock enable bit - bit_offset: 7 - bit_size: 1 -fieldset/IOPRSTR: - description: GPIO reset register - fields: - - name: IOPARST - description: I/O port A reset - bit_offset: 0 - bit_size: 1 - enum: IOPHRST - - name: IOPBRST - description: I/O port B reset - bit_offset: 1 - bit_size: 1 - enum: IOPHRST - - name: IOPCRST - description: I/O port A reset - bit_offset: 2 - bit_size: 1 - enum: IOPHRST - - name: IOPDRST - description: I/O port D reset - bit_offset: 3 - bit_size: 1 - enum: IOPHRST - - name: IOPERST - description: I/O port E reset - bit_offset: 4 - bit_size: 1 - enum: IOPHRST - - name: IOPHRST - description: I/O port H reset - bit_offset: 7 - bit_size: 1 - enum: IOPHRST -fieldset/IOPSMEN: - description: GPIO clock enable in sleep mode register - fields: - - name: IOPASMEN - description: IOPASMEN - bit_offset: 0 - bit_size: 1 - - name: IOPBSMEN - description: IOPBSMEN - bit_offset: 1 - bit_size: 1 - - name: IOPCSMEN - description: IOPCSMEN - bit_offset: 2 - bit_size: 1 - - name: IOPDSMEN - description: IOPDSMEN - bit_offset: 3 - bit_size: 1 - - name: IOPESMEN - description: Port E clock enable during Sleep mode bit - bit_offset: 4 - bit_size: 1 - - name: IOPHSMEN - description: IOPHSMEN - bit_offset: 7 - bit_size: 1 + - byte_offset: 0 + description: Clock control register + fieldset: CR + name: CR + - byte_offset: 4 + description: Internal clock sources calibration register + fieldset: ICSCR + name: ICSCR + - byte_offset: 12 + description: Clock configuration register + fieldset: CFGR + name: CFGR + - access: Read + byte_offset: 16 + description: Clock interrupt enable register + fieldset: CIER + name: CIER + - access: Read + byte_offset: 20 + description: Clock interrupt flag register + fieldset: CIFR + name: CIFR + - access: Read + byte_offset: 24 + description: Clock interrupt clear register + fieldset: CICR + name: CICR + - byte_offset: 28 + description: GPIO reset register + fieldset: IOPRSTR + name: IOPRSTR + - byte_offset: 32 + description: AHB peripheral reset register + fieldset: AHBRSTR + name: AHBRSTR + - byte_offset: 36 + description: APB2 peripheral reset register + fieldset: APB2RSTR + name: APB2RSTR + - byte_offset: 40 + description: APB1 peripheral reset register + fieldset: APB1RSTR + name: APB1RSTR + - byte_offset: 44 + description: GPIO clock enable register + fieldset: IOPENR + name: IOPENR + - byte_offset: 48 + description: AHB peripheral clock enable register + fieldset: AHBENR + name: AHBENR + - byte_offset: 52 + description: APB2 peripheral clock enable register + fieldset: APB2ENR + name: APB2ENR + - byte_offset: 56 + description: APB1 peripheral clock enable register + fieldset: APB1ENR + name: APB1ENR + - byte_offset: 60 + description: GPIO clock enable in sleep mode register + fieldset: IOPSMEN + name: IOPSMEN + - byte_offset: 64 + description: AHB peripheral clock enable in sleep mode register + fieldset: AHBSMENR + name: AHBSMENR + - byte_offset: 68 + description: APB2 peripheral clock enable in sleep mode register + fieldset: APB2SMENR + name: APB2SMENR + - byte_offset: 72 + description: APB1 peripheral clock enable in sleep mode register + fieldset: APB1SMENR + name: APB1SMENR + - byte_offset: 76 + description: Clock configuration register + fieldset: CCIPR + name: CCIPR + - byte_offset: 80 + description: Control and status register + fieldset: CSR + name: CSR + - byte_offset: 8 + description: Clock recovery RC register + fieldset: CRRCR + name: CRRCR enum/CRYPRSTW: bit_size: 1 variants: - - name: Reset - description: Reset the module - value: 1 + - description: Reset the module + name: Reset + value: 1 enum/CSSHSECW: bit_size: 1 variants: - - name: Clear - description: Clear interrupt flag - value: 1 + - description: Clear interrupt flag + name: Clear + value: 1 enum/CSSHSEF: bit_size: 1 variants: - - name: NoClock - description: No clock security interrupt caused by HSE clock failure - value: 0 - - name: Clock - description: Clock security interrupt caused by HSE clock failure - value: 1 + - description: No clock security interrupt caused by HSE clock failure + name: NoClock + value: 0 + - description: Clock security interrupt caused by HSE clock failure + name: Clock + value: 1 +enum/CSSLSE: + bit_size: 1 + variants: + - description: LSE CSS interrupt disabled + name: Disabled + value: 0 + - description: LSE CSS interrupt enabled + name: Enabled + value: 1 enum/CSSLSED: bit_size: 1 variants: - - name: NoFailure - description: No failure detected on LSE (32 kHz oscillator) - value: 0 - - name: Failure - description: Failure detected on LSE (32 kHz oscillator) - value: 1 + - description: No failure detected on LSE (32 kHz oscillator) + name: NoFailure + value: 0 + - description: Failure detected on LSE (32 kHz oscillator) + name: Failure + value: 1 enum/CSSLSEF: bit_size: 1 variants: - - name: NoFailure - description: No failure detected on LSE clock failure - value: 0 - - name: Failure - description: Failure detected on LSE clock failure - value: 1 + - description: No failure detected on LSE clock failure + name: NoFailure + value: 0 + - description: Failure detected on LSE clock failure + name: Failure + value: 1 enum/DBGRSTW: bit_size: 1 variants: - - name: Reset - description: Reset the module - value: 1 + - description: Reset the module + name: Reset + value: 1 enum/HPRE: bit_size: 4 variants: - - name: Div1 - description: system clock not divided - value: 0 - - name: Div2 - description: system clock divided by 2 - value: 8 - - name: Div4 - description: system clock divided by 4 - value: 9 - - name: Div8 - description: system clock divided by 8 - value: 10 - - name: Div16 - description: system clock divided by 16 - value: 11 - - name: Div64 - description: system clock divided by 64 - value: 12 - - name: Div128 - description: system clock divided by 128 - value: 13 - - name: Div256 - description: system clock divided by 256 - value: 14 - - name: Div512 - description: system clock divided by 512 - value: 15 + - description: system clock not divided + name: Div1 + value: 0 + - description: system clock divided by 2 + name: Div2 + value: 8 + - description: system clock divided by 4 + name: Div4 + value: 9 + - description: system clock divided by 8 + name: Div8 + value: 10 + - description: system clock divided by 16 + name: Div16 + value: 11 + - description: system clock divided by 64 + name: Div64 + value: 12 + - description: system clock divided by 128 + name: Div128 + value: 13 + - description: system clock divided by 256 + name: Div256 + value: 14 + - description: system clock divided by 512 + name: Div512 + value: 15 enum/HSEBYP: bit_size: 1 variants: - - name: NotBypassed - description: HSE oscillator not bypassed - value: 0 - - name: Bypassed - description: HSE oscillator bypassed - value: 1 + - description: HSE oscillator not bypassed + name: NotBypassed + value: 0 + - description: HSE oscillator bypassed + name: Bypassed + value: 1 enum/HSERDYR: bit_size: 1 variants: - - name: NotReady - description: Oscillator is not stable - value: 0 - - name: Ready - description: Oscillator is stable - value: 1 + - description: Oscillator is not stable + name: NotReady + value: 0 + - description: Oscillator is stable + name: Ready + value: 1 enum/HSI16RDYFR: bit_size: 1 variants: - - name: NotReady - description: HSI 16 MHz oscillator not ready - value: 0 - - name: Ready - description: HSI 16 MHz oscillator ready - value: 1 + - description: HSI 16 MHz oscillator not ready + name: NotReady + value: 0 + - description: HSI 16 MHz oscillator ready + name: Ready + value: 1 enum/HSI48RDYFR: bit_size: 1 variants: - - name: NotInterrupted - description: No clock ready interrupt - value: 0 - - name: Interrupted - description: Clock ready interrupt - value: 1 + - description: No clock ready interrupt + name: NotInterrupted + value: 0 + - description: Clock ready interrupt + name: Interrupted + value: 1 enum/HSIDIVFR: bit_size: 1 variants: - - name: NotDivided - description: 16 MHz HSI clock not divided - value: 0 - - name: Div4 - description: 16 MHz HSI clock divided by 4 - value: 1 + - description: 16 MHz HSI clock not divided + name: NotDivided + value: 0 + - description: 16 MHz HSI clock divided by 4 + name: Div4 + value: 1 +enum/HSIRDYFR: + bit_size: 1 + variants: + - description: HSI 16 MHz oscillator not ready + name: NotReady + value: 0 + - description: HSI 16 MHz oscillator ready + name: Ready + value: 1 +enum/HSIRDYIE: + bit_size: 1 + variants: + - description: Ready interrupt disabled + name: Disabled + value: 0 + - description: Ready interrupt enabled + name: Enabled + value: 1 enum/ICSEL: bit_size: 2 variants: - - name: APB - description: APB clock selected as peripheral clock - value: 0 - - name: SYSTEM - description: System clock selected as peripheral clock - value: 1 - - name: HSI16 - description: HSI16 clock selected as peripheral clock - value: 2 -enum/IOPHRST: - bit_size: 1 - variants: - - name: Reset - description: Reset I/O port - value: 1 + - description: APB clock selected as peripheral clock + name: APB + value: 0 + - description: System clock selected as peripheral clock + name: SYSTEM + value: 1 + - description: HSI16 clock selected as peripheral clock + name: HSI16 + value: 2 enum/LPTIMRSTW: bit_size: 1 variants: - - name: Reset - description: Reset the module - value: 1 + - description: Reset the module + name: Reset + value: 1 enum/LPTIMSEL: bit_size: 2 variants: - - name: APB - description: APB clock selected as Timer clock - value: 0 - - name: LSI - description: LSI clock selected as Timer clock - value: 1 - - name: HSI16 - description: HSI16 clock selected as Timer clock - value: 2 - - name: LSE - description: LSE clock selected as Timer clock - value: 3 + - description: APB clock selected as Timer clock + name: APB + value: 0 + - description: LSI clock selected as Timer clock + name: LSI + value: 1 + - description: HSI16 clock selected as Timer clock + name: HSI16 + value: 2 + - description: LSE clock selected as Timer clock + name: LSE + value: 3 enum/LPUARTSEL: bit_size: 2 variants: - - name: APB - description: APB clock selected as peripheral clock - value: 0 - - name: SYSTEM - description: System clock selected as peripheral clock - value: 1 - - name: HSI16 - description: HSI16 clock selected as peripheral clock - value: 2 - - name: LSE - description: LSE clock selected as peripheral clock - value: 3 + - description: APB clock selected as peripheral clock + name: APB + value: 0 + - description: System clock selected as peripheral clock + name: SYSTEM + value: 1 + - description: HSI16 clock selected as peripheral clock + name: HSI16 + value: 2 + - description: LSE clock selected as peripheral clock + name: LSE + value: 3 enum/LPWRRSTFR: bit_size: 1 variants: - - name: NoReset - description: No reset has occured - value: 0 - - name: Reset - description: A reset has occured - value: 1 + - description: No reset has occured + name: NoReset + value: 0 + - description: A reset has occured + name: Reset + value: 1 +enum/LPWRSTFR: + bit_size: 1 + variants: + - description: No reset has occured + name: NoReset + value: 0 + - description: A reset has occured + name: Reset + value: 1 enum/LSEBYP: bit_size: 1 variants: - - name: NotBypassed - description: LSE oscillator not bypassed - value: 0 - - name: Bypassed - description: LSE oscillator bypassed - value: 1 + - description: LSE oscillator not bypassed + name: NotBypassed + value: 0 + - description: LSE oscillator bypassed + name: Bypassed + value: 1 enum/LSEDRV: bit_size: 2 variants: - - name: Low - description: Lowest drive - value: 0 - - name: MediumLow - description: Medium low drive - value: 1 - - name: MediumHigh - description: Medium high drive - value: 2 - - name: High - description: Highest drive - value: 3 + - description: Lowest drive + name: Low + value: 0 + - description: Medium low drive + name: MediumLow + value: 1 + - description: Medium high drive + name: MediumHigh + value: 2 + - description: Highest drive + name: High + value: 3 enum/LSERDY: bit_size: 1 variants: - - name: NotReady - description: Oscillator not ready - value: 0 - - name: Ready - description: Oscillator ready - value: 1 + - description: Oscillator not ready + name: NotReady + value: 0 + - description: Oscillator ready + name: Ready + value: 1 enum/MCOPRE: bit_size: 3 variants: - - name: Div1 - description: No division - value: 0 - - name: Div2 - description: Division by 2 - value: 1 - - name: Div4 - description: Division by 4 - value: 2 - - name: Div8 - description: Division by 8 - value: 3 - - name: Div16 - description: Division by 16 - value: 4 + - description: No division + name: Div1 + value: 0 + - description: Division by 2 + name: Div2 + value: 1 + - description: Division by 4 + name: Div4 + value: 2 + - description: Division by 8 + name: Div8 + value: 3 + - description: Division by 16 + name: Div16 + value: 4 enum/MCOSEL: bit_size: 4 variants: - - name: NoClock - description: No clock - value: 0 - - name: SYSCLK - description: SYSCLK clock selected - value: 1 - - name: HSI16 - description: HSI oscillator clock selected - value: 2 - - name: MSI - description: MSI oscillator clock selected - value: 3 - - name: HSE - description: HSE oscillator clock selected - value: 4 - - name: PLL - description: PLL clock selected - value: 5 - - name: LSI - description: LSI oscillator clock selected - value: 6 - - name: LSE - description: LSE oscillator clock selected - value: 7 + - description: No clock + name: NoClock + value: 0 + - description: SYSCLK clock selected + name: SYSCLK + value: 1 + - description: HSI oscillator clock selected + name: HSI16 + value: 2 + - description: MSI oscillator clock selected + name: MSI + value: 3 + - description: HSE oscillator clock selected + name: HSE + value: 4 + - description: PLL clock selected + name: PLL + value: 5 + - description: LSI oscillator clock selected + name: LSI + value: 6 + - description: LSE oscillator clock selected + name: LSE + value: 7 enum/MSIRANGE: bit_size: 3 variants: - - name: Range0 - description: range 0 around 65.536 kHz - value: 0 - - name: Range1 - description: range 1 around 131.072 kHz - value: 1 - - name: Range2 - description: range 2 around 262.144 kHz - value: 2 - - name: Range3 - description: range 3 around 524.288 kHz - value: 3 - - name: Range4 - description: range 4 around 1.048 MHz - value: 4 - - name: Range5 - description: range 5 around 2.097 MHz (reset value) - value: 5 - - name: Range6 - description: range 6 around 4.194 MHz - value: 6 - - name: Range7 - description: not allowed - value: 7 + - description: range 0 around 65.536 kHz + name: Range0 + value: 0 + - description: range 1 around 131.072 kHz + name: Range1 + value: 1 + - description: range 2 around 262.144 kHz + name: Range2 + value: 2 + - description: range 3 around 524.288 kHz + name: Range3 + value: 3 + - description: range 4 around 1.048 MHz + name: Range4 + value: 4 + - description: range 5 around 2.097 MHz (reset value) + name: Range5 + value: 5 + - description: range 6 around 4.194 MHz + name: Range6 + value: 6 + - description: not allowed + name: Range7 + value: 7 +enum/MSIRDYFR: + bit_size: 1 + variants: + - description: No clock ready interrupt + name: NotInterrupted + value: 0 + - description: Clock ready interrupt + name: Interrupted + value: 1 +enum/MSIRDYIE: + bit_size: 1 + variants: + - description: Ready interrupt disabled + name: Disabled + value: 0 + - description: Ready interrupt enabled + name: Enabled + value: 1 enum/PLLDIV: bit_size: 2 variants: - - name: Div2 - description: PLLVCO / 2 - value: 1 - - name: Div3 - description: PLLVCO / 3 - value: 2 - - name: Div4 - description: PLLVCO / 4 - value: 3 + - description: PLLVCO / 2 + name: Div2 + value: 1 + - description: PLLVCO / 3 + name: Div3 + value: 2 + - description: PLLVCO / 4 + name: Div4 + value: 3 enum/PLLMUL: bit_size: 4 variants: - - name: Mul3 - description: PLL clock entry x 3 - value: 0 - - name: Mul4 - description: PLL clock entry x 4 - value: 1 - - name: Mul6 - description: PLL clock entry x 6 - value: 2 - - name: Mul8 - description: PLL clock entry x 8 - value: 3 - - name: Mul12 - description: PLL clock entry x 12 - value: 4 - - name: Mul16 - description: PLL clock entry x 16 - value: 5 - - name: Mul24 - description: PLL clock entry x 24 - value: 6 - - name: Mul32 - description: PLL clock entry x 32 - value: 7 - - name: Mul48 - description: PLL clock entry x 48 - value: 8 + - description: PLL clock entry x 3 + name: Mul3 + value: 0 + - description: PLL clock entry x 4 + name: Mul4 + value: 1 + - description: PLL clock entry x 6 + name: Mul6 + value: 2 + - description: PLL clock entry x 8 + name: Mul8 + value: 3 + - description: PLL clock entry x 12 + name: Mul12 + value: 4 + - description: PLL clock entry x 16 + name: Mul16 + value: 5 + - description: PLL clock entry x 24 + name: Mul24 + value: 6 + - description: PLL clock entry x 32 + name: Mul32 + value: 7 + - description: PLL clock entry x 48 + name: Mul48 + value: 8 enum/PLLRDYR: bit_size: 1 variants: - - name: Unlocked - description: PLL unlocked - value: 0 - - name: Locked - description: PLL locked - value: 1 + - description: PLL unlocked + name: Unlocked + value: 0 + - description: PLL locked + name: Locked + value: 1 enum/PLLSRC: bit_size: 1 variants: - - name: HSI16 - description: HSI selected as PLL input clock - value: 0 - - name: HSE - description: HSE selected as PLL input clock - value: 1 + - description: HSI selected as PLL input clock + name: HSI16 + value: 0 + - description: HSE selected as PLL input clock + name: HSE + value: 1 enum/PPRE: bit_size: 3 variants: - - name: Div1 - description: HCLK not divided - value: 0 - - name: Div2 - description: HCLK divided by 2 - value: 4 - - name: Div4 - description: HCLK divided by 4 - value: 5 - - name: Div8 - description: HCLK divided by 8 - value: 6 - - name: Div16 - description: HCLK divided by 16 - value: 7 + - description: HCLK not divided + name: Div1 + value: 0 + - description: HCLK divided by 2 + name: Div2 + value: 4 + - description: HCLK divided by 4 + name: Div4 + value: 5 + - description: HCLK divided by 8 + name: Div8 + value: 6 + - description: HCLK divided by 16 + name: Div16 + value: 7 enum/RMVFW: bit_size: 1 variants: - - name: Clear - description: Clears the reset flag - value: 1 + - description: Clears the reset flag + name: Clear + value: 1 enum/RTCPRE: bit_size: 2 variants: - - name: Div2 - description: HSE divided by 2 - value: 0 - - name: Div4 - description: HSE divided by 4 - value: 1 - - name: Div8 - description: HSE divided by 8 - value: 2 - - name: Div16 - description: HSE divided by 16 - value: 3 + - description: HSE divided by 2 + name: Div2 + value: 0 + - description: HSE divided by 4 + name: Div4 + value: 1 + - description: HSE divided by 8 + name: Div8 + value: 2 + - description: HSE divided by 16 + name: Div16 + value: 3 enum/RTCRSTW: bit_size: 1 variants: - - name: Reset - description: Resets the RTC peripheral - value: 1 + - description: Resets the RTC peripheral + name: Reset + value: 1 enum/RTCSEL: bit_size: 2 variants: - - name: NoClock - description: No clock - value: 0 - - name: LSE - description: LSE oscillator clock used as RTC clock - value: 1 - - name: LSI - description: LSI oscillator clock used as RTC clock - value: 2 - - name: HSE - description: "HSE oscillator clock divided by a programmable prescaler (selection through the RTCPRE[1:0] bits in the RCC clock control register (RCC_CR)) used as the RTC clock" - value: 3 + - description: No clock + name: NoClock + value: 0 + - description: LSE oscillator clock used as RTC clock + name: LSE + value: 1 + - description: LSI oscillator clock used as RTC clock + name: LSI + value: 2 + - description: HSE oscillator clock divided by a programmable prescaler (selection + through the RTCPRE[1:0] bits in the RCC clock control register (RCC_CR)) used + as the RTC clock + name: HSE + value: 3 enum/STOPWUCK: bit_size: 1 variants: - - name: MSI - description: Internal 64 KHz to 4 MHz (MSI) oscillator selected as wake-up from Stop clock - value: 0 - - name: HSI16 - description: Internal 16 MHz (HSI) oscillator selected as wake-up from Stop clock (or HSI16/4 if HSI16DIVEN=1) - value: 1 + - description: Internal 64 KHz to 4 MHz (MSI) oscillator selected as wake-up from + Stop clock + name: MSI + value: 0 + - description: Internal 16 MHz (HSI) oscillator selected as wake-up from Stop clock + (or HSI16/4 if HSI16DIVEN=1) + name: HSI16 + value: 1 enum/SW: bit_size: 2 variants: - - name: MSI - description: MSI oscillator used as system clock - value: 0 - - name: HSI16 - description: HSI oscillator used as system clock - value: 1 - - name: HSE - description: HSE oscillator used as system clock - value: 2 - - name: PLL - description: PLL used as system clock - value: 3 + - description: MSI oscillator used as system clock + name: MSI + value: 0 + - description: HSI oscillator used as system clock + name: HSI16 + value: 1 + - description: HSE oscillator used as system clock + name: HSE + value: 2 + - description: PLL used as system clock + name: PLL + value: 3 enum/SWS: bit_size: 2 variants: - - name: MSI - description: MSI oscillator used as system clock - value: 0 - - name: HSI16 - description: HSI oscillator used as system clock - value: 1 - - name: HSE - description: HSE oscillator used as system clock - value: 2 - - name: PLL - description: PLL used as system clock - value: 3 + - description: MSI oscillator used as system clock + name: MSI + value: 0 + - description: HSI oscillator used as system clock + name: HSI16 + value: 1 + - description: HSE oscillator used as system clock + name: HSE + value: 2 + - description: PLL used as system clock + name: PLL + value: 3 +fieldset/AHBENR: + description: AHB peripheral clock enable register + fields: + - bit_offset: 0 + bit_size: 1 + description: DMA clock enable bit + name: DMAEN + - bit_offset: 8 + bit_size: 1 + description: NVM interface clock enable bit + name: MIFEN + - bit_offset: 12 + bit_size: 1 + description: CRC clock enable bit + name: CRCEN + - bit_offset: 24 + bit_size: 1 + description: Crypto clock enable bit + name: CRYPEN + - bit_offset: 16 + bit_size: 1 + description: Touch Sensing clock enable bit + name: TOUCHEN + - bit_offset: 20 + bit_size: 1 + description: Random Number Generator clock enable bit + name: RNGEN +fieldset/AHBRSTR: + description: AHB peripheral reset register + fields: + - bit_offset: 0 + bit_size: 1 + description: DMA reset + enum_write: CRYPRSTW + name: DMARST + - bit_offset: 8 + bit_size: 1 + description: Memory interface reset + enum_write: CRYPRSTW + name: MIFRST + - bit_offset: 12 + bit_size: 1 + description: Test integration module reset + enum_write: CRYPRSTW + name: CRCRST + - bit_offset: 24 + bit_size: 1 + description: Crypto module reset + enum_write: CRYPRSTW + name: CRYPRST + - bit_offset: 16 + bit_size: 1 + description: Touch Sensing reset + enum_write: CRYPRSTW + name: TOUCHRST + - bit_offset: 20 + bit_size: 1 + description: Random Number Generator module reset + enum_write: CRYPRSTW + name: RNGRST +fieldset/AHBSMENR: + description: AHB peripheral clock enable in sleep mode register + fields: + - bit_offset: 0 + bit_size: 1 + description: DMA clock enable during sleep mode bit + name: DMASMEN + - bit_offset: 8 + bit_size: 1 + description: NVM interface clock enable during sleep mode bit + name: MIFSMEN + - bit_offset: 9 + bit_size: 1 + description: SRAM interface clock enable during sleep mode bit + name: SRAMSMEN + - bit_offset: 12 + bit_size: 1 + description: CRC clock enable during sleep mode bit + name: CRCSMEN + - bit_offset: 24 + bit_size: 1 + description: Crypto clock enable during sleep mode bit + name: CRYPSMEN + - bit_offset: 16 + bit_size: 1 + description: Touch Sensing clock enable during sleep mode bit + name: TOUCHSMEN + - bit_offset: 20 + bit_size: 1 + description: Random Number Generator clock enable during sleep mode bit + name: RNGSMEN +fieldset/APB1ENR: + description: APB1 peripheral clock enable register + fields: + - bit_offset: 0 + bit_size: 1 + description: Timer2 clock enable bit + name: TIM2EN + - bit_offset: 4 + bit_size: 1 + description: Timer 6 clock enable bit + name: TIM6EN + - bit_offset: 5 + bit_size: 1 + description: Timer 7 clock enable bit + name: TIM7EN + - bit_offset: 11 + bit_size: 1 + description: Window watchdog clock enable bit + name: WWDGEN + - bit_offset: 14 + bit_size: 1 + description: SPI2 clock enable bit + name: SPI2EN + - bit_offset: 17 + bit_size: 1 + description: UART2 clock enable bit + name: USART2EN + - bit_offset: 18 + bit_size: 1 + description: LPUART1 clock enable bit + name: LPUART1EN + - bit_offset: 19 + bit_size: 1 + description: USART4 clock enable bit + name: USART4EN + - bit_offset: 20 + bit_size: 1 + description: USART5 clock enable bit + name: USART5EN + - bit_offset: 21 + bit_size: 1 + description: I2C1 clock enable bit + name: I2C1EN + - bit_offset: 22 + bit_size: 1 + description: I2C2 clock enable bit + name: I2C2EN + - bit_offset: 28 + bit_size: 1 + description: Power interface clock enable bit + name: PWREN + - bit_offset: 30 + bit_size: 1 + description: I2C3 clock enable bit + name: I2C3EN + - bit_offset: 31 + bit_size: 1 + description: Low power timer clock enable bit + name: LPTIM1EN + - bit_offset: 1 + bit_size: 1 + description: Timer 3 clock enbale bit + name: TIM3EN + - bit_offset: 23 + bit_size: 1 + description: USB clock enable bit + name: USBEN + - bit_offset: 27 + bit_size: 1 + description: Clock recovery system clock enable bit + name: CRSEN + - bit_offset: 29 + bit_size: 1 + description: DAC interface clock enable bit + name: DACEN +fieldset/APB1RSTR: + description: APB1 peripheral reset register + fields: + - bit_offset: 0 + bit_size: 1 + description: Timer 2 reset + enum_write: LPTIMRSTW + name: TIM2RST + - bit_offset: 1 + bit_size: 1 + description: Timer 3 reset + enum_write: LPTIMRSTW + name: TIM3RST + - bit_offset: 4 + bit_size: 1 + description: Timer 6 reset + enum_write: LPTIMRSTW + name: TIM6RST + - bit_offset: 5 + bit_size: 1 + description: Timer 7 reset + enum_write: LPTIMRSTW + name: TIM7RST + - bit_offset: 11 + bit_size: 1 + description: Window watchdog reset + enum_write: LPTIMRSTW + name: WWDGRST + - bit_offset: 14 + bit_size: 1 + description: SPI2 reset + enum_write: LPTIMRSTW + name: SPI2RST + - bit_offset: 17 + bit_size: 1 + description: USART2 reset + enum_write: LPTIMRSTW + name: USART2RST + - bit_offset: 18 + bit_size: 1 + description: LPUART1 reset + enum_write: LPTIMRSTW + name: LPUART1RST + - bit_offset: 19 + bit_size: 1 + description: USART4 reset + enum_write: LPTIMRSTW + name: USART4RST + - bit_offset: 20 + bit_size: 1 + description: USART5 reset + enum_write: LPTIMRSTW + name: USART5RST + - bit_offset: 21 + bit_size: 1 + description: I2C1 reset + enum_write: LPTIMRSTW + name: I2C1RST + - bit_offset: 22 + bit_size: 1 + description: I2C2 reset + enum_write: LPTIMRSTW + name: I2C2RST + - bit_offset: 27 + bit_size: 1 + description: CRC reset + enum_write: LPTIMRSTW + name: CRCRST + - bit_offset: 28 + bit_size: 1 + description: Power interface reset + enum_write: LPTIMRSTW + name: PWRRST + - bit_offset: 30 + bit_size: 1 + description: I2C3 reset + name: I2C3 + - bit_offset: 31 + bit_size: 1 + description: Low power timer reset + enum_write: LPTIMRSTW + name: LPTIM1RST + - bit_offset: 30 + bit_size: 1 + description: I2C3 reset + enum_write: LPTIMRSTW + name: I2C3RST + - bit_offset: 11 + bit_size: 1 + description: Window watchdog reset + enum_write: LPTIMRSTW + name: WWDRST + - bit_offset: 17 + bit_size: 1 + description: UART2 reset + enum_write: LPTIMRSTW + name: LPUART12RST + - bit_offset: 23 + bit_size: 1 + description: USB reset + enum_write: LPTIMRSTW + name: USBRST + - bit_offset: 27 + bit_size: 1 + description: Clock recovery system reset + enum_write: LPTIMRSTW + name: CRSRST + - bit_offset: 29 + bit_size: 1 + description: DAC interface reset + enum_write: LPTIMRSTW + name: DACRST +fieldset/APB1SMENR: + description: APB1 peripheral clock enable in sleep mode register + fields: + - bit_offset: 0 + bit_size: 1 + description: Timer2 clock enable during sleep mode bit + name: TIM2SMEN + - bit_offset: 1 + bit_size: 1 + description: Timer 3 clock enable during sleep mode bit + name: TIM3SMEN + - bit_offset: 4 + bit_size: 1 + description: Timer 6 clock enable during sleep mode bit + name: TIM6SMEN + - bit_offset: 5 + bit_size: 1 + description: Timer 7 clock enable during sleep mode bit + name: TIM7SMEN + - bit_offset: 11 + bit_size: 1 + description: Window watchdog clock enable during sleep mode bit + name: WWDGSMEN + - bit_offset: 14 + bit_size: 1 + description: SPI2 clock enable during sleep mode bit + name: SPI2SMEN + - bit_offset: 17 + bit_size: 1 + description: UART2 clock enable during sleep mode bit + name: USART2SMEN + - bit_offset: 18 + bit_size: 1 + description: LPUART1 clock enable during sleep mode bit + name: LPUART1SMEN + - bit_offset: 19 + bit_size: 1 + description: USART4 clock enabe during sleep mode bit + name: USART4SMEN + - bit_offset: 20 + bit_size: 1 + description: USART5 clock enable during sleep mode bit + name: USART5SMEN + - bit_offset: 21 + bit_size: 1 + description: I2C1 clock enable during sleep mode bit + name: I2C1SMEN + - bit_offset: 22 + bit_size: 1 + description: I2C2 clock enable during sleep mode bit + name: I2C2SMEN + - bit_offset: 27 + bit_size: 1 + description: Clock recovery system clock enable during sleep mode bit + name: CRSSMEN + - bit_offset: 28 + bit_size: 1 + description: Power interface clock enable during sleep mode bit + name: PWRSMEN + - bit_offset: 30 + bit_size: 1 + description: I2C3 clock enable during sleep mode bit + name: I2C3SMEN + - bit_offset: 31 + bit_size: 1 + description: Low power timer clock enable during sleep mode bit + name: LPTIM1SMEN + - bit_offset: 23 + bit_size: 1 + description: USB clock enable during sleep mode bit + name: USBSMEN + - bit_offset: 29 + bit_size: 1 + description: DAC interface clock enable during sleep mode bit + name: DACSMEN +fieldset/APB2ENR: + description: APB2 peripheral clock enable register + fields: + - bit_offset: 0 + bit_size: 1 + description: System configuration controller clock enable bit + name: SYSCFGEN + - bit_offset: 2 + bit_size: 1 + description: TIM21 timer clock enable bit + name: TIM21EN + - bit_offset: 5 + bit_size: 1 + description: TIM22 timer clock enable bit + name: TIM22EN + - bit_offset: 7 + bit_size: 1 + description: Firewall clock enable bit + name: FWEN + - bit_offset: 9 + bit_size: 1 + description: ADC clock enable bit + name: ADCEN + - bit_offset: 12 + bit_size: 1 + description: SPI1 clock enable bit + name: SPI1EN + - bit_offset: 14 + bit_size: 1 + description: USART1 clock enable bit + name: USART1EN + - bit_offset: 22 + bit_size: 1 + description: DBG clock enable bit + name: DBGEN + - bit_offset: 7 + bit_size: 1 + description: MiFaRe Firewall clock enable bit + name: MIFIEN +fieldset/APB2RSTR: + description: APB2 peripheral reset register + fields: + - bit_offset: 0 + bit_size: 1 + description: System configuration controller reset + enum_write: DBGRSTW + name: SYSCFGRST + - bit_offset: 2 + bit_size: 1 + description: TIM21 timer reset + enum_write: DBGRSTW + name: TIM21RST + - bit_offset: 5 + bit_size: 1 + description: TIM22 timer reset + enum_write: DBGRSTW + name: TIM22RST + - bit_offset: 9 + bit_size: 1 + description: ADC interface reset + enum_write: DBGRSTW + name: ADCRST + - bit_offset: 12 + bit_size: 1 + description: SPI 1 reset + enum_write: DBGRSTW + name: SPI1RST + - bit_offset: 14 + bit_size: 1 + description: USART1 reset + enum_write: DBGRSTW + name: USART1RST + - bit_offset: 22 + bit_size: 1 + description: DBG reset + enum_write: DBGRSTW + name: DBGRST +fieldset/APB2SMENR: + description: APB2 peripheral clock enable in sleep mode register + fields: + - bit_offset: 0 + bit_size: 1 + description: System configuration controller clock enable during sleep mode bit + name: SYSCFGSMEN + - bit_offset: 2 + bit_size: 1 + description: TIM21 timer clock enable during sleep mode bit + name: TIM21SMEN + - bit_offset: 5 + bit_size: 1 + description: TIM22 timer clock enable during sleep mode bit + name: TIM22SMEN + - bit_offset: 9 + bit_size: 1 + description: ADC clock enable during sleep mode bit + name: ADCSMEN + - bit_offset: 12 + bit_size: 1 + description: SPI1 clock enable during sleep mode bit + name: SPI1SMEN + - bit_offset: 14 + bit_size: 1 + description: USART1 clock enable during sleep mode bit + name: USART1SMEN + - bit_offset: 22 + bit_size: 1 + description: DBG clock enable during sleep mode bit + name: DBGSMEN +fieldset/CCIPR: + description: Clock configuration register + fields: + - bit_offset: 0 + bit_size: 2 + description: USART1 clock source selection bits + enum: LPUARTSEL + name: USART1SEL + - bit_offset: 2 + bit_size: 2 + description: USART2 clock source selection bits + enum: LPUARTSEL + name: USART2SEL + - bit_offset: 10 + bit_size: 2 + description: LPUART1 clock source selection bits + enum: LPUARTSEL + name: LPUART1SEL + - bit_offset: 12 + bit_size: 2 + description: I2C1 clock source selection bits + enum: ICSEL + name: I2C1SEL + - bit_offset: 16 + bit_size: 2 + description: I2C3 clock source selection bits + enum: ICSEL + name: I2C3SEL + - bit_offset: 18 + bit_size: 2 + description: Low Power Timer clock source selection bits + enum: LPTIMSEL + name: LPTIM1SEL + - bit_offset: 26 + bit_size: 1 + description: 48 MHz HSI48 clock source selection bit + name: HSI48MSEL +fieldset/CFGR: + description: Clock configuration register + fields: + - bit_offset: 0 + bit_size: 2 + description: System clock switch + enum: SW + name: SW + - bit_offset: 2 + bit_size: 2 + description: System clock switch status + enum: SWS + name: SWS + - bit_offset: 4 + bit_size: 4 + description: AHB prescaler + enum: HPRE + name: HPRE + - bit_offset: 8 + bit_size: 3 + description: APB low-speed prescaler (APB1) + enum: PPRE + name: PPRE1 + - bit_offset: 11 + bit_size: 3 + description: APB high-speed prescaler (APB2) + enum: PPRE + name: PPRE2 + - bit_offset: 15 + bit_size: 1 + description: Wake-up from stop clock selection + enum: STOPWUCK + name: STOPWUCK + - bit_offset: 16 + bit_size: 1 + description: PLL entry clock source + enum: PLLSRC + name: PLLSRC + - bit_offset: 18 + bit_size: 4 + description: PLL multiplication factor + enum: PLLMUL + name: PLLMUL + - bit_offset: 22 + bit_size: 2 + description: PLL output division + enum: PLLDIV + name: PLLDIV + - bit_offset: 24 + bit_size: 3 + description: Microcontroller clock output selection + enum: MCOSEL + name: MCOSEL + - bit_offset: 28 + bit_size: 3 + description: Microcontroller clock output prescaler + enum: MCOPRE + name: MCOPRE +fieldset/CICR: + description: Clock interrupt clear register + fields: + - bit_offset: 0 + bit_size: 1 + description: LSI ready Interrupt clear + enum_write: CSSHSECW + name: LSIRDYC + - bit_offset: 1 + bit_size: 1 + description: LSE ready Interrupt clear + enum_write: CSSHSECW + name: LSERDYC + - bit_offset: 2 + bit_size: 1 + description: HSI16 ready Interrupt clear + enum_write: CSSHSECW + name: HSI16RDYC + - bit_offset: 3 + bit_size: 1 + description: HSE ready Interrupt clear + enum_write: CSSHSECW + name: HSERDYC + - bit_offset: 4 + bit_size: 1 + description: PLL ready Interrupt clear + enum_write: CSSHSECW + name: PLLRDYC + - bit_offset: 5 + bit_size: 1 + description: MSI ready Interrupt clear + enum_write: CSSHSECW + name: MSIRDYC + - bit_offset: 7 + bit_size: 1 + description: LSE Clock Security System Interrupt clear + enum_write: CSSHSECW + name: CSSLSEC + - bit_offset: 8 + bit_size: 1 + description: Clock Security System Interrupt clear + enum_write: CSSHSECW + name: CSSHSEC + - bit_offset: 6 + bit_size: 1 + description: HSI48 ready Interrupt clear + enum_write: CSSHSECW + name: HSI48RDYC +fieldset/CIER: + description: Clock interrupt enable register + fields: + - bit_offset: 0 + bit_size: 1 + description: LSI ready interrupt flag + enum: MSIRDYIE + name: LSIRDYIE + - bit_offset: 1 + bit_size: 1 + description: LSE ready interrupt flag + enum: MSIRDYIE + name: LSERDYIE + - bit_offset: 2 + bit_size: 1 + description: HSI16 ready interrupt flag + enum: MSIRDYIE + name: HSI16RDYIE + - bit_offset: 3 + bit_size: 1 + description: HSE ready interrupt flag + enum: MSIRDYIE + name: HSERDYIE + - bit_offset: 4 + bit_size: 1 + description: PLL ready interrupt flag + enum: MSIRDYIE + name: PLLRDYIE + - bit_offset: 5 + bit_size: 1 + description: MSI ready interrupt flag + enum: MSIRDYIE + name: MSIRDYIE + - bit_offset: 7 + bit_size: 1 + description: LSE CSS interrupt flag + enum: CSSLSE + name: CSSLSE + - bit_offset: 6 + bit_size: 1 + description: HSI48 ready interrupt flag + enum: HSIRDYIE + name: HSI48RDYIE +fieldset/CIFR: + description: Clock interrupt flag register + fields: + - bit_offset: 0 + bit_size: 1 + description: LSI ready interrupt flag + enum_read: MSIRDYFR + name: LSIRDYF + - bit_offset: 1 + bit_size: 1 + description: LSE ready interrupt flag + enum_read: MSIRDYFR + name: LSERDYF + - bit_offset: 2 + bit_size: 1 + description: HSI16 ready interrupt flag + enum_read: MSIRDYFR + name: HSI16RDYF + - bit_offset: 3 + bit_size: 1 + description: HSE ready interrupt flag + enum_read: MSIRDYFR + name: HSERDYF + - bit_offset: 4 + bit_size: 1 + description: PLL ready interrupt flag + enum_read: MSIRDYFR + name: PLLRDYF + - bit_offset: 5 + bit_size: 1 + description: MSI ready interrupt flag + enum_read: MSIRDYFR + name: MSIRDYF + - bit_offset: 7 + bit_size: 1 + description: LSE Clock Security System Interrupt flag + enum: CSSLSEF + name: CSSLSEF + - bit_offset: 8 + bit_size: 1 + description: Clock Security System Interrupt flag + enum: CSSHSEF + name: CSSHSEF + - bit_offset: 6 + bit_size: 1 + description: HSI48 ready interrupt flag + enum_read: HSI48RDYFR + name: HSI48RDYF +fieldset/CR: + description: Clock control register + fields: + - bit_offset: 0 + bit_size: 1 + description: 16 MHz high-speed internal clock enable + name: HSI16ON + - bit_offset: 1 + bit_size: 1 + description: High-speed internal clock enable bit for some IP kernels + name: HSI16KERON + - bit_offset: 2 + bit_size: 1 + description: Internal high-speed clock ready flag + enum_read: HSIRDYFR + name: HSI16RDYF + - bit_offset: 3 + bit_size: 1 + description: HSI16DIVEN + name: HSI16DIVEN + - bit_offset: 4 + bit_size: 1 + description: HSI16DIVF + enum_read: HSIDIVFR + name: HSI16DIVF + - bit_offset: 5 + bit_size: 1 + description: 16 MHz high-speed internal clock output enable + name: HSI16OUTEN + - bit_offset: 8 + bit_size: 1 + description: MSI clock enable bit + name: MSION + - bit_offset: 9 + bit_size: 1 + description: MSI clock ready flag + enum_read: HSERDYR + name: MSIRDY + - bit_offset: 16 + bit_size: 1 + description: HSE clock enable bit + name: HSEON + - bit_offset: 17 + bit_size: 1 + description: HSE clock ready flag + enum_read: HSERDYR + name: HSERDY + - bit_offset: 18 + bit_size: 1 + description: HSE clock bypass bit + enum: HSEBYP + name: HSEBYP + - bit_offset: 19 + bit_size: 1 + description: Clock security system on HSE enable bit + name: CSSHSEON + - bit_offset: 20 + bit_size: 2 + description: TC/LCD prescaler + enum: RTCPRE + name: RTCPRE + - bit_offset: 24 + bit_size: 1 + description: PLL enable bit + name: PLLON + - bit_offset: 25 + bit_size: 1 + description: PLL clock ready flag + enum_read: PLLRDYR + name: PLLRDY +fieldset/CRRCR: + description: Clock recovery RC register + fields: + - bit_offset: 0 + bit_size: 1 + description: 48MHz HSI clock enable bit + name: HSI48ON + - bit_offset: 1 + bit_size: 1 + description: 48MHz HSI clock ready flag + name: HSI48RDY + - bit_offset: 2 + bit_size: 1 + description: 48 MHz HSI clock divided by 6 output enable + name: HSI48DIV6EN + - bit_offset: 8 + bit_size: 8 + description: 48 MHz HSI clock calibration + name: HSI48CAL +fieldset/CSR: + description: Control and status register + fields: + - bit_offset: 0 + bit_size: 1 + description: Internal low-speed oscillator enable + name: LSION + - bit_offset: 1 + bit_size: 1 + description: Internal low-speed oscillator ready bit + enum: LSERDY + name: LSIRDY + - bit_offset: 8 + bit_size: 1 + description: External low-speed oscillator enable bit + name: LSEON + - bit_offset: 9 + bit_size: 1 + description: External low-speed oscillator ready bit + enum: LSERDY + name: LSERDY + - bit_offset: 10 + bit_size: 1 + description: External low-speed oscillator bypass bit + enum: LSEBYP + name: LSEBYP + - bit_offset: 11 + bit_size: 2 + description: LSEDRV + enum: LSEDRV + name: LSEDRV + - bit_offset: 13 + bit_size: 1 + description: CSSLSEON + name: CSSLSEON + - bit_offset: 14 + bit_size: 1 + description: CSS on LSE failure detection flag + enum: CSSLSED + name: CSSLSED + - bit_offset: 16 + bit_size: 2 + description: RTC and LCD clock source selection bits + enum: RTCSEL + name: RTCSEL + - bit_offset: 18 + bit_size: 1 + description: RTC clock enable bit + name: RTCEN + - bit_offset: 19 + bit_size: 1 + description: RTC software reset bit + enum_write: RTCRSTW + name: RTCRST + - bit_offset: 23 + bit_size: 1 + description: Remove reset flag + enum_write: RMVFW + name: RMVF + - bit_offset: 24 + bit_size: 1 + description: Firewall reset flag + enum_read: LPWRRSTFR + name: FWRSTF + - bit_offset: 25 + bit_size: 1 + description: OBLRSTF + enum_read: LPWRRSTFR + name: OBLRSTF + - bit_offset: 26 + bit_size: 1 + description: PIN reset flag + enum_read: LPWRRSTFR + name: PINRSTF + - bit_offset: 27 + bit_size: 1 + description: POR/PDR reset flag + enum_read: LPWRRSTFR + name: PORRSTF + - bit_offset: 28 + bit_size: 1 + description: Software reset flag + enum_read: LPWRRSTFR + name: SFTRSTF + - bit_offset: 29 + bit_size: 1 + description: Independent watchdog reset flag + enum_read: LPWRRSTFR + name: IWDGRSTF + - bit_offset: 30 + bit_size: 1 + description: Window watchdog reset flag + enum_read: LPWRRSTFR + name: WWDGRSTF + - bit_offset: 31 + bit_size: 1 + description: Low-power reset flag + enum_read: LPWRRSTFR + name: LPWRRSTF + - bit_offset: 31 + bit_size: 1 + description: Low-power reset flag + enum_read: LPWRSTFR + name: LPWRSTF +fieldset/ICSCR: + description: Internal clock sources calibration register + fields: + - bit_offset: 0 + bit_size: 8 + description: nternal high speed clock calibration + name: HSI16CAL + - bit_offset: 8 + bit_size: 5 + description: High speed internal clock trimming + name: HSI16TRIM + - bit_offset: 13 + bit_size: 3 + description: MSI clock ranges + enum: MSIRANGE + name: MSIRANGE + - bit_offset: 16 + bit_size: 8 + description: MSI clock calibration + name: MSICAL + - bit_offset: 24 + bit_size: 8 + description: MSI clock trimming + name: MSITRIM +fieldset/IOPENR: + description: GPIO clock enable register + fields: + - bit_offset: 0 + bit_size: 1 + description: IO port A clock enable bit + name: IOPAEN + - bit_offset: 1 + bit_size: 1 + description: IO port B clock enable bit + name: IOPBEN + - bit_offset: 2 + bit_size: 1 + description: IO port A clock enable bit + name: IOPCEN + - bit_offset: 3 + bit_size: 1 + description: I/O port D clock enable bit + name: IOPDEN + - bit_offset: 4 + bit_size: 1 + description: IO port E clock enable bit + name: IOPEEN + - bit_offset: 7 + bit_size: 1 + description: I/O port H clock enable bit + name: IOPHEN +fieldset/IOPRSTR: + description: GPIO reset register + fields: + - bit_offset: 0 + bit_size: 1 + description: I/O port A reset + name: IOPARST + - bit_offset: 1 + bit_size: 1 + description: I/O port B reset + name: IOPBRST + - bit_offset: 2 + bit_size: 1 + description: I/O port A reset + name: IOPCRST + - bit_offset: 3 + bit_size: 1 + description: I/O port D reset + name: IOPDRST + - bit_offset: 4 + bit_size: 1 + description: I/O port E reset + name: IOPERST + - bit_offset: 7 + bit_size: 1 + description: I/O port H reset + name: IOPHRST +fieldset/IOPSMEN: + description: GPIO clock enable in sleep mode register + fields: + - bit_offset: 0 + bit_size: 1 + description: Port A clock enable during Sleep mode bit + name: IOPASMEN + - bit_offset: 1 + bit_size: 1 + description: Port B clock enable during Sleep mode bit + name: IOPBSMEN + - bit_offset: 2 + bit_size: 1 + description: Port C clock enable during Sleep mode bit + name: IOPCSMEN + - bit_offset: 3 + bit_size: 1 + description: Port D clock enable during Sleep mode bit + name: IOPDSMEN + - bit_offset: 4 + bit_size: 1 + description: Port E clock enable during Sleep mode bit + name: IOPESMEN + - bit_offset: 7 + bit_size: 1 + description: Port H clock enable during Sleep mode bit + name: IOPHSMEN diff --git a/data/registers/rcc_l4.yaml b/data/registers/rcc_l4.yaml new file mode 100644 index 0000000..86b66ca --- /dev/null +++ b/data/registers/rcc_l4.yaml @@ -0,0 +1,1778 @@ +block/RCC: + description: Reset and clock control + items: + - byte_offset: 0 + description: Clock control register + fieldset: CR + name: CR + - byte_offset: 4 + description: Internal clock sources calibration register + fieldset: ICSCR + name: ICSCR + - byte_offset: 8 + description: Clock configuration register + fieldset: CFGR + name: CFGR + - byte_offset: 12 + description: PLL configuration register + fieldset: PLLCFGR + name: PLLCFGR + - byte_offset: 16 + description: PLLSAI1 configuration register + fieldset: PLLSAI1CFGR + name: PLLSAI1CFGR + - byte_offset: 20 + description: PLLSAI2 configuration register + fieldset: PLLSAI2CFGR + name: PLLSAI2CFGR + - byte_offset: 24 + description: Clock interrupt enable register + fieldset: CIER + name: CIER + - access: Read + byte_offset: 28 + description: Clock interrupt flag register + fieldset: CIFR + name: CIFR + - access: Write + byte_offset: 32 + description: Clock interrupt clear register + fieldset: CICR + name: CICR + - byte_offset: 40 + description: AHB1 peripheral reset register + fieldset: AHB1RSTR + name: AHB1RSTR + - byte_offset: 44 + description: AHB2 peripheral reset register + fieldset: AHB2RSTR + name: AHB2RSTR + - byte_offset: 48 + description: AHB3 peripheral reset register + fieldset: AHB3RSTR + name: AHB3RSTR + - byte_offset: 56 + description: APB1 peripheral reset register 1 + fieldset: APB1RSTR1 + name: APB1RSTR1 + - byte_offset: 60 + description: APB1 peripheral reset register 2 + fieldset: APB1RSTR2 + name: APB1RSTR2 + - byte_offset: 64 + description: APB2 peripheral reset register + fieldset: APB2RSTR + name: APB2RSTR + - byte_offset: 72 + description: AHB1 peripheral clock enable register + fieldset: AHB1ENR + name: AHB1ENR + - byte_offset: 76 + description: AHB2 peripheral clock enable register + fieldset: AHB2ENR + name: AHB2ENR + - byte_offset: 80 + description: AHB3 peripheral clock enable register + fieldset: AHB3ENR + name: AHB3ENR + - byte_offset: 88 + description: APB1ENR1 + fieldset: APB1ENR1 + name: APB1ENR1 + - byte_offset: 92 + description: APB1 peripheral clock enable register 2 + fieldset: APB1ENR2 + name: APB1ENR2 + - byte_offset: 96 + description: APB2ENR + fieldset: APB2ENR + name: APB2ENR + - byte_offset: 104 + description: AHB1 peripheral clocks enable in Sleep and Stop modes register + fieldset: AHB1SMENR + name: AHB1SMENR + - byte_offset: 108 + description: AHB2 peripheral clocks enable in Sleep and Stop modes register + fieldset: AHB2SMENR + name: AHB2SMENR + - byte_offset: 112 + description: AHB3 peripheral clocks enable in Sleep and Stop modes register + fieldset: AHB3SMENR + name: AHB3SMENR + - byte_offset: 120 + description: APB1SMENR1 + fieldset: APB1SMENR1 + name: APB1SMENR1 + - byte_offset: 124 + description: APB1 peripheral clocks enable in Sleep and Stop modes register 2 + fieldset: APB1SMENR2 + name: APB1SMENR2 + - byte_offset: 128 + description: APB2SMENR + fieldset: APB2SMENR + name: APB2SMENR + - byte_offset: 136 + description: CCIPR + fieldset: CCIPR + name: CCIPR + - byte_offset: 144 + description: BDCR + fieldset: BDCR + name: BDCR + - byte_offset: 148 + description: CSR + fieldset: CSR + name: CSR + - byte_offset: 152 + description: Clock recovery RC register + fieldset: CRRCR + name: CRRCR + - byte_offset: 156 + description: Peripherals independent clock configuration register + fieldset: CCIPR2 + name: CCIPR2 +enum/MSIRANGE: + bit_size: 4 + variants: + - description: range 0 around 100 kHz + name: Range100K + value: 0 + - description: range 1 around 200 kHz + name: Range200K + value: 1 + - description: range 2 around 400 kHz + name: Range400K + value: 2 + - description: range 3 around 800 kHz + name: Range800K + value: 3 + - description: range 4 around 1 MHz + name: Range1M + value: 4 + - description: range 5 around 2 MHz + name: Range2M + value: 5 + - description: range 6 around 4 MHz + name: Range4M + value: 6 + - description: range 7 around 8 MHz + name: Range8M + value: 7 + - description: range 8 around 16 MHz + name: Range16M + value: 8 + - description: range 9 around 24 MHz + name: Range24M + value: 9 + - description: range 10 around 32 MHz + name: Range32M + value: 10 + - description: range 11 around 48 MHz + name: Range48M + value: 11 +fieldset/AHB1ENR: + description: AHB1 peripheral clock enable register + fields: + - bit_offset: 0 + bit_size: 1 + description: DMA1 clock enable + name: DMA1EN + - bit_offset: 1 + bit_size: 1 + description: DMA2 clock enable + name: DMA2EN + - bit_offset: 2 + bit_size: 1 + description: DMAMUX clock enable + name: DMAMUX1EN + - bit_offset: 8 + bit_size: 1 + description: Flash memory interface clock enable + name: FLASHEN + - bit_offset: 12 + bit_size: 1 + description: CRC clock enable + name: CRCEN + - bit_offset: 16 + bit_size: 1 + description: Touch Sensing Controller clock enable + name: TSCEN + - bit_offset: 17 + bit_size: 1 + description: DMA2D clock enable + name: DMA2DEN + - bit_offset: 18 + bit_size: 1 + description: Graphic MMU clock enable + name: GFXMMUEN +fieldset/AHB1RSTR: + description: AHB1 peripheral reset register + fields: + - bit_offset: 0 + bit_size: 1 + description: DMA1 reset + name: DMA1RST + - bit_offset: 1 + bit_size: 1 + description: DMA2 reset + name: DMA2RST + - bit_offset: 2 + bit_size: 1 + description: DMAMUXRST + name: DMAMUX1RST + - bit_offset: 8 + bit_size: 1 + description: Flash memory interface reset + name: FLASHRST + - bit_offset: 12 + bit_size: 1 + description: CRC reset + name: CRCRST + - bit_offset: 16 + bit_size: 1 + description: Touch Sensing Controller reset + name: TSCRST + - bit_offset: 17 + bit_size: 1 + description: DMA2D reset + name: DMA2DRST + - bit_offset: 18 + bit_size: 1 + description: GFXMMU reset + name: GFXMMURST +fieldset/AHB1SMENR: + description: AHB1 peripheral clocks enable in Sleep and Stop modes register + fields: + - bit_offset: 0 + bit_size: 1 + description: DMA1 clocks enable during Sleep and Stop modes + name: DMA1SMEN + - bit_offset: 1 + bit_size: 1 + description: DMA2 clocks enable during Sleep and Stop modes + name: DMA2SMEN + - bit_offset: 2 + bit_size: 1 + description: DMAMUX clock enable during Sleep and Stop modes + name: DMAMUX1SMEN + - bit_offset: 8 + bit_size: 1 + description: Flash memory interface clocks enable during Sleep and Stop modes + name: FLASHSMEN + - bit_offset: 9 + bit_size: 1 + description: SRAM1 interface clocks enable during Sleep and Stop modes + name: SRAM1SMEN + - bit_offset: 12 + bit_size: 1 + description: CRCSMEN + name: CRCSMEN + - bit_offset: 16 + bit_size: 1 + description: Touch Sensing Controller clocks enable during Sleep and Stop modes + name: TSCSMEN + - bit_offset: 17 + bit_size: 1 + description: DMA2D clock enable during Sleep and Stop modes + name: DMA2DSMEN + - bit_offset: 18 + bit_size: 1 + description: GFXMMU clock enable during Sleep and Stop modes + name: GFXMMUSMEN +fieldset/AHB2ENR: + description: AHB2 peripheral clock enable register + fields: + - bit_offset: 0 + bit_size: 1 + description: IO port A clock enable + name: GPIOAEN + - bit_offset: 1 + bit_size: 1 + description: IO port B clock enable + name: GPIOBEN + - bit_offset: 2 + bit_size: 1 + description: IO port C clock enable + name: GPIOCEN + - bit_offset: 3 + bit_size: 1 + description: IO port D clock enable + name: GPIODEN + - bit_offset: 4 + bit_size: 1 + description: IO port E clock enable + name: GPIOEEN + - bit_offset: 5 + bit_size: 1 + description: IO port F clock enable + name: GPIOFEN + - bit_offset: 6 + bit_size: 1 + description: IO port G clock enable + name: GPIOGEN + - bit_offset: 7 + bit_size: 1 + description: IO port H clock enable + name: GPIOHEN + - bit_offset: 8 + bit_size: 1 + description: IO port I clock enable + name: GPIOIEN + - bit_offset: 12 + bit_size: 1 + description: OTG full speed clock enable + name: OTGFSEN + - bit_offset: 13 + bit_size: 1 + description: ADC clock enable + name: ADCEN + - bit_offset: 14 + bit_size: 1 + description: DCMI clock enable + name: DCMIEN + - bit_offset: 16 + bit_size: 1 + description: AES accelerator clock enable + name: AESEN + - bit_offset: 17 + bit_size: 1 + description: HASH clock enable + name: HASHEN + - bit_offset: 17 + bit_size: 1 + description: HASH clock enable + name: HASH1EN + - bit_offset: 18 + bit_size: 1 + description: Random Number Generator clock enable + name: RNGEN + - bit_offset: 20 + bit_size: 1 + description: OctoSPI IO manager clock enable + name: OSPIMEN + - bit_offset: 22 + bit_size: 1 + description: SDMMC1 clock enable + name: SDMMC1EN +fieldset/AHB2RSTR: + description: AHB2 peripheral reset register + fields: + - bit_offset: 0 + bit_size: 1 + description: IO port A reset + name: GPIOARST + - bit_offset: 1 + bit_size: 1 + description: IO port B reset + name: GPIOBRST + - bit_offset: 2 + bit_size: 1 + description: IO port C reset + name: GPIOCRST + - bit_offset: 3 + bit_size: 1 + description: IO port D reset + name: GPIODRST + - bit_offset: 4 + bit_size: 1 + description: IO port E reset + name: GPIOERST + - bit_offset: 5 + bit_size: 1 + description: IO port F reset + name: GPIOFRST + - bit_offset: 6 + bit_size: 1 + description: IO port G reset + name: GPIOGRST + - bit_offset: 7 + bit_size: 1 + description: IO port H reset + name: GPIOHRST + - bit_offset: 8 + bit_size: 1 + description: IO port I reset + name: GPIOIRST + - bit_offset: 12 + bit_size: 1 + description: USB OTG FS reset + name: OTGFSRST + - bit_offset: 13 + bit_size: 1 + description: ADC reset + name: ADCRST + - bit_offset: 14 + bit_size: 1 + description: Digital Camera Interface reset + name: DCMIRST + - bit_offset: 16 + bit_size: 1 + description: AES hardware accelerator reset + name: AESRST + - bit_offset: 17 + bit_size: 1 + description: Hash reset + name: HASHRST + - bit_offset: 17 + bit_size: 1 + description: Hash reset + name: HASH1RST + - bit_offset: 18 + bit_size: 1 + description: Random number generator reset + name: RNGRST + - bit_offset: 20 + bit_size: 1 + description: OCTOSPI IO manager reset + name: OSPIMRST + - bit_offset: 22 + bit_size: 1 + description: SDMMC1 reset + name: SDMMC1RST +fieldset/AHB2SMENR: + description: AHB2 peripheral clocks enable in Sleep and Stop modes register + fields: + - bit_offset: 0 + bit_size: 1 + description: IO port A clocks enable during Sleep and Stop modes + name: GPIOASMEN + - bit_offset: 1 + bit_size: 1 + description: IO port B clocks enable during Sleep and Stop modes + name: GPIOBSMEN + - bit_offset: 2 + bit_size: 1 + description: IO port C clocks enable during Sleep and Stop modes + name: GPIOCSMEN + - bit_offset: 3 + bit_size: 1 + description: IO port D clocks enable during Sleep and Stop modes + name: GPIODSMEN + - bit_offset: 4 + bit_size: 1 + description: IO port E clocks enable during Sleep and Stop modes + name: GPIOESMEN + - bit_offset: 5 + bit_size: 1 + description: IO port F clocks enable during Sleep and Stop modes + name: GPIOFSMEN + - bit_offset: 6 + bit_size: 1 + description: IO port G clocks enable during Sleep and Stop modes + name: GPIOGSMEN + - bit_offset: 7 + bit_size: 1 + description: IO port H clocks enable during Sleep and Stop modes + name: GPIOHSMEN + - bit_offset: 8 + bit_size: 1 + description: IO port I clocks enable during Sleep and Stop modes + name: GPIOISMEN + - bit_offset: 9 + bit_size: 1 + description: SRAM2 interface clocks enable during Sleep and Stop modes + name: SRAM2SMEN + - bit_offset: 10 + bit_size: 1 + description: SRAM2 interface clocks enable during Sleep and Stop modes + name: SRAM3SMEN + - bit_offset: 12 + bit_size: 1 + description: OTG full speed clocks enable during Sleep and Stop modes + name: OTGFSSMEN + - bit_offset: 13 + bit_size: 1 + description: ADC clocks enable during Sleep and Stop modes + name: ADCFSSMEN + - bit_offset: 14 + bit_size: 1 + description: DCMI clock enable during Sleep and Stop modes + name: DCMISMEN + - bit_offset: 16 + bit_size: 1 + description: AES accelerator clocks enable during Sleep and Stop modes + name: AESSMEN + - bit_offset: 17 + bit_size: 1 + description: HASH clock enable during Sleep and Stop modes + name: HASHSMEN + - bit_offset: 17 + bit_size: 1 + description: HASH clock enable during Sleep and Stop modes + name: HASH1SMEN + - bit_offset: 18 + bit_size: 1 + description: Random Number Generator clocks enable during Sleep and Stop modes + name: RNGSMEN + - bit_offset: 20 + bit_size: 1 + description: OctoSPI IO manager clocks enable during Sleep and Stop modes + name: OSPIMSMEN + - bit_offset: 22 + bit_size: 1 + description: SDMMC1 clocks enable during Sleep and Stop modes + name: SDMMC1SMEN +fieldset/AHB3ENR: + description: AHB3 peripheral clock enable register + fields: + - bit_offset: 0 + bit_size: 1 + description: Flexible memory controller clock enable + name: FMCEN + - bit_offset: 8 + bit_size: 1 + description: QSPIEN + name: QSPIEN + - bit_offset: 9 + bit_size: 1 + description: OSPI2EN memory interface clock enable + name: OSPI2EN +fieldset/AHB3RSTR: + description: AHB3 peripheral reset register + fields: + - bit_offset: 0 + bit_size: 1 + description: Flexible memory controller reset + name: FMCRST + - bit_offset: 8 + bit_size: 1 + description: Quad SPI memory interface reset + name: QSPIRST + - bit_offset: 9 + bit_size: 1 + description: OctOSPI2 memory interface reset + name: OSPI2RST +fieldset/AHB3SMENR: + description: AHB3 peripheral clocks enable in Sleep and Stop modes register + fields: + - bit_offset: 0 + bit_size: 1 + description: Flexible memory controller clocks enable during Sleep and Stop modes + name: FMCSMEN + - bit_offset: 8 + bit_size: 1 + description: QSPISMEN + name: QSPISMEN + - bit_offset: 9 + bit_size: 1 + description: OctoSPI2 memory interface clocks enable during Sleep and Stop modes + name: OCTOSPI2 +fieldset/APB1ENR1: + description: APB1ENR1 + fields: + - bit_offset: 0 + bit_size: 1 + description: TIM2 timer clock enable + name: TIM2EN + - bit_offset: 1 + bit_size: 1 + description: TIM3 timer clock enable + name: TIM3EN + - bit_offset: 2 + bit_size: 1 + description: TIM4 timer clock enable + name: TIM4EN + - bit_offset: 3 + bit_size: 1 + description: TIM5 timer clock enable + name: TIM5EN + - bit_offset: 4 + bit_size: 1 + description: TIM6 timer clock enable + name: TIM6EN + - bit_offset: 5 + bit_size: 1 + description: TIM7 timer clock enable + name: TIM7EN + - bit_offset: 9 + bit_size: 1 + description: LCD clock enable + name: LCDEN + - bit_offset: 10 + bit_size: 1 + description: RTC APB clock enable + name: RTCAPBEN + - bit_offset: 11 + bit_size: 1 + description: Window watchdog clock enable + name: WWDGEN + - bit_offset: 14 + bit_size: 1 + description: SPI2 clock enable + name: SPI2EN + - bit_offset: 15 + bit_size: 1 + description: SPI peripheral 3 clock enable + name: SPI3EN + - bit_offset: 15 + bit_size: 1 + description: SPI3 clock enable + name: SP3EN + - bit_offset: 17 + bit_size: 1 + description: USART2 clock enable + name: USART2EN + - bit_offset: 18 + bit_size: 1 + description: USART3 clock enable + name: USART3EN + - bit_offset: 18 + bit_size: 1 + description: USART1 clock enable + name: USART1EN + - bit_offset: 19 + bit_size: 1 + description: UART4 clock enable + name: UART4EN + - bit_offset: 20 + bit_size: 1 + description: UART5 clock enable + name: UART5EN + - bit_offset: 21 + bit_size: 1 + description: I2C1 clock enable + name: I2C1EN + - bit_offset: 22 + bit_size: 1 + description: I2C2 clock enable + name: I2C2EN + - bit_offset: 23 + bit_size: 1 + description: I2C3 clock enable + name: I2C3EN + - bit_offset: 24 + bit_size: 1 + description: Clock Recovery System clock enable + name: CRSEN + - bit_offset: 25 + bit_size: 1 + description: CAN1 clock enable + name: CAN1EN + - bit_offset: 26 + bit_size: 1 + description: USB FS clock enable + name: USBF + - bit_offset: 26 + bit_size: 1 + description: USB FS clock enable + name: USBFSEN + - bit_offset: 26 + bit_size: 1 + description: CAN2 clock enable + name: CAN2EN + - bit_offset: 28 + bit_size: 1 + description: Power interface clock enable + name: PWREN + - bit_offset: 29 + bit_size: 1 + description: DAC1 interface clock enable + name: DAC1EN + - bit_offset: 30 + bit_size: 1 + description: OPAMP interface clock enable + name: OPAMPEN + - bit_offset: 31 + bit_size: 1 + description: Low power timer 1 clock enable + name: LPTIM1EN +fieldset/APB1ENR2: + description: APB1 peripheral clock enable register 2 + fields: + - bit_offset: 0 + bit_size: 1 + description: Low power UART 1 clock enable + name: LPUART1EN + - bit_offset: 1 + bit_size: 1 + description: I2C4 clock enable + name: I2C4EN + - bit_offset: 2 + bit_size: 1 + description: Single wire protocol clock enable + name: SWPMI1EN + - bit_offset: 5 + bit_size: 1 + description: LPTIM2EN + name: LPTIM2EN + - bit_offset: 24 + bit_size: 1 + description: DFSDMEN enable + name: DFSDMEN +fieldset/APB1RSTR1: + description: APB1 peripheral reset register 1 + fields: + - bit_offset: 0 + bit_size: 1 + description: TIM2 timer reset + name: TIM2RST + - bit_offset: 1 + bit_size: 1 + description: TIM3 timer reset + name: TIM3RST + - bit_offset: 2 + bit_size: 1 + description: TIM3 timer reset + name: TIM4RST + - bit_offset: 3 + bit_size: 1 + description: TIM5 timer reset + name: TIM5RST + - bit_offset: 4 + bit_size: 1 + description: TIM6 timer reset + name: TIM6RST + - bit_offset: 5 + bit_size: 1 + description: TIM7 timer reset + name: TIM7RST + - bit_offset: 9 + bit_size: 1 + description: LCD interface reset + name: LCDRST + - bit_offset: 14 + bit_size: 1 + description: SPI2 reset + name: SPI2RST + - bit_offset: 15 + bit_size: 1 + description: SPI3 reset + name: SPI3RST + - bit_offset: 17 + bit_size: 1 + description: USART2 reset + name: USART2RST + - bit_offset: 18 + bit_size: 1 + description: USART3 reset + name: USART3RST + - bit_offset: 19 + bit_size: 1 + description: UART4 reset + name: UART4RST + - bit_offset: 19 + bit_size: 1 + description: USART4 reset. + name: USART4RST + - bit_offset: 20 + bit_size: 1 + description: UART5 reset + name: UART5RST + - bit_offset: 21 + bit_size: 1 + description: I2C1 reset + name: I2C1RST + - bit_offset: 22 + bit_size: 1 + description: I2C2 reset + name: I2C2RST + - bit_offset: 23 + bit_size: 1 + description: I2C3 reset + name: I2C3RST + - bit_offset: 24 + bit_size: 1 + description: CRS reset + name: CRSRST + - bit_offset: 25 + bit_size: 1 + description: CAN1 reset + name: CAN1RST + - bit_offset: 26 + bit_size: 1 + description: USB FS reset + name: USBFSRST + - bit_offset: 26 + bit_size: 1 + description: CAN2 reset + name: CAN2RST + - bit_offset: 28 + bit_size: 1 + description: Power interface reset + name: PWRRST + - bit_offset: 29 + bit_size: 1 + description: DAC1 interface reset + name: DAC1RST + - bit_offset: 30 + bit_size: 1 + description: OPAMP interface reset + name: OPAMPRST + - bit_offset: 31 + bit_size: 1 + description: Low Power Timer 1 reset + name: LPTIM1RST +fieldset/APB1RSTR2: + description: APB1 peripheral reset register 2 + fields: + - bit_offset: 0 + bit_size: 1 + description: Low-power UART 1 reset + name: LPUART1RST + - bit_offset: 1 + bit_size: 1 + description: I2C4 reset + name: I2C4RST + - bit_offset: 2 + bit_size: 1 + description: Single wire protocol reset + name: SWPMI1RST + - bit_offset: 5 + bit_size: 1 + description: Low-power timer 2 reset + name: LPTIM2RST +fieldset/APB1SMENR1: + description: APB1SMENR1 + fields: + - bit_offset: 0 + bit_size: 1 + description: TIM2 timer clocks enable during Sleep and Stop modes + name: TIM2SMEN + - bit_offset: 1 + bit_size: 1 + description: TIM3 timer clocks enable during Sleep and Stop modes + name: TIM3SMEN + - bit_offset: 2 + bit_size: 1 + description: TIM4 timer clocks enable during Sleep and Stop modes + name: TIM4SMEN + - bit_offset: 3 + bit_size: 1 + description: TIM5 timer clocks enable during Sleep and Stop modes + name: TIM5SMEN + - bit_offset: 4 + bit_size: 1 + description: TIM6 timer clocks enable during Sleep and Stop modes + name: TIM6SMEN + - bit_offset: 5 + bit_size: 1 + description: TIM7 timer clocks enable during Sleep and Stop modes + name: TIM7SMEN + - bit_offset: 9 + bit_size: 1 + description: LCD clocks enable during Sleep and Stop modes + name: LCDSMEN + - bit_offset: 10 + bit_size: 1 + description: RTC APB clock enable during Sleep and Stop modes + name: RTCAPBSMEN + - bit_offset: 11 + bit_size: 1 + description: Window watchdog clocks enable during Sleep and Stop modes + name: WWDGSMEN + - bit_offset: 14 + bit_size: 1 + description: SPI2 clocks enable during Sleep and Stop modes + name: SPI2SMEN + - bit_offset: 15 + bit_size: 1 + description: SPI3 clocks enable during Sleep and Stop modes + name: SP3SMEN + - bit_offset: 17 + bit_size: 1 + description: USART2 clocks enable during Sleep and Stop modes + name: USART2SMEN + - bit_offset: 17 + bit_size: 1 + description: USART1 clocks enable during Sleep and Stop modes + name: USART1SMEN + - bit_offset: 18 + bit_size: 1 + description: USART3 clocks enable during Sleep and Stop modes + name: USART3SMEN + - bit_offset: 19 + bit_size: 1 + description: UART4 clocks enable during Sleep and Stop modes + name: UART4SMEN + - bit_offset: 19 + bit_size: 1 + description: USART2 clocks enable during Sleep and Stop modes + name: USART4SMEN + - bit_offset: 20 + bit_size: 1 + description: UART5 clocks enable during Sleep and Stop modes + name: UART5SMEN + - bit_offset: 21 + bit_size: 1 + description: I2C1 clocks enable during Sleep and Stop modes + name: I2C1SMEN + - bit_offset: 22 + bit_size: 1 + description: I2C2 clocks enable during Sleep and Stop modes + name: I2C2SMEN + - bit_offset: 23 + bit_size: 1 + description: I2C3 clocks enable during Sleep and Stop modes + name: I2C3SMEN + - bit_offset: 24 + bit_size: 1 + description: CRS clock enable during Sleep and Stop modes + name: CRSSMEN + - bit_offset: 25 + bit_size: 1 + description: CAN1 clocks enable during Sleep and Stop modes + name: CAN1SMEN + - bit_offset: 26 + bit_size: 1 + description: USB FS clock enable during Sleep and Stop modes + name: USBFSSMEN + - bit_offset: 26 + bit_size: 1 + description: CAN2 clocks enable during Sleep and Stop modes + name: CAN2SMEN + - bit_offset: 28 + bit_size: 1 + description: Power interface clocks enable during Sleep and Stop modes + name: PWRSMEN + - bit_offset: 29 + bit_size: 1 + description: DAC1 interface clocks enable during Sleep and Stop modes + name: DAC1SMEN + - bit_offset: 30 + bit_size: 1 + description: OPAMP interface clocks enable during Sleep and Stop modes + name: OPAMPSMEN + - bit_offset: 31 + bit_size: 1 + description: Low power timer 1 clocks enable during Sleep and Stop modes + name: LPTIM1SMEN +fieldset/APB1SMENR2: + description: APB1 peripheral clocks enable in Sleep and Stop modes register 2 + fields: + - bit_offset: 0 + bit_size: 1 + description: Low power UART 1 clocks enable during Sleep and Stop modes + name: LPUART1SMEN + - bit_offset: 1 + bit_size: 1 + description: I2C4 clocks enable during Sleep and Stop modes + name: I2C4SMEN + - bit_offset: 2 + bit_size: 1 + description: Single wire protocol clocks enable during Sleep and Stop modes + name: SWPMI1SMEN + - bit_offset: 5 + bit_size: 1 + description: LPTIM2SMEN + name: LPTIM2SMEN +fieldset/APB2ENR: + description: APB2ENR + fields: + - bit_offset: 0 + bit_size: 1 + description: SYSCFG clock enable + name: SYSCFGEN + - bit_offset: 7 + bit_size: 1 + description: Firewall clock enable + name: FWEN + - bit_offset: 7 + bit_size: 1 + description: Firewall clock enable + name: FIREWALLEN + - bit_offset: 10 + bit_size: 1 + description: SDMMC clock enable + name: SDMMCEN + - bit_offset: 11 + bit_size: 1 + description: TIM1 timer clock enable + name: TIM1EN + - bit_offset: 12 + bit_size: 1 + description: SPI1 clock enable + name: SPI1EN + - bit_offset: 13 + bit_size: 1 + description: TIM8 timer clock enable + name: TIM8EN + - bit_offset: 14 + bit_size: 1 + description: USART1clock enable + name: USART1EN + - bit_offset: 16 + bit_size: 1 + description: TIM15 timer clock enable + name: TIM15EN + - bit_offset: 17 + bit_size: 1 + description: TIM16 timer clock enable + name: TIM16EN + - bit_offset: 18 + bit_size: 1 + description: TIM17 timer clock enable + name: TIM17EN + - bit_offset: 21 + bit_size: 1 + description: SAI1 clock enable + name: SAI1EN + - bit_offset: 22 + bit_size: 1 + description: SAI2 clock enable + name: SAI2EN + - bit_offset: 24 + bit_size: 1 + description: DFSDM timer clock enable + name: DFSDM1EN + - bit_offset: 24 + bit_size: 1 + description: DFSDM timer clock enable + name: DFSDMEN + - bit_offset: 26 + bit_size: 1 + description: LCD-TFT clock enable + name: LTDCEN + - bit_offset: 27 + bit_size: 1 + description: DSI clock enable + name: DSIEN +fieldset/APB2RSTR: + description: APB2 peripheral reset register + fields: + - bit_offset: 0 + bit_size: 1 + description: System configuration (SYSCFG) reset + name: SYSCFGRST + - bit_offset: 10 + bit_size: 1 + description: SDMMC reset + name: SDMMCRST + - bit_offset: 11 + bit_size: 1 + description: TIM1 timer reset + name: TIM1RST + - bit_offset: 12 + bit_size: 1 + description: SPI1 reset + name: SPI1RST + - bit_offset: 13 + bit_size: 1 + description: TIM8 timer reset + name: TIM8RST + - bit_offset: 14 + bit_size: 1 + description: USART1 reset + name: USART1RST + - bit_offset: 16 + bit_size: 1 + description: TIM15 timer reset + name: TIM15RST + - bit_offset: 17 + bit_size: 1 + description: TIM16 timer reset + name: TIM16RST + - bit_offset: 18 + bit_size: 1 + description: TIM17 timer reset + name: TIM17RST + - bit_offset: 21 + bit_size: 1 + description: Serial audio interface 1 (SAI1) reset + name: SAI1RST + - bit_offset: 22 + bit_size: 1 + description: Serial audio interface 2 (SAI2) reset + name: SAI2RST + - bit_offset: 24 + bit_size: 1 + description: Digital filters for sigma-delata modulators (DFSDM) reset + name: DFSDM1RST + - bit_offset: 24 + bit_size: 1 + description: DFSDM filter reset + name: DFSDMRST + - bit_offset: 26 + bit_size: 1 + description: LCD-TFT reset + name: LTDCRST + - bit_offset: 27 + bit_size: 1 + description: DSI reset + name: DSIRST +fieldset/APB2SMENR: + description: APB2SMENR + fields: + - bit_offset: 0 + bit_size: 1 + description: SYSCFG clocks enable during Sleep and Stop modes + name: SYSCFGSMEN + - bit_offset: 10 + bit_size: 1 + description: SDMMC clocks enable during Sleep and Stop modes + name: SDMMCSMEN + - bit_offset: 11 + bit_size: 1 + description: TIM1 timer clocks enable during Sleep and Stop modes + name: TIM1SMEN + - bit_offset: 12 + bit_size: 1 + description: SPI1 clocks enable during Sleep and Stop modes + name: SPI1SMEN + - bit_offset: 13 + bit_size: 1 + description: TIM8 timer clocks enable during Sleep and Stop modes + name: TIM8SMEN + - bit_offset: 14 + bit_size: 1 + description: USART1clocks enable during Sleep and Stop modes + name: USART1SMEN + - bit_offset: 16 + bit_size: 1 + description: TIM15 timer clocks enable during Sleep and Stop modes + name: TIM15SMEN + - bit_offset: 17 + bit_size: 1 + description: TIM16 timer clocks enable during Sleep and Stop modes + name: TIM16SMEN + - bit_offset: 18 + bit_size: 1 + description: TIM17 timer clocks enable during Sleep and Stop modes + name: TIM17SMEN + - bit_offset: 21 + bit_size: 1 + description: SAI1 clocks enable during Sleep and Stop modes + name: SAI1SMEN + - bit_offset: 22 + bit_size: 1 + description: SAI2 clocks enable during Sleep and Stop modes + name: SAI2SMEN + - bit_offset: 24 + bit_size: 1 + description: DFSDM timer clocks enable during Sleep and Stop modes + name: DFSDM1SMEN + - bit_offset: 24 + bit_size: 1 + description: DFSDM timer clocks enable during Sleep and Stop modes + name: DFSDMSMEN + - bit_offset: 26 + bit_size: 1 + description: LCD-TFT timer clocks enable during Sleep and Stop modes + name: LTDCSMEN + - bit_offset: 27 + bit_size: 1 + description: DSI clocks enable during Sleep and Stop modes + name: DSISMEN +fieldset/BDCR: + description: BDCR + fields: + - bit_offset: 0 + bit_size: 1 + description: LSE oscillator enable + name: LSEON + - bit_offset: 1 + bit_size: 1 + description: LSE oscillator ready + name: LSERDY + - bit_offset: 2 + bit_size: 1 + description: LSE oscillator bypass + name: LSEBYP + - bit_offset: 3 + bit_size: 2 + description: SE oscillator drive capability + name: LSEDRV + - bit_offset: 5 + bit_size: 1 + description: LSECSSON + name: LSECSSON + - bit_offset: 6 + bit_size: 1 + description: LSECSSD + name: LSECSSD + - bit_offset: 8 + bit_size: 2 + description: RTC clock source selection + name: RTCSEL + - bit_offset: 15 + bit_size: 1 + description: RTC clock enable + name: RTCEN + - bit_offset: 16 + bit_size: 1 + description: Backup domain software reset + name: BDRST + - bit_offset: 24 + bit_size: 1 + description: Low speed clock output enable + name: LSCOEN + - bit_offset: 25 + bit_size: 1 + description: Low speed clock output selection + name: LSCOSEL +fieldset/CCIPR: + description: CCIPR + fields: + - bit_offset: 0 + bit_size: 2 + description: USART1 clock source selection + name: USART1SEL + - bit_offset: 2 + bit_size: 2 + description: USART2 clock source selection + name: USART2SEL + - bit_offset: 4 + bit_size: 2 + description: USART3 clock source selection + name: USART3SEL + - bit_offset: 6 + bit_size: 2 + description: UART4 clock source selection + name: UART4SEL + - bit_offset: 6 + bit_size: 2 + description: USART4 clock source selection + name: USART4SEL + - bit_offset: 8 + bit_size: 2 + description: UART5 clock source selection + name: UART5SEL + - bit_offset: 10 + bit_size: 2 + description: LPUART1 clock source selection + name: LPUART1SEL + - bit_offset: 12 + bit_size: 2 + description: I2C1 clock source selection + name: I2C1SEL + - bit_offset: 14 + bit_size: 2 + description: I2C2 clock source selection + name: I2C2SEL + - bit_offset: 16 + bit_size: 2 + description: I2C3 clock source selection + name: I2C3SEL + - bit_offset: 18 + bit_size: 2 + description: Low power timer 1 clock source selection + name: LPTIM1SEL + - bit_offset: 20 + bit_size: 2 + description: Low power timer 2 clock source selection + name: LPTIM2SEL + - bit_offset: 22 + bit_size: 2 + description: SAI1 clock source selection + name: SAI1SEL + - bit_offset: 24 + bit_size: 2 + description: SAI2 clock source selection + name: SAI2SEL + - bit_offset: 26 + bit_size: 2 + description: 48 MHz clock source selection + name: CLK48SEL + - bit_offset: 28 + bit_size: 2 + description: ADCs clock source selection + name: ADCSEL + - bit_offset: 30 + bit_size: 1 + description: SWPMI1 clock source selection + name: SWPMI1SEL + - bit_offset: 31 + bit_size: 1 + description: DFSDM clock source selection + name: DFSDMSEL +fieldset/CCIPR2: + description: Peripherals independent clock configuration register + fields: + - bit_offset: 0 + bit_size: 2 + description: I2C4 clock source selection + name: I2C4SEL + - bit_offset: 2 + bit_size: 1 + description: Digital filter for sigma delta modulator kernel clock source selection + name: DFSDMSEL + - bit_offset: 3 + bit_size: 2 + description: Digital filter for sigma delta modulator audio clock source selection + name: ADFSDMSEL + - bit_offset: 5 + bit_size: 3 + description: SAI1 clock source selection + name: SAI1SEL + - bit_offset: 8 + bit_size: 3 + description: SAI2 clock source selection + name: SAI2SEL + - bit_offset: 12 + bit_size: 1 + description: clock selection + name: DSISEL + - bit_offset: 14 + bit_size: 1 + description: SDMMC clock selection + name: SDMMCSEL + - bit_offset: 16 + bit_size: 2 + description: division factor for LTDC clock + name: PLLSAI2DIVR + - bit_offset: 20 + bit_size: 2 + description: Octospi clock source selection + name: OSPISEL +fieldset/CFGR: + description: Clock configuration register + fields: + - bit_offset: 0 + bit_size: 2 + description: System clock switch + name: SW + - bit_offset: 2 + bit_size: 2 + description: System clock switch status + name: SWS + - bit_offset: 4 + bit_size: 4 + description: AHB prescaler + name: HPRE + - bit_offset: 8 + bit_size: 3 + description: PB low-speed prescaler (APB1) + name: PPRE1 + - bit_offset: 11 + bit_size: 3 + description: APB high-speed prescaler (APB2) + name: PPRE2 + - bit_offset: 15 + bit_size: 1 + description: Wakeup from Stop and CSS backup clock selection + name: STOPWUCK + - bit_offset: 24 + bit_size: 3 + description: Microcontroller clock output + name: MCOSEL + - bit_offset: 28 + bit_size: 3 + description: Microcontroller clock output prescaler + name: MCOPRE +fieldset/CICR: + description: Clock interrupt clear register + fields: + - bit_offset: 0 + bit_size: 1 + description: LSI ready interrupt clear + name: LSIRDYC + - bit_offset: 1 + bit_size: 1 + description: LSE ready interrupt clear + name: LSERDYC + - bit_offset: 2 + bit_size: 1 + description: MSI ready interrupt clear + name: MSIRDYC + - bit_offset: 3 + bit_size: 1 + description: HSI ready interrupt clear + name: HSIRDYC + - bit_offset: 4 + bit_size: 1 + description: HSE ready interrupt clear + name: HSERDYC + - bit_offset: 5 + bit_size: 1 + description: PLL ready interrupt clear + name: PLLRDYC + - bit_offset: 6 + bit_size: 1 + description: PLLSAI1 ready interrupt clear + name: PLLSAI1RDYC + - bit_offset: 7 + bit_size: 1 + description: PLLSAI2 ready interrupt clear + name: PLLSAI2RDYC + - bit_offset: 8 + bit_size: 1 + description: Clock security system interrupt clear + name: CSSC + - bit_offset: 9 + bit_size: 1 + description: LSE Clock security system interrupt clear + name: LSECSSC + - bit_offset: 10 + bit_size: 1 + description: HSI48 oscillator ready interrupt clear + name: HSI48RDYC +fieldset/CIER: + description: Clock interrupt enable register + fields: + - bit_offset: 0 + bit_size: 1 + description: LSI ready interrupt enable + name: LSIRDYIE + - bit_offset: 1 + bit_size: 1 + description: LSE ready interrupt enable + name: LSERDYIE + - bit_offset: 2 + bit_size: 1 + description: MSI ready interrupt enable + name: MSIRDYIE + - bit_offset: 3 + bit_size: 1 + description: HSI ready interrupt enable + name: HSIRDYIE + - bit_offset: 4 + bit_size: 1 + description: HSE ready interrupt enable + name: HSERDYIE + - bit_offset: 5 + bit_size: 1 + description: PLL ready interrupt enable + name: PLLRDYIE + - bit_offset: 6 + bit_size: 1 + description: PLLSAI1 ready interrupt enable + name: PLLSAI1RDYIE + - bit_offset: 7 + bit_size: 1 + description: PLLSAI2 ready interrupt enable + name: PLLSAI2RDYIE + - bit_offset: 9 + bit_size: 1 + description: LSE clock security system interrupt enable + name: LSECSSIE + - bit_offset: 10 + bit_size: 1 + description: HSI48 ready interrupt enable + name: HSI48RDYIE +fieldset/CIFR: + description: Clock interrupt flag register + fields: + - bit_offset: 0 + bit_size: 1 + description: LSI ready interrupt flag + name: LSIRDYF + - bit_offset: 1 + bit_size: 1 + description: LSE ready interrupt flag + name: LSERDYF + - bit_offset: 2 + bit_size: 1 + description: MSI ready interrupt flag + name: MSIRDYF + - bit_offset: 3 + bit_size: 1 + description: HSI ready interrupt flag + name: HSIRDYF + - bit_offset: 4 + bit_size: 1 + description: HSE ready interrupt flag + name: HSERDYF + - bit_offset: 5 + bit_size: 1 + description: PLL ready interrupt flag + name: PLLRDYF + - bit_offset: 6 + bit_size: 1 + description: PLLSAI1 ready interrupt flag + name: PLLSAI1RDYF + - bit_offset: 7 + bit_size: 1 + description: PLLSAI2 ready interrupt flag + name: PLLSAI2RDYF + - bit_offset: 8 + bit_size: 1 + description: Clock security system interrupt flag + name: CSSF + - bit_offset: 9 + bit_size: 1 + description: LSE Clock security system interrupt flag + name: LSECSSF + - bit_offset: 10 + bit_size: 1 + description: HSI48 ready interrupt flag + name: HSI48RDYF +fieldset/CR: + description: Clock control register + fields: + - bit_offset: 0 + bit_size: 1 + description: MSI clock enable + name: MSION + - bit_offset: 1 + bit_size: 1 + description: MSI clock ready flag + name: MSIRDY + - bit_offset: 2 + bit_size: 1 + description: MSI clock PLL enable + name: MSIPLLEN + - bit_offset: 3 + bit_size: 1 + description: MSI clock range selection + name: MSIRGSEL + - bit_offset: 4 + bit_size: 4 + description: MSI clock ranges + enum: MSIRANGE + name: MSIRANGE + - bit_offset: 8 + bit_size: 1 + description: HSI clock enable + name: HSION + - bit_offset: 9 + bit_size: 1 + description: HSI always enable for peripheral kernels + name: HSIKERON + - bit_offset: 10 + bit_size: 1 + description: HSI clock ready flag + name: HSIRDY + - bit_offset: 11 + bit_size: 1 + description: HSI automatic start from Stop + name: HSIASFS + - bit_offset: 16 + bit_size: 1 + description: HSE clock enable + name: HSEON + - bit_offset: 17 + bit_size: 1 + description: HSE clock ready flag + name: HSERDY + - bit_offset: 18 + bit_size: 1 + description: HSE crystal oscillator bypass + name: HSEBYP + - bit_offset: 19 + bit_size: 1 + description: Clock security system enable + name: CSSON + - bit_offset: 24 + bit_size: 1 + description: Main PLL enable + name: PLLON + - bit_offset: 25 + bit_size: 1 + description: Main PLL clock ready flag + name: PLLRDY + - bit_offset: 26 + bit_size: 1 + description: SAI1 PLL enable + name: PLLSAI1ON + - bit_offset: 27 + bit_size: 1 + description: SAI1 PLL clock ready flag + name: PLLSAI1RDY + - bit_offset: 28 + bit_size: 1 + description: SAI2 PLL enable + name: PLLSAI2ON + - bit_offset: 29 + bit_size: 1 + description: SAI2 PLL clock ready flag + name: PLLSAI2RDY +fieldset/CRRCR: + description: Clock recovery RC register + fields: + - bit_offset: 0 + bit_size: 1 + description: HSI48 clock enable + name: HSI48ON + - bit_offset: 1 + bit_size: 1 + description: HSI48 clock ready flag + name: HSI48RDY + - bit_offset: 7 + bit_size: 9 + description: HSI48 clock calibration + name: HSI48CAL +fieldset/CSR: + description: CSR + fields: + - bit_offset: 0 + bit_size: 1 + description: LSI oscillator enable + name: LSION + - bit_offset: 1 + bit_size: 1 + description: LSI oscillator ready + name: LSIRDY + - bit_offset: 8 + bit_size: 4 + description: SI range after Standby mode + name: MSISRANGE + - bit_offset: 23 + bit_size: 1 + description: Remove reset flag + name: RMVF + - bit_offset: 24 + bit_size: 1 + description: Firewall reset flag + name: FWRSTF + - bit_offset: 24 + bit_size: 1 + description: Firewall reset flag + name: FIREWALLRSTF + - bit_offset: 25 + bit_size: 1 + description: Option byte loader reset flag + name: OBLRSTF + - bit_offset: 26 + bit_size: 1 + description: Pin reset flag + name: PINRSTF + - bit_offset: 27 + bit_size: 1 + description: BOR flag + name: BORRSTF + - bit_offset: 28 + bit_size: 1 + description: Software reset flag + name: SFTRSTF + - bit_offset: 29 + bit_size: 1 + description: Independent window watchdog reset flag + name: IWDGRSTF + - bit_offset: 30 + bit_size: 1 + description: Window watchdog reset flag + name: WWDGRSTF + - bit_offset: 31 + bit_size: 1 + description: Low-power reset flag + name: LPWRSTF +fieldset/ICSCR: + description: Internal clock sources calibration register + fields: + - bit_offset: 0 + bit_size: 8 + description: MSI clock calibration + name: MSICAL + - bit_offset: 8 + bit_size: 8 + description: MSI clock trimming + name: MSITRIM + - bit_offset: 16 + bit_size: 8 + description: HSI clock calibration + name: HSICAL + - bit_offset: 24 + bit_size: 7 + description: HSI clock trimming + name: HSITRIM +fieldset/PLLCFGR: + description: PLL configuration register + fields: + - bit_offset: 0 + bit_size: 2 + description: Main PLL, PLLSAI1 and PLLSAI2 entry clock source + name: PLLSRC + - bit_offset: 4 + bit_size: 4 + description: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) + input clock + name: PLLM + - bit_offset: 8 + bit_size: 7 + description: Main PLL multiplication factor for VCO + name: PLLN + - bit_offset: 16 + bit_size: 1 + description: Main PLL PLLSAI3CLK output enable + name: PLLPEN + - bit_offset: 17 + bit_size: 1 + description: Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) + name: PLLP + - bit_offset: 20 + bit_size: 1 + description: Main PLL PLLUSB1CLK output enable + name: PLLQEN + - bit_offset: 21 + bit_size: 2 + description: Main PLL division factor for PLLUSB1CLK(48 MHz clock) + name: PLLQ + - bit_offset: 24 + bit_size: 1 + description: Main PLL PLLCLK output enable + name: PLLREN + - bit_offset: 25 + bit_size: 2 + description: Main PLL division factor for PLLCLK (system clock) + name: PLLR + - bit_offset: 27 + bit_size: 5 + description: Main PLL division factor for PLLSAI2CLK + name: PLLPDIV +fieldset/PLLSAI1CFGR: + description: PLLSAI1 configuration register + fields: + - bit_offset: 4 + bit_size: 4 + description: Division factor for PLLSAI1 input clock + name: PLLSAI1M + - bit_offset: 8 + bit_size: 7 + description: SAI1PLL multiplication factor for VCO + name: PLLSAI1N + - bit_offset: 16 + bit_size: 1 + description: SAI1PLL PLLSAI1CLK output enable + name: PLLSAI1PEN + - bit_offset: 17 + bit_size: 1 + description: SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock) + name: PLLSAI1P + - bit_offset: 20 + bit_size: 1 + description: SAI1PLL PLLUSB2CLK output enable + name: PLLSAI1QEN + - bit_offset: 21 + bit_size: 2 + description: SAI1PLL division factor for PLLUSB2CLK (48 MHz clock) + name: PLLSAI1Q + - bit_offset: 24 + bit_size: 1 + description: PLLSAI1 PLLADC1CLK output enable + name: PLLSAI1REN + - bit_offset: 25 + bit_size: 2 + description: PLLSAI1 division factor for PLLADC1CLK (ADC clock) + name: PLLSAI1R + - bit_offset: 27 + bit_size: 5 + description: PLLSAI1 division factor for PLLSAI1CLK + name: PLLSAI1PDIV +fieldset/PLLSAI2CFGR: + description: PLLSAI2 configuration register + fields: + - bit_offset: 4 + bit_size: 4 + description: Division factor for PLLSAI2 input clock + name: PLLSAI2M + - bit_offset: 8 + bit_size: 7 + description: SAI2PLL multiplication factor for VCO + name: PLLSAI2N + - bit_offset: 16 + bit_size: 1 + description: SAI2PLL PLLSAI2CLK output enable + name: PLLSAI2PEN + - bit_offset: 17 + bit_size: 1 + description: SAI1PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock) + name: PLLSAI2P + - bit_offset: 20 + bit_size: 1 + description: PLLSAI2 division factor for PLLDISCLK + name: PLLSAI2QEN + - bit_offset: 21 + bit_size: 2 + description: SAI2PLL PLLSAI2CLK output enable + name: PLLSAI2Q + - bit_offset: 24 + bit_size: 1 + description: PLLSAI2 PLLADC2CLK output enable + name: PLLSAI2REN + - bit_offset: 25 + bit_size: 2 + description: PLLSAI2 division factor for PLLADC2CLK (ADC clock) + name: PLLSAI2R + - bit_offset: 27 + bit_size: 5 + description: PLLSAI2 division factor for PLLSAI2CLK + name: PLLSAI2PDIV diff --git a/extract.sh b/extract.sh index f2fc555..2f52429 100755 --- a/extract.sh +++ b/extract.sh @@ -6,7 +6,7 @@ board=$1 peri=$2 mkdir -p regs/$peri -cargo build --release --manifest-path ../../../svd2rust/Cargo.toml +cargo build --release --manifest-path ../../svd2rust/Cargo.toml transform="transform.yaml" @@ -28,7 +28,7 @@ for f in `ls $query`; do f=${f#"stm32"} f=${f%".svd"} echo -n processing $f ... - RUST_LOG=info ../../../svd2rust/target/release/svd4rust extract-peripheral --svd sources/svd/stm32$f.svd --transform $transform --peripheral $peri > regs/$peri/$f.yaml 2> regs/$peri/$f.yaml.out + RUST_LOG=info ../../svd2rust/target/release/svd4rust extract-peripheral --svd sources/svd/stm32$f.svd --transform $transform --peripheral $peri > regs/$peri/$f.yaml 2> regs/$peri/$f.yaml.out if [ $? -ne 0 ]; then mv regs/$peri/$f.yaml.out regs/$peri/$f.err rm regs/$peri/$f.yaml diff --git a/merge_regs.py b/merge_regs.py new file mode 100644 index 0000000..f8dbf58 --- /dev/null +++ b/merge_regs.py @@ -0,0 +1,61 @@ +import xmltodict +import yaml +import re +import json +import sys +import os +from collections import OrderedDict +from glob import glob + +def item_key(a): + return int(a["byte_offset"]) + +def field_key(a): + return int(a["bit_offset"]) + +def merge_block(origin, new): + for newval in new: + found = False + for val in origin: + if val["name"] == newval["name"] and val["byte_offset"] == newval["byte_offset"]: + found = True + if not found: + origin.append(newval) + origin.sort(key=item_key) + +def merge_fields(origin, new): + for newval in new: + found = False + for val in origin: + if val["name"] == newval["name"] and val["bit_offset"] == newval["bit_offset"]: + found = True + if not found: + origin.append(newval) + origin.sort(key=field_key) + +def merge_dicts(origin, new): + for k, v in new.items(): + if k in origin: + if type(v) is dict: + merge_dicts(origin[k], v) + elif type(v) is list: + if k == "items": + merge_block(origin[k], v) + if k == "fields": + merge_fields(origin[k], v) + else: + origin[k] = v + else: + origin[k] = v + +first=True +reg_map={} +for regfile in sys.argv[1:]: + print("Loading", regfile) + with open(regfile, 'r') as f: + y = yaml.load(f, Loader=yaml.SafeLoader) + merge_dicts(reg_map, y) + + +with open('regs_merged.yaml', 'w') as f: + f.write(yaml.dump(reg_map)) diff --git a/parse.py b/parse.py index f0e9ea5..13e557f 100644 --- a/parse.py +++ b/parse.py @@ -242,16 +242,26 @@ perimap = [ ('STM32L0.*:SYS:.*', 'syscfg_l0/SYSCFG'), ('STM32H7.*:SYS:.*', 'syscfg_h7/SYSCFG'), ('STM32L0.*:RCC:.*', 'rcc_l0/RCC'), + ('STM32L4.*:RCC:.*', 'rcc_l4/RCC'), + ('STM32F4.*:RCC:.*', 'rcc_f4/RCC'), + ('.*:STM32H7AB_rcc_v1_0', 'rcc_h7ab/RCC'), + ('.*:STM32H7_rcc_v1_0', 'rcc_h7/RCC'), ('.*:STM32L0_dbgmcu_v1_0', 'dbg_l0/DBG'), ('.*:STM32L0_crs_v1_0', 'crs_l0/CRS'), ('.*SDMMC:sdmmc2_v1_0', 'sdmmc_v2/SDMMC'), - ('.*:STM32H7_rcc_v1_0', 'rcc_h7/RCC'), ('.*:STM32H7_pwr_v1_0', 'pwr_h7/PWR'), ('.*:STM32H7_flash_v1_0', 'flash_h7/FLASH'), ('.*:STM32H7_dbgmcu_v1_0', 'dbgmcu_h7/DBGMCU'), ('.*TIM\d.*:gptimer.*', 'timer_v1/TIM_GP16'), ] +rng_clock_map = [ + ('STM32L0.*:RNG:.*', 'AHB'), + ('STM32L4.*:RNG:.*', 'AHB2'), + ('STM32F4.*:RNG:.*', 'AHB2'), + ('STM32H7.*:RNG:.*', 'AHB2'), +] + def match_peri(peri): for r, block in perimap: @@ -266,6 +276,11 @@ def find_af(gpio_af, peri_name, pin_name, signal_name): return af[gpio_af][pin_name][peri_name + '_' + signal_name] return None +def match_rng_clock(rcc): + for r, clock in rng_clock_map: + if re.match(r, rcc): + return clock + return None def parse_headers(): os.makedirs('sources/headers_parsed', exist_ok=True) @@ -458,6 +473,11 @@ def parse_chips(): if len(chip['pins'][pname]) > 0: p['pins'] = chip['pins'][pname] + # RNG Clock definitions are not easily determined, so lookup in mapping + if block is not None and block.startswith("rng_"): + if (clock := match_rng_clock(chip_name+':'+pname+':'+pkind)) != None: + p['clock'] = clock + peris[pname] = p @@ -599,6 +619,7 @@ def parse_clocks(): peripherals = peripherals.split(",") for p in peripherals: chip_clocks[p] = name + clocks[ff] = chip_clocks diff --git a/transform-RCC.yaml b/transform-RCC.yaml index d212685..224a48a 100644 --- a/transform-RCC.yaml +++ b/transform-RCC.yaml @@ -1,4 +1,5 @@ transforms: + - MergeEnums: from: CCMR\d_Input_CC\dS to: CCMR_Input_CCS @@ -10,11 +11,11 @@ transforms: to: $1$2$3 skip_unmergeable: true - - MakeFieldArray: - fieldsets: .* - from: ([A-Z]+)\d+ - to: $1 - allow_cursed: true + #- MakeFieldArray: + # fieldsets: .* + # from: ([A-Z]+)\d([A-Z]*) + # to: $1$2 + # allow_cursed: true - MakeFieldArray: fieldsets: .* from: P\d+WP @@ -41,5 +42,23 @@ transforms: from: '[HL](IFCR|ISR)' to: $1 - DeleteEnums: - from: '.*[EN]' + from: '.*EN' bit_size: 1 + - DeleteEnums: + from: '.*RST' + bit_size: 1 + - DeleteEnums: + from: '.*ON' + bit_size: 1 + - MakeRegisterArray: + blocks: .* + from: PLL\d+(.*) + to: PLL$1 + - MakeFieldArray: + fieldsets: .* + from: PLL\d+(.*) + to: PLL$1 + - MakeFieldArray: + fieldsets: (PLLCFGR|PLLCKSELR) + from: DIV([A-Z]+)\d+([A-Z]*) + to: DIV$1$2