H7 RCC: Make more arrays
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@ -3736,20 +3736,13 @@ fieldset/PLLCFGR:
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len: 3
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stride: 4
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enum: PLL1VCOSEL
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- name: PLL1RGE
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- name: PLLRGE
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description: PLL1 input frequency range
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bit_offset: 2
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bit_size: 2
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enum: PLL1RGE
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- name: PLL2RGE
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description: PLL2 input frequency range
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bit_offset: 6
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bit_size: 2
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enum: PLL1RGE
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- name: PLL3RGE
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description: PLL3 input frequency range
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bit_offset: 10
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bit_size: 2
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array:
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len: 3
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stride: 4
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enum: PLL1RGE
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- name: DIVPEN
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description: PLL1 DIVP divider output enable
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