diff --git a/data/registers/rcc_h7.yaml b/data/registers/rcc_h7.yaml
index fae0ef1..34749b4 100644
--- a/data/registers/rcc_h7.yaml
+++ b/data/registers/rcc_h7.yaml
@@ -3736,20 +3736,13 @@ fieldset/PLLCFGR:
         len: 3
         stride: 4
       enum: PLL1VCOSEL
-    - name: PLL1RGE
+    - name: PLLRGE
       description: PLL1 input frequency range
       bit_offset: 2
       bit_size: 2
-      enum: PLL1RGE
-    - name: PLL2RGE
-      description: PLL2 input frequency range
-      bit_offset: 6
-      bit_size: 2
-      enum: PLL1RGE
-    - name: PLL3RGE
-      description: PLL3 input frequency range
-      bit_offset: 10
-      bit_size: 2
+      array:
+        len: 3
+        stride: 4
       enum: PLL1RGE
     - name: DIVPEN
       description: PLL1 DIVP divider output enable