ADC support for H5
This commit is contained in:
Torin Cooper-Bennun
parent
3e97a2e937
commit
23e9b3a864
557
data/registers/adc_h5.yaml
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557
data/registers/adc_h5.yaml
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block/ADC:
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description: Analog to digital converter
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items:
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- name: ISR
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description: interrupt and status register
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byte_offset: 0
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fieldset: ISR
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- name: IER
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description: interrupt enable register
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byte_offset: 4
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fieldset: IER
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- name: CR
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description: control register
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byte_offset: 8
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fieldset: CR
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- name: CFGR
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description: configuration register
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byte_offset: 12
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fieldset: CFGR
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- name: CFGR2
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description: configuration register 2
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byte_offset: 16
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fieldset: CFGR2
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- name: SMPR1
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description: sample time register 1
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byte_offset: 20
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fieldset: SMPR1
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- name: SMPR2
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description: sample time register 2
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byte_offset: 24
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fieldset: SMPR2
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- name: TR1
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description: watchdog threshold register 1
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byte_offset: 32
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fieldset: TR1
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- name: TR2
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description: watchdog threshold register 2
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byte_offset: 36
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fieldset: TR2
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- name: TR3
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description: watchdog threshold register 3
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byte_offset: 40
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fieldset: TR3
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- name: SQR1
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description: regular sequence register 1
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byte_offset: 48
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fieldset: SQR1
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- name: SQR2
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description: regular sequence register 2
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byte_offset: 52
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fieldset: SQR2
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- name: SQR3
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description: regular sequence register 3
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byte_offset: 56
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fieldset: SQR3
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- name: SQR4
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description: regular sequence register 4
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byte_offset: 60
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fieldset: SQR4
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- name: DR
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description: regular data register
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byte_offset: 64
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fieldset: DR
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- name: JSQR
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description: injected sequence register
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byte_offset: 76
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fieldset: JSQR
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- name: OFR
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description: offset 1-4 register
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array:
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len: 4
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stride: 4
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byte_offset: 96
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fieldset: OFR
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- name: JDR
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description: injected channel 1-4 register
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array:
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len: 4
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stride: 4
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byte_offset: 128
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# access: Read
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fieldset: JDR
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- name: AWD2CR
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description: Analog Watchdog 2 Configuration Register
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byte_offset: 160
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fieldset: AWD2CR
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- name: AWD3CR
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description: Analog Watchdog 3 Configuration Register
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byte_offset: 164
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fieldset: AWD3CR
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- name: DIFSEL
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description: Differential mode Selection Register
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byte_offset: 176
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fieldset: DIFSEL
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- name: CALFACT
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description: Calibration Factors
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byte_offset: 180
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fieldset: CALFACT
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- name: OR
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description: option register
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byte_offset: 200
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fieldset: OR
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fieldset/AWD2CR:
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description: Analog Watchdog 2 Configuration Register
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fields:
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- name: AWD2CH
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description: 'Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2. AWD2CH[i] = 0: analog input channel i is not monitored by AWD2 AWD2CH[i] = 1: analog input channel i is monitored by AWD2 When AWD2CH[19:0] = 000..0, the analog Watchdog 2 is disabled Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers. The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically and must not be selected for the analog watchdog.'
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bit_offset: 0
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bit_size: 20
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fieldset/AWD3CR:
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description: Analog Watchdog 3 Configuration Register
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fields:
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- name: AWD3CH
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description: 'Analog watchdog 3 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 3. AWD3CH[i] = 0: analog input channel i is not monitored by AWD3 AWD3CH[i] = 1: analog input channel i is monitored by AWD3 When AWD3CH[19:0] = 000..0, the analog Watchdog 3 is disabled Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers. The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically and must not be selected for the analog watchdog.'
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bit_offset: 0
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bit_size: 20
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fieldset/CALFACT:
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description: Calibration Factors
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fields:
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- name: CALFACT_S
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description: 'Calibration Factors In Single-ended mode These bits are written by hardware or by software. Once a single-ended inputs calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new single-ended calibration is launched. Note: The software is allowed to write these bits only when ADEN = 1, ADSTART = 0 and JADSTART = 0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing).'
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bit_offset: 0
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bit_size: 7
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- name: CALFACT_D
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description: 'Calibration Factors in differential mode These bits are written by hardware or by software. Once a differential inputs calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new differential calibration is launched. Note: The software is allowed to write these bits only when ADEN = 1, ADSTART = 0 and JADSTART = 0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing).'
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bit_offset: 16
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bit_size: 7
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fieldset/CFGR:
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description: configuration register
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fields:
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- name: DMAEN
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description: 'Direct memory access enable This bit is set and cleared by software to enable the generation of DMA requests. This allows to use the DMA to manage automatically the converted data. For more details, refer to conversions using the DMA. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).'
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bit_offset: 0
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bit_size: 1
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- name: DMACFG
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description: 'Direct memory access configuration This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1. For more details, refer to Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).'
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bit_offset: 1
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bit_size: 1
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- name: RES
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description: 'Data resolution These bits are written by software to select the resolution of the conversion. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).'
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bit_offset: 3
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bit_size: 2
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- name: EXTSEL
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description: 'External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).'
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bit_offset: 5
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bit_size: 1
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array:
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len: 5
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stride: 1
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- name: EXTEN
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description: 'External trigger enable and polarity selection for regular channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of a regular group. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).'
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bit_offset: 10
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bit_size: 2
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- name: OVRMOD
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description: 'Overrun mode This bit is set and cleared by software and configure the way data overrun is managed. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).'
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bit_offset: 12
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bit_size: 1
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- name: CONT
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description: 'Single / Continuous conversion mode for regular conversions This bit is set and cleared by software. If it is set, regular conversion takes place continuously until it is cleared. Note: It is not possible to have both Discontinuous mode and Continuous mode enabled: it is forbidden to set both DISCEN = 1 and CONT = 1. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).'
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bit_offset: 13
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bit_size: 1
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- name: AUTDLY
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description: 'Delayed conversion mode This bit is set and cleared by software to enable/disable the Auto Delayed Conversion mode.. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).'
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bit_offset: 14
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bit_size: 1
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- name: ALIGN
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description: 'Data alignment This bit is set and cleared by software to select right or left alignment. Refer to register, data alignment and offset (ADC_DR, OFFSET, OFFSET_CH, ALIGN). Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).'
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bit_offset: 15
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bit_size: 1
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- name: DISCEN
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description: 'Discontinuous mode for regular channels This bit is set and cleared by software to enable/disable Discontinuous mode for regular channels. Note: It is not possible to have both Discontinuous mode and Continuous mode enabled: it is forbidden to set both DISCEN = 1 and CONT = 1. It is not possible to use both auto-injected mode and Discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).'
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bit_offset: 16
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bit_size: 1
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- name: DISCNUM
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description: 'Discontinuous mode channel count These bits are written by software to define the number of regular channels to be converted in Discontinuous mode, after receiving an external trigger. ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).'
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bit_offset: 17
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bit_size: 3
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- name: JDISCEN
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description: 'Discontinuous mode on injected channels This bit is set and cleared by software to enable/disable Discontinuous mode on the injected channels of a group. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). It is not possible to use both auto-injected mode and Discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set.'
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bit_offset: 20
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bit_size: 1
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- name: JQM
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description: 'JSQR queue mode This bit is set and cleared by software. It defines how an empty Queue is managed. Refer to for more information. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing).'
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bit_offset: 21
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bit_size: 1
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- name: AWD1SGL
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description: 'Enable the watchdog 1 on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWD1CH[4:0] bits or on all the channels Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).'
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bit_offset: 22
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bit_size: 1
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- name: AWD1EN
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description: 'Analog watchdog 1 enable on regular channels This bit is set and cleared by software Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).'
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bit_offset: 23
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bit_size: 1
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- name: JAWD1EN
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description: 'Analog watchdog 1 enable on injected channels This bit is set and cleared by software Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing).'
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bit_offset: 24
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bit_size: 1
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- name: JAUTO
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description: 'Automatic injected group conversion This bit is set and cleared by software to enable/disable automatic injected group conversion after regular group conversion. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no regular nor injected conversion is ongoing).'
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bit_offset: 25
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bit_size: 1
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- name: AWD1CH
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description: 'Analog watchdog 1 channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. ..... others: reserved, must not be used Note: Some channels are not connected physically. Keep the corresponding AWD1CH[4:0] setting to the reset value. The channel selected by AWD1CH must be also selected into the SQRi or JSQRi registers. The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).'
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bit_offset: 26
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bit_size: 5
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- name: JQDIS
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description: 'Injected Queue disable These bits are set and cleared by software to disable the Injected Queue mechanism : Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no regular nor injected conversion is ongoing). A set or reset of JQDIS bit causes the injected queue to be flushed and the JSQR register is cleared.'
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bit_offset: 31
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bit_size: 1
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fieldset/CFGR2:
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description: configuration register 2
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fields:
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- name: ROVSE
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description: 'Regular Oversampling Enable This bit is set and cleared by software to enable regular oversampling. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).'
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bit_offset: 0
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bit_size: 1
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- name: JOVSE
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description: 'Injected Oversampling Enable This bit is set and cleared by software to enable injected oversampling. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).'
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bit_offset: 1
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bit_size: 1
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- name: OVSR
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description: 'Oversampling ratio This bitfield is set and cleared by software to define the oversampling ratio. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no conversion is ongoing).'
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bit_offset: 2
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bit_size: 3
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- name: OVSS
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description: 'Oversampling shift This bitfield is set and cleared by software to define the right shifting applied to the raw oversampling result. Other codes reserved Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no conversion is ongoing).'
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bit_offset: 5
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bit_size: 4
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- name: TROVS
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description: 'Triggered Regular Oversampling This bit is set and cleared by software to enable triggered oversampling Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).'
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bit_offset: 9
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bit_size: 1
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- name: ROVSM
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description: 'Regular Oversampling mode This bit is set and cleared by software to select the regular oversampling mode. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).'
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bit_offset: 10
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bit_size: 1
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- name: SWTRIG
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description: 'Software trigger bit for sampling time control trigger mode This bit is set and cleared by software to enable the bulb sampling mode. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).'
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bit_offset: 25
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bit_size: 1
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- name: BULB
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description: 'Bulb sampling mode This bit is set and cleared by software to enable the bulb sampling mode. SAMPTRIG bit must not be set when the BULB bit is set. The very first ADC conversion is performed with the sampling time specified in SMPx bits. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).'
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bit_offset: 26
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bit_size: 1
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- name: SMPTRIG
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description: 'Sampling time control trigger mode This bit is set and cleared by software to enable the sampling time control trigger mode. The sampling time starts on the trigger rising edge, and the conversion on the trigger falling edge. EXTEN bit should be set to 01. BULB bit must not be set when the SMPTRIG bit is set. When EXTEN bit is set to 00, set SWTRIG to start the sampling and clear SWTRIG bit to start the conversion. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).'
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bit_offset: 27
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bit_size: 1
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fieldset/CR:
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description: control register
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fields:
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- name: ADEN
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description: 'ADC enable control This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the flag ADRDY has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0) except for bit ADVREGEN which must be 1 (and the software must have wait for the startup time of the voltage regulator).'
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bit_offset: 0
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bit_size: 1
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- name: ADDIS
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description: 'ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: The software is allowed to set ADDIS only when ADEN = 1 and both ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).'
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bit_offset: 1
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bit_size: 1
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- name: ADSTART
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description: 'ADC start of regular conversion This bit is set by software to start ADC conversion of regular channels. Depending on the configuration bits EXTEN, a conversion immediately starts (software trigger configuration) or once a regular hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: in Single conversion mode when software trigger is selected (EXTSEL = 0x0): at the assertion of the End of Regular Conversion Sequence (EOS) flag. in all cases: after the execution of the ADSTP command, at the same time that ADSTP is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC) In auto-injection mode (JAUTO = 1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared).'
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bit_offset: 2
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bit_size: 1
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- name: JADSTART
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description: 'ADC start of injected conversion This bit is set by software to start ADC conversion of injected channels. Depending on the configuration bits JEXTEN, a conversion immediately starts (software trigger configuration) or once an injected hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: in Single conversion mode when software trigger is selected (JEXTSEL = 0x0): at the assertion of the End of Injected Conversion Sequence (JEOS) flag. in all cases: after the execution of the JADSTP command, at the same time that JADSTP is cleared by hardware. Note: The software is allowed to set JADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC). In auto-injection mode (JAUTO = 1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared).'
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bit_offset: 3
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bit_size: 1
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- name: ADSTP
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description: 'ADC stop of regular conversion command This bit is set by software to stop and discard an ongoing regular conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC regular sequence and triggers can be re-configured. The ADC is then ready to accept a new start of regular conversions (ADSTART command). Note: The software is allowed to set ADSTP only when ADSTART = 1 and ADDIS = 0 (ADC is enabled and eventually converting a regular conversion and there is no pending request to disable the ADC). In auto-injection mode (JAUTO = 1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP).'
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bit_offset: 4
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bit_size: 1
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- name: JADSTP
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description: 'ADC stop of injected conversion command This bit is set by software to stop and discard an ongoing injected conversion (JADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC injected sequence and triggers can be re-configured. The ADC is then ready to accept a new start of injected conversions (JADSTART command). Note: The software is allowed to set JADSTP only when JADSTART = 1 and ADDIS = 0 (ADC is enabled and eventually converting an injected conversion and there is no pending request to disable the ADC) In Auto-injection mode (JAUTO = 1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP).'
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bit_offset: 5
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bit_size: 1
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- name: ADVREGEN
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description: voltage regulator enable This bits is set by software to enable the ADC voltage regulator. Before performing any operation such as launching a calibration or enabling the ADC, the ADC voltage regulator must first be enabled and the software must wait for the regulator start-up time. For more details about the ADC voltage regulator enable and disable sequences, refer to (ADVREGEN). The software can program this bit field only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)
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bit_offset: 28
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bit_size: 1
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- name: DEEPPWD
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description: 'Deep-power-down enable This bit is set and cleared by software to put the ADC in Deep-power-down mode. Note: The software is allowed to write this bit only when the ADC is disabled (ADCAL = 0, JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).'
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bit_offset: 29
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bit_size: 1
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- name: ADCALDIF
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description: 'Differential mode for calibration This bit is set and cleared by software to configure the Single-ended or Differential inputs mode for the calibration. Note: The software is allowed to write this bit only when the ADC is disabled and is not calibrating (ADCAL = 0, JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).'
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bit_offset: 30
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bit_size: 1
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- name: ADCAL
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description: 'ADC calibration This bit is set by software to start the calibration of the ADC. Program first the bit ADCALDIF to determine if this calibration applies for Single-ended or Differential inputs mode. It is cleared by hardware after calibration is complete. Note: The software is allowed to launch a calibration by setting ADCAL only when ADEN = 0. The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN = 1 and ADSTART = 0 and JADSTART = 0 (ADC enabled and no conversion is ongoing).'
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bit_offset: 31
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bit_size: 1
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fieldset/DIFSEL:
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description: Differential mode Selection Register
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fields:
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- name: DIFSEL
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description: 'Differential mode for channels 19 to 0. These bits are set and cleared by software. They allow to select if a channel is configured as Single-ended or Differential mode. DIFSEL[i] = 0: analog input channel is configured in Single-ended mode DIFSEL[i] = 1: analog input channel i is configured in Differential mode Note: The DIFSEL bits corresponding to channels that are either connected to a single-ended I/O port or to an internal channel must be kept their reset value (Single-ended input mode). The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).'
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bit_offset: 0
|
||||
bit_size: 20
|
||||
fieldset/DR:
|
||||
description: regular data register
|
||||
fields:
|
||||
- name: RDATA
|
||||
description: Regular data converted These bits are read-only. They contain the conversion result from the last converted regular channel. The data are left- or right-aligned as described in
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/IER:
|
||||
description: interrupt enable register
|
||||
fields:
|
||||
- name: ADRDYIE
|
||||
description: 'ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).'
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: EOSMPIE
|
||||
description: 'End of sampling flag interrupt enable for regular conversions This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt for regular conversions. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).'
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: EOCIE
|
||||
description: 'End of regular conversion interrupt enable This bit is set and cleared by software to enable/disable the end of a regular conversion interrupt. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).'
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: EOSIE
|
||||
description: 'End of regular sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of regular sequence of conversions interrupt. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).'
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: OVRIE
|
||||
description: 'Overrun interrupt enable This bit is set and cleared by software to enable/disable the Overrun interrupt of a regular conversion. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).'
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: JEOCIE
|
||||
description: 'End of injected conversion interrupt enable This bit is set and cleared by software to enable/disable the end of an injected conversion interrupt. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing).'
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: JEOSIE
|
||||
description: 'End of injected sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of injected sequence of conversions interrupt. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing).'
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: AWDIE
|
||||
description: 'Analog watchdog 1-3 interrupt enable. This bit is set and cleared by software to enable/disable the analog watchdog 1-3 interrupts. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).'
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 3
|
||||
stride: 1
|
||||
- name: JQOVFIE
|
||||
description: 'Injected context queue overflow interrupt enable This bit is set and cleared by software to enable/disable the Injected Context Queue Overflow interrupt. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing).'
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
fieldset/ISR:
|
||||
description: interrupt and status register
|
||||
fields:
|
||||
- name: ADRDY
|
||||
description: ready This bit is set by hardware after the ADC has been enabled (ADEN = 1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: EOSMP
|
||||
description: End of sampling flag This bit is set by hardware during the conversion of any channel (only for regular channels), at the end of the sampling phase
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: EOC
|
||||
description: End of conversion flag This bit is set by hardware at the end of each regular conversion of a channel when a new data is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: EOS
|
||||
description: End of regular sequence flag This bit is set by hardware at the end of the conversions of a regular sequence of channels. It is cleared by software writing 1 to it
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: OVR
|
||||
description: overrun This bit is set by hardware when an overrun occurs on a regular channel, meaning that a new conversion has completed while the EOC flag was already set. It is cleared by software writing 1 to it
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: JEOC
|
||||
description: Injected channel end of conversion flag This bit is set by hardware at the end of each injected conversion of a channel when a new data is available in the corresponding ADC_JDRy register. It is cleared by software writing 1 to it or by reading the corresponding ADC_JDRy register
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: JEOS
|
||||
description: Injected channel end of sequence flag This bit is set by hardware at the end of the conversions of all injected channels in the group. It is cleared by software writing 1 to it
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: AWD
|
||||
description: Analog watchdog 1-3 flags. Set by hardware when the converted voltage crosses the values programmed in the corresponding fields LT and HT fields of the relevant TR register. It is cleared by software.
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 3
|
||||
stride: 1
|
||||
- name: JQOVF
|
||||
description: Injected context queue overflow This bit is set by hardware when an Overflow of the Injected Queue of Context occurs. It is cleared by software writing 1 to it. Refer to for more information
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
fieldset/JDR:
|
||||
description: injected channel 1-4 data register
|
||||
fields:
|
||||
- name: JDATA
|
||||
description: Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/JSQR:
|
||||
description: injected sequence register
|
||||
fields:
|
||||
- name: JL
|
||||
description: 'Injected channel sequence length These bits are written by software to define the total number of conversions in the injected channel conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing).'
|
||||
bit_offset: 0
|
||||
bit_size: 2
|
||||
- name: JEXTSEL
|
||||
description: 'External Trigger Selection for injected group These bits select the external event used to trigger the start of conversion of an injected group: ... Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing).'
|
||||
bit_offset: 2
|
||||
bit_size: 5
|
||||
- name: JEXTEN
|
||||
description: 'External trigger enable and polarity selection for injected channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing). If JQM = 1 and if the Queue of Context becomes empty, the software and hardware triggers of the injected sequence are both internally disabled (refer to Queue of context for injected conversions).'
|
||||
bit_offset: 7
|
||||
bit_size: 2
|
||||
- name: JSQ
|
||||
description: '1st-4th conversions in the injected sequence These bits are written by software with the channel number (0 to 19) assigned as the 1st-4th in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing).'
|
||||
bit_offset: 9
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 4
|
||||
stride: 6
|
||||
fieldset/OFR:
|
||||
description: offset 1-4 register
|
||||
fields:
|
||||
- name: OFFSET
|
||||
description: 'Data offset y for the channel programmed into bits OFFSET_CH[4:0] These bits are written by software to define the offset to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset must be programmed in the bits OFFSET_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). If several offset (OFFSET) point to the same channel, only the offset with the lowest x value is considered for the subtraction. Ex: if OFFSET1_CH[4:0] = 4 and OFFSET2_CH[4:0] = 4, this is OFFSET1[11:0] which is subtracted when converting channel 4.'
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: OFFSETPOS
|
||||
description: 'Positive offset This bit is set and cleared by software to enable the positive offset. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).'
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: SATEN
|
||||
description: 'Saturation enable This bit is set and cleared by software to enable the saturation at 0x000 and 0xFFF for the offset function. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).'
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: OFFSET_CH
|
||||
description: 'Channel selection for the data offset y These bits are written by software to define the channel to which the offset programmed into bits OFFSET[11:0] applies. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically and must not be selected for the data offset y. If OFFSET_EN is set, it is not allowed to select the same channel for different ADC_OFRy registers.'
|
||||
bit_offset: 26
|
||||
bit_size: 5
|
||||
- name: OFFSET_EN
|
||||
description: 'Offset y enable This bit is written by software to enable or disable the offset programmed into bits OFFSET[11:0]. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).'
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/OR:
|
||||
description: option register
|
||||
fields:
|
||||
- name: OP0
|
||||
description: Option bit 0
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: OP1
|
||||
description: Option bit 1. Note - not documented for H562/H563/H573
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
fieldset/SMPR1:
|
||||
description: sample time register 1
|
||||
fields:
|
||||
- name: SMP
|
||||
description: 'Channel 0-9 sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value.'
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
array:
|
||||
len: 10
|
||||
stride: 3
|
||||
- name: SMPPLUS
|
||||
description: Addition of one clock cycle to the sampling time. To make sure no conversion is ongoing, the software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/SMPR2:
|
||||
description: sample time register 2
|
||||
fields:
|
||||
- name: SMP
|
||||
description: 'Channel 10-19 sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value.'
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
array:
|
||||
len: 10
|
||||
stride: 3
|
||||
fieldset/SQR1:
|
||||
description: regular sequence register 1
|
||||
fields:
|
||||
- name: L
|
||||
description: 'Regular channel sequence length These bits are written by software to define the total number of conversions in the regular channel conversion sequence. ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).'
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: SQ
|
||||
description: '1st-4th conversions in regular sequence These bits are written by software with the channel number (0 to 19) assigned as the 1st-4th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).'
|
||||
bit_offset: 6
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 4
|
||||
stride: 6
|
||||
fieldset/SQR2:
|
||||
description: regular sequence register 2
|
||||
fields:
|
||||
- name: SQ
|
||||
description: '5th-9th conversions in regular sequence These bits are written by software with the channel number (0 to 19) assigned as the 5th-9th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).'
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 5
|
||||
stride: 6
|
||||
fieldset/SQR3:
|
||||
description: regular sequence register 3
|
||||
fields:
|
||||
- name: SQ
|
||||
description: '10th-14th conversions in regular sequence These bits are written by software with the channel number (0 to 19) assigned as the 10th-14th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).'
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 5
|
||||
stride: 6
|
||||
fieldset/SQR4:
|
||||
description: regular sequence register 4
|
||||
fields:
|
||||
- name: SQ
|
||||
description: '15th-16th conversions in regular sequence These bits are written by software with the channel number (0 to 19) assigned as the 15th-16th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).'
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 2
|
||||
stride: 6
|
||||
fieldset/TR1:
|
||||
description: watchdog threshold register 1
|
||||
fields:
|
||||
- name: LT1
|
||||
description: 'Analog watchdog 1 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 1. Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).'
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: AWDFILT
|
||||
description: 'Analog watchdog filtering parameter This bit is set and cleared by software. ... Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).'
|
||||
bit_offset: 12
|
||||
bit_size: 3
|
||||
- name: HT1
|
||||
description: 'Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 1. Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).'
|
||||
bit_offset: 16
|
||||
bit_size: 12
|
||||
fieldset/TR2:
|
||||
description: watchdog threshold register 2
|
||||
fields:
|
||||
- name: LT2
|
||||
description: 'Analog watchdog 2 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 2. Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).'
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: HT2
|
||||
description: 'Analog watchdog 2 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 2. Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).'
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
fieldset/TR3:
|
||||
description: watchdog threshold register 3
|
||||
fields:
|
||||
- name: LT3
|
||||
description: 'Analog watchdog 3 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 3. This watchdog compares the 8-bit of LT3 with the 8 MSB of the converted data. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).'
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: HT3
|
||||
description: 'Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 3. Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).'
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
200
data/registers/adccommon_h5.yaml
Normal file
200
data/registers/adccommon_h5.yaml
Normal file
@ -0,0 +1,200 @@
|
||||
block/ADC_COMMON:
|
||||
description: ADC common registers
|
||||
items:
|
||||
- name: CSR
|
||||
description: common status register
|
||||
byte_offset: 0
|
||||
fieldset: CSR
|
||||
- name: CCR
|
||||
description: common control register
|
||||
byte_offset: 8
|
||||
fieldset: CCR
|
||||
- name: CDR
|
||||
description: common regular data register for dual mode
|
||||
byte_offset: 12
|
||||
fieldset: CDR
|
||||
- name: HWCFGR0
|
||||
description: hardware configuration register
|
||||
byte_offset: 240
|
||||
fieldset: HWCFGR0
|
||||
- name: VERR
|
||||
description: version register
|
||||
byte_offset: 244
|
||||
fieldset: VERR
|
||||
- name: IPDR
|
||||
description: identification register
|
||||
byte_offset: 248
|
||||
fieldset: IPDR
|
||||
- name: SIDR
|
||||
description: size identification register
|
||||
byte_offset: 252
|
||||
fieldset: SIDR
|
||||
fieldset/CSR:
|
||||
description: common status register
|
||||
fields:
|
||||
- name: ADRDY_MST
|
||||
description: Master ADC ready This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register.
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: EOSMP_MST
|
||||
description: End of Sampling phase flag of the master ADC This bit is a copy of the EOSMP bit in the corresponding ADC_ISR register.
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: EOC_MST
|
||||
description: End of regular conversion of the master ADC This bit is a copy of the EOC bit in the corresponding ADC_ISR register.
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: EOS_MST
|
||||
description: End of regular sequence flag of the master ADC This bit is a copy of the EOS bit in the corresponding ADC_ISR register.
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: OVR_MST
|
||||
description: Overrun flag of the master ADC This bit is a copy of the OVR bit in the corresponding ADC_ISR register.
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: JEOC_MST
|
||||
description: End of injected conversion flag of the master ADC This bit is a copy of the JEOC bit in the corresponding ADC_ISR register.
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: JEOS_MST
|
||||
description: End of injected sequence flag of the master ADC This bit is a copy of the JEOS bit in the corresponding ADC_ISR register.
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: AWD1_MST
|
||||
description: Analog watchdog 1 flag of the master ADC This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register.
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: AWD2_MST
|
||||
description: Analog watchdog 2 flag of the master ADC This bit is a copy of the AWD2 bit in the corresponding ADC_ISR register.
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: AWD3_MST
|
||||
description: Analog watchdog 3 flag of the master ADC This bit is a copy of the AWD3 bit in the corresponding ADC_ISR register.
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: JQOVF_MST
|
||||
description: Injected Context Queue Overflow flag of the master ADC This bit is a copy of the JQOVF bit in the corresponding ADC_ISR register.
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: ADRDY_SLV
|
||||
description: Slave ADC ready This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register.
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: EOSMP_SLV
|
||||
description: End of Sampling phase flag of the slave ADC This bit is a copy of the EOSMP2 bit in the corresponding ADC_ISR register.
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: EOC_SLV
|
||||
description: End of regular conversion of the slave ADC This bit is a copy of the EOC bit in the corresponding ADC_ISR register.
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: EOS_SLV
|
||||
description: End of regular sequence flag of the slave ADC. This bit is a copy of the EOS bit in the corresponding ADC_ISR register.
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: OVR_SLV
|
||||
description: Overrun flag of the slave ADC This bit is a copy of the OVR bit in the corresponding ADC_ISR register.
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: JEOC_SLV
|
||||
description: End of injected conversion flag of the slave ADC This bit is a copy of the JEOC bit in the corresponding ADC_ISR register.
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: JEOS_SLV
|
||||
description: End of injected sequence flag of the slave ADC This bit is a copy of the JEOS bit in the corresponding ADC_ISR register.
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: AWD1_SLV
|
||||
description: Analog watchdog 1 flag of the slave ADC This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register.
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: AWD2_SLV
|
||||
description: Analog watchdog 2 flag of the slave ADC This bit is a copy of the AWD2 bit in the corresponding ADC_ISR register.
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: AWD3_SLV
|
||||
description: Analog watchdog 3 flag of the slave ADC This bit is a copy of the AWD3 bit in the corresponding ADC_ISR register.
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: JQOVF_SLV
|
||||
description: Injected Context Queue Overflow flag of the slave ADC This bit is a copy of the JQOVF bit in the corresponding ADC_ISR register.
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
fieldset/CCR:
|
||||
description: common control register
|
||||
fields:
|
||||
- name: CKMODE
|
||||
description: 'ADC clock mode These bits are set and cleared by software to define the ADC clock scheme (which is common to both master and slave ADCs): In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).'
|
||||
bit_offset: 16
|
||||
bit_size: 2
|
||||
- name: PRESC
|
||||
description: 'ADC prescaler These bits are set and cleared by software to select the frequency of the clock to the ADC. The clock is common for all the ADCs. other: reserved Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). The ADC prescaler value is applied only when CKMODE[1:0] = 0b00.'
|
||||
bit_offset: 18
|
||||
bit_size: 4
|
||||
- name: VREFEN
|
||||
description: VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT channel
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: TSEN
|
||||
description: VSENSE enable This bit is set and cleared by software to control VSENSE
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: VBATEN
|
||||
description: VBAT enable This bit is set and cleared by software to control
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
fieldset/CDR:
|
||||
description: common regular data register for dual mode
|
||||
fields:
|
||||
- name: RDATA_MST
|
||||
description: Regular data of the master ADC. In dual mode, these bits contain the regular data of the master ADC. Refer to . The data alignment is applied as described in offset (ADC_DR, OFFSET, OFFSET_CH, ALIGN)) In MDMA = 0b11 mode, bits 15:8 contains SLV_ADC_DR[7:0], bits 7:0 contains MST_ADC_DR[7:0].
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: RDATA_SLV
|
||||
description: Regular data of the slave ADC In dual mode, these bits contain the regular data of the slave ADC. Refer to Dual ADC modes. The data alignment is applied as described in offset (ADC_DR, OFFSET, OFFSET_CH, ALIGN)).
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
fieldset/HWCFGR0:
|
||||
description: hardware configuration register
|
||||
fields:
|
||||
- name: ADCNUM
|
||||
description: Number of ADCs implemented
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: MULPIPE
|
||||
description: Number of pipeline stages
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
- name: OPBITS
|
||||
description: 'Number of option bits 0002: 2 option bits implemented in the ADC option register (ADC_OR) at address offset 0xC8.'
|
||||
bit_offset: 8
|
||||
bit_size: 4
|
||||
- name: IDLEVALUE
|
||||
description: Idle value for non-selected channels
|
||||
bit_offset: 12
|
||||
bit_size: 4
|
||||
fieldset/VERR:
|
||||
description: version register
|
||||
fields:
|
||||
- name: MINREV
|
||||
description: 'Minor revision These bits returns the ADC IP minor revision 0002: Major revision = X.2.'
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: MAJREV
|
||||
description: Major revision These bits returns the ADC IP major revision
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
fieldset/IPDR:
|
||||
description: identification register
|
||||
fields:
|
||||
- name: ID
|
||||
description: 'Peripheral identifier These bits returns the ADC identifier. ID[31:0] = 0x0011 0006: c7amba_aditf5_90_v1.'
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/SIDR:
|
||||
description: size identification register
|
||||
fields:
|
||||
- name: SID
|
||||
description: 'Size Identification SID[31:8]: fixed code that characterizes the ADC_SIDR register. This field is always read at 0xA3C5DD. SID[7:0]: read-only numeric field that returns the address offset (in Kbytes) of the identification registers from the IP base address:.'
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
90
data/registers/adccommon_h50.yaml
Normal file
90
data/registers/adccommon_h50.yaml
Normal file
@ -0,0 +1,90 @@
|
||||
block/ADC_COMMON:
|
||||
description: ADC common registers
|
||||
items:
|
||||
- name: CCR
|
||||
description: common control register
|
||||
byte_offset: 8
|
||||
fieldset: CCR
|
||||
- name: HWCFGR0
|
||||
description: hardware configuration register
|
||||
byte_offset: 240
|
||||
fieldset: HWCFGR0
|
||||
- name: VERR
|
||||
description: version register
|
||||
byte_offset: 244
|
||||
fieldset: VERR
|
||||
- name: IPDR
|
||||
description: identification register
|
||||
byte_offset: 248
|
||||
fieldset: IPDR
|
||||
- name: SIDR
|
||||
description: size identification register
|
||||
byte_offset: 252
|
||||
fieldset: SIDR
|
||||
fieldset/CCR:
|
||||
description: common control register
|
||||
fields:
|
||||
- name: CKMODE
|
||||
description: 'ADC clock mode These bits are set and cleared by software to define the ADC clock scheme (which is common to both master and slave ADCs): In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).'
|
||||
bit_offset: 16
|
||||
bit_size: 2
|
||||
- name: PRESC
|
||||
description: 'ADC prescaler These bits are set and cleared by software to select the frequency of the clock to the ADC. The clock is common for all the ADCs. other: reserved Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). The ADC prescaler value is applied only when CKMODE[1:0] = 0b00.'
|
||||
bit_offset: 18
|
||||
bit_size: 4
|
||||
- name: VREFEN
|
||||
description: VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT channel
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: TSEN
|
||||
description: VSENSE enable This bit is set and cleared by software to control VSENSE
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: VBATEN
|
||||
description: VBAT enable This bit is set and cleared by software to control
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
fieldset/HWCFGR0:
|
||||
description: hardware configuration register
|
||||
fields:
|
||||
- name: ADCNUM
|
||||
description: Number of ADCs implemented
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: MULPIPE
|
||||
description: Number of pipeline stages
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
- name: OPBITS
|
||||
description: 'Number of option bits 0002: 2 option bits implemented in the ADC option register (ADC_OR) at address offset 0xC8.'
|
||||
bit_offset: 8
|
||||
bit_size: 4
|
||||
- name: IDLEVALUE
|
||||
description: Idle value for non-selected channels
|
||||
bit_offset: 12
|
||||
bit_size: 4
|
||||
fieldset/VERR:
|
||||
description: version register
|
||||
fields:
|
||||
- name: MINREV
|
||||
description: 'Minor revision These bits returns the ADC IP minor revision 0002: Major revision = X.2.'
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: MAJREV
|
||||
description: Major revision These bits returns the ADC IP major revision
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
fieldset/IPDR:
|
||||
description: identification register
|
||||
fields:
|
||||
- name: ID
|
||||
description: 'Peripheral identifier These bits returns the ADC identifier. ID[31:0] = 0x0011 0006: c7amba_aditf5_90_v1.'
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/SIDR:
|
||||
description: size identification register
|
||||
fields:
|
||||
- name: SID
|
||||
description: 'Size Identification SID[31:8]: fixed code that characterizes the ADC_SIDR register. This field is always read at 0xA3C5DD. SID[7:0]: read-only numeric field that returns the address offset (in Kbytes) of the identification registers from the IP base address:.'
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
@ -200,6 +200,7 @@ impl PeriMatcher {
|
||||
(".*:ADC:aditf5_v2_0", ("adc", "v3", "ADC")),
|
||||
(".*:ADC:aditf5_v2_2", ("adc", "v3", "ADC")),
|
||||
(".*:ADC:aditf5_v3_0", ("adc", "v4", "ADC")),
|
||||
(".*:ADC:aditf5_v3_0_H5", ("adc", "h5", "ADC")),
|
||||
(".*:ADC:aditf5_v3_1", ("adc", "v4", "ADC")),
|
||||
("STM32WL5.*:ADC:.*", ("adc", "g0", "ADC")),
|
||||
("STM32WLE.*:ADC:.*", ("adc", "g0", "ADC")),
|
||||
@ -213,6 +214,11 @@ impl PeriMatcher {
|
||||
(".*:ADC_COMMON:aditf4_v3_0_WL", ("adccommon", "v3", "ADC_COMMON")),
|
||||
(".*:ADC_COMMON:aditf5_v1_1", ("adccommon", "f3", "ADC_COMMON")),
|
||||
(".*:ADC3_COMMON:aditf5_v1_1", ("adccommon", "f3", "ADC_COMMON")),
|
||||
(
|
||||
"STM32H50.*:ADC_COMMON:aditf5_v3_0_H5",
|
||||
("adccommon", "h50", "ADC_COMMON"),
|
||||
),
|
||||
("STM32H5.*:ADC_COMMON:aditf5_v3_0_H5", ("adccommon", "h5", "ADC_COMMON")),
|
||||
("STM32H7.*:ADC_COMMON:.*", ("adccommon", "v4", "ADC_COMMON")),
|
||||
("STM32H7.*:ADC3_COMMON:.*", ("adccommon", "v4", "ADC_COMMON")),
|
||||
("STM32G4.*:OPAMP:G4_tsmc90_fastOpamp", ("opamp", "g4", "OPAMP")),
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user