91 lines
3.4 KiB
YAML
91 lines
3.4 KiB
YAML
block/ADC_COMMON:
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description: ADC common registers
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items:
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- name: CCR
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description: common control register
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byte_offset: 8
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fieldset: CCR
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- name: HWCFGR0
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description: hardware configuration register
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byte_offset: 240
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fieldset: HWCFGR0
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- name: VERR
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description: version register
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byte_offset: 244
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fieldset: VERR
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- name: IPDR
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description: identification register
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byte_offset: 248
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fieldset: IPDR
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- name: SIDR
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description: size identification register
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byte_offset: 252
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fieldset: SIDR
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fieldset/CCR:
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description: common control register
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fields:
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- name: CKMODE
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description: 'ADC clock mode These bits are set and cleared by software to define the ADC clock scheme (which is common to both master and slave ADCs): In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).'
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bit_offset: 16
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bit_size: 2
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- name: PRESC
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description: 'ADC prescaler These bits are set and cleared by software to select the frequency of the clock to the ADC. The clock is common for all the ADCs. other: reserved Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). The ADC prescaler value is applied only when CKMODE[1:0] = 0b00.'
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bit_offset: 18
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bit_size: 4
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- name: VREFEN
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description: VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT channel
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bit_offset: 22
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bit_size: 1
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- name: TSEN
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description: VSENSE enable This bit is set and cleared by software to control VSENSE
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bit_offset: 23
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bit_size: 1
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- name: VBATEN
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description: VBAT enable This bit is set and cleared by software to control
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bit_offset: 24
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bit_size: 1
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fieldset/HWCFGR0:
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description: hardware configuration register
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fields:
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- name: ADCNUM
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description: Number of ADCs implemented
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bit_offset: 0
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bit_size: 4
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- name: MULPIPE
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description: Number of pipeline stages
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bit_offset: 4
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bit_size: 4
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- name: OPBITS
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description: 'Number of option bits 0002: 2 option bits implemented in the ADC option register (ADC_OR) at address offset 0xC8.'
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bit_offset: 8
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bit_size: 4
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- name: IDLEVALUE
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description: Idle value for non-selected channels
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bit_offset: 12
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bit_size: 4
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fieldset/VERR:
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description: version register
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fields:
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- name: MINREV
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description: 'Minor revision These bits returns the ADC IP minor revision 0002: Major revision = X.2.'
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bit_offset: 0
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bit_size: 4
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- name: MAJREV
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description: Major revision These bits returns the ADC IP major revision
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bit_offset: 4
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bit_size: 4
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fieldset/IPDR:
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description: identification register
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fields:
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- name: ID
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description: 'Peripheral identifier These bits returns the ADC identifier. ID[31:0] = 0x0011 0006: c7amba_aditf5_90_v1.'
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bit_offset: 0
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bit_size: 32
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fieldset/SIDR:
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description: size identification register
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fields:
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- name: SID
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description: 'Size Identification SID[31:8]: fixed code that characterizes the ADC_SIDR register. This field is always read at 0xA3C5DD. SID[7:0]: read-only numeric field that returns the address offset (in Kbytes) of the identification registers from the IP base address:.'
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bit_offset: 0
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bit_size: 32
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