run chiptool fmt with new version that trims descriptions.

2022-04-08 01:17:53 +02:00 · 2022-04-08 01:17:53 +02:00 · 1d5853be40
commit 1d5853be40
parent b797baeb14
14 changed files with 1636 additions and 1645 deletions
--- a/data/registers/flash_g0.yaml
+++ b/data/registers/flash_g0.yaml
@ -386,69 +386,69 @@ fieldset/WRP1BR:
      description: WRP area B end offset
      bit_offset: 16
      bit_size: 6
 enum/LATENCY:
  bit_size: 3
  variants:
    - name: WS0
      description: Zero wait states
      value: 0b000
    - name: WS1
      description: One wait state
      value: 0b001
    - name: WS2
      description: Two wait states
      value: 0b010
 enum/NRST_MODE:
  bit_size: 2
  variants:
    - name: INPUT_ONLY
      description: Reset pin is in reset input mode only
      value: 0b01
    - name: GPIO
      description: Reset pin is in GPIO mode only
      value: 0b10
    - name: INPUT_OUTPUT
      description: Reset pin is in resety input and output mode
      value: 0b11
 enum/BORR_LEV:
  bit_size: 2
  variants:
    - name: RISING_0
      description: BOR rising level 1 with threshold around 2.1V
      value: 0b00
    - name: RISING_1
      description: BOR rising level 2 with threshold around 2.3V
      value: 0b01
    - name: RISING_2
      description: BOR rising level 3 with threshold around 2.6V
      value: 0b10
    - name: RISING_3
      description: BOR rising level 4 with threshold around 2.9V
      value: 0b11
 enum/BORF_LEV:
  bit_size: 2
  variants:
    - name: FALLING_0
      description: BOR falling level 1 with threshold around 2.0V
-      value: 0b00
+      value: 0
    - name: FALLING_1
      description: BOR falling level 2 with threshold around 2.2V
-      value: 0b01
+      value: 1
    - name: FALLING_2
      description: BOR falling level 3 with threshold around 2.5V
-      value: 0b10
+      value: 2
    - name: FALLING_3
      description: BOR falling level 4 with threshold around 2.8V
-      value: 0b11
+      value: 3
 enum/BORR_LEV:
  bit_size: 2
  variants:
    - name: RISING_0
      description: BOR rising level 1 with threshold around 2.1V
      value: 0
    - name: RISING_1
      description: BOR rising level 2 with threshold around 2.3V
      value: 1
    - name: RISING_2
      description: BOR rising level 3 with threshold around 2.6V
      value: 2
    - name: RISING_3
      description: BOR rising level 4 with threshold around 2.9V
      value: 3
 enum/LATENCY:
  bit_size: 3
  variants:
    - name: WS0
      description: Zero wait states
      value: 0
    - name: WS1
      description: One wait state
      value: 1
    - name: WS2
      description: Two wait states
      value: 2
 enum/NRST_MODE:
  bit_size: 2
  variants:
    - name: INPUT_ONLY
      description: Reset pin is in reset input mode only
      value: 1
    - name: GPIO
      description: Reset pin is in GPIO mode only
      value: 2
    - name: INPUT_OUTPUT
      description: Reset pin is in resety input and output mode
      value: 3
 enum/RDP:
  bit_size: 8
  variants:
    - name: LEVEL_0
      value: 0xAA
      description: Read protection not active
      value: 170
    - name: LEVEL_1
      value: 0xBB
      description: Memories read protection active
      value: 187
    - name: LEVEL_2
      value: 0xCC
      description: Chip read protection active
      value: 204
--- a/data/registers/flash_u5.yaml
+++ b/data/registers/flash_u5.yaml
@ -3,115 +3,115 @@ block/FLASH:
  description: Flash
  items:
    - name: ACR
-      description: "FLASH access control register "
+      description: FLASH access control register
      byte_offset: 0
      fieldset: ACR
    - name: NSKEYR
-      description: "FLASH non-secure key register "
+      description: FLASH non-secure key register
      byte_offset: 8
      fieldset: NSKEYR
    - name: SECKEYR
-      description: "FLASH secure key register "
+      description: FLASH secure key register
      byte_offset: 12
      fieldset: SECKEYR
    - name: OPTKEYR
-      description: "FLASH option key register "
+      description: FLASH option key register
      byte_offset: 16
      fieldset: OPTKEYR
    - name: PDKEY1R
-      description: "FLASH bank 1 power-down key register "
+      description: FLASH bank 1 power-down key register
      byte_offset: 24
      fieldset: PDKEY1R
    - name: PDKEY2R
-      description: "FLASH bank 2 power-down key register "
+      description: FLASH bank 2 power-down key register
      byte_offset: 28
      fieldset: PDKEY2R
    - name: NSSR
-      description: "FLASH non-secure status register "
+      description: FLASH non-secure status register
      byte_offset: 32
      fieldset: NSSR
    - name: SECSR
-      description: "FLASH secure status register "
+      description: FLASH secure status register
      byte_offset: 36
      fieldset: SECSR
    - name: NSCR
-      description: "FLASH non-secure control register "
+      description: FLASH non-secure control register
      byte_offset: 40
      fieldset: NSCR
    - name: SECCR
-      description: "FLASH secure control register "
+      description: FLASH secure control register
      byte_offset: 44
      fieldset: SECCR
    - name: ECCR
-      description: "FLASH ECC register "
+      description: FLASH ECC register
      byte_offset: 48
      fieldset: ECCR
    - name: OPSR
-      description: "FLASH operation status register "
+      description: FLASH operation status register
      byte_offset: 52
      fieldset: OPSR
    - name: OPTR
-      description: "FLASH option register "
+      description: FLASH option register
      byte_offset: 64
      fieldset: OPTR
    - name: NSBOOTADD0R
-      description: "FLASH non-secure boot address 0 register\t"
+      description: FLASH non-secure boot address 0 register
      byte_offset: 68
      fieldset: NSBOOTADD0R
    - name: NSBOOTADD1R
-      description: "FLASH non-secure boot address 1 register\t"
+      description: FLASH non-secure boot address 1 register
      byte_offset: 72
      fieldset: NSBOOTADD1R
    - name: SECBOOTADD0R
-      description: "FLASH secure boot address 0 register "
+      description: FLASH secure boot address 0 register
      byte_offset: 76
      fieldset: SECBOOTADD0R
    - name: SECWM1R1
-      description: "FLASH secure watermark1 register 1 "
+      description: FLASH secure watermark1 register 1
      byte_offset: 80
      fieldset: SECWM1R1
    - name: SECWM1R2
-      description: "FLASH secure watermark1 register 2 "
+      description: FLASH secure watermark1 register 2
      byte_offset: 84
      fieldset: SECWM1R2
    - name: WRP1AR
-      description: "FLASH WRP1 area A address register "
+      description: FLASH WRP1 area A address register
      byte_offset: 88
      fieldset: WRP1AR
    - name: WRP1BR
-      description: "FLASH WRP1 area B address register "
+      description: FLASH WRP1 area B address register
      byte_offset: 92
      fieldset: WRP1BR
    - name: SECWM2R1
-      description: "FLASH secure watermark2 register 1 "
+      description: FLASH secure watermark2 register 1
      byte_offset: 96
      fieldset: SECWM2R1
    - name: SECWM2R2
-      description: "FLASH secure watermark2 register 2 "
+      description: FLASH secure watermark2 register 2
      byte_offset: 100
      fieldset: SECWM2R2
    - name: WRP2AR
-      description: "FLASH WPR2 area A address register "
+      description: FLASH WPR2 area A address register
      byte_offset: 104
      fieldset: WRP2AR
    - name: WRP2BR
-      description: "FLASH WPR2 area B address register "
+      description: FLASH WPR2 area B address register
      byte_offset: 108
      fieldset: WRP2BR
    - name: OEM1KEYR1
-      description: "FLASH OEM1 key register 1 "
+      description: FLASH OEM1 key register 1
      byte_offset: 112
      fieldset: OEM1KEYR1
    - name: OEM1KEYR2
-      description: "FLASH OEM1 key register 2 "
+      description: FLASH OEM1 key register 2
      byte_offset: 116
      fieldset: OEM1KEYR2
    - name: OEM2KEYR1
-      description: "FLASH OEM2 key register 1 "
+      description: FLASH OEM2 key register 1
      byte_offset: 120
      fieldset: OEM2KEYR1
    - name: OEM2KEYR2
-      description: "FLASH OEM2 key register 2 "
+      description: FLASH OEM2 key register 2
      byte_offset: 124
      fieldset: OEM2KEYR2
    - name: SEC1BBR1
@ -147,11 +147,11 @@ block/FLASH:
      byte_offset: 172
      fieldset: SEC2BBR4
    - name: SECHDPCR
-      description: "FLASH secure HDP control register "
+      description: FLASH secure HDP control register
      byte_offset: 192
      fieldset: SECHDPCR
    - name: PRIVCFGR
-      description: "FLASH privilege configuration register "
+      description: FLASH privilege configuration register
      byte_offset: 196
      fieldset: PRIVCFGR
    - name: PRIV1BBR1
@ -187,7 +187,7 @@ block/FLASH:
      byte_offset: 252
      fieldset: PRIV2BBR4
 fieldset/ACR:
-  description: "FLASH access control register "
+  description: FLASH access control register
  fields:
    - name: LATENCY
      description: "Latency\r These bits represent the ratio between the HCLK (AHB clock) period and the Flash memory access time.\r ..."
@ -218,7 +218,7 @@ fieldset/ACR:
      bit_size: 1
      enum: SLEEP_PD
 fieldset/ECCR:
-  description: "FLASH ECC register "
+  description: FLASH ECC register
  fields:
    - name: ADDR_ECC
      description: ECC fail address
@ -247,21 +247,21 @@ fieldset/ECCR:
      bit_offset: 31
      bit_size: 1
 fieldset/NSBOOTADD0R:
-  description: "FLASH non-secure boot address 0 register\t"
+  description: FLASH non-secure boot address 0 register
  fields:
    - name: NSBOOTADD0
      description: "Non-secure boot base address 0\r The non-secure boot memory address can be programmed to any address in the valid address range with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or nSWBOOT0 state.\r Examples:\r NSBOOTADD0[24:0] = 0x0100000: Boot from non-secure Flash memory (0x0800 0000)\r NSBOOTADD0[24:0] = 0x017F200: Boot from system memory bootloader (0x0BF9 0000)\r NSBOOTADD0[24:0] = 0x0400000: Boot from non-secure SRAM1 on S-Bus (0x2000 0000)"
      bit_offset: 7
      bit_size: 25
 fieldset/NSBOOTADD1R:
-  description: "FLASH non-secure boot address 1 register\t"
+  description: FLASH non-secure boot address 1 register
  fields:
    - name: NSBOOTADD1
      description: "Non-secure boot address 1\r The non-secure boot memory address can be programmed to any address in the valid address range with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or nSWBOOT0 state.\r Examples:\r NSBOOTADD1[24:0] = 0x0100000: Boot from non-secure Flash memory (0x0800 0000)\r NSBOOTADD1[24:0] = 0x017F200: Boot from system memory bootloader (0x0BF9 0000)\r NSBOOTADD1[24:0] = 0x0400000: Boot from non-secure SRAM1 on S-Bus (0x2000 0000)"
      bit_offset: 7
      bit_size: 25
 fieldset/NSCR:
-  description: "FLASH non-secure control register "
+  description: FLASH non-secure control register
  fields:
    - name: PG
      description: Non-secure programming
@ -326,14 +326,14 @@ fieldset/NSCR:
      bit_offset: 31
      bit_size: 1
 fieldset/NSKEYR:
-  description: "FLASH non-secure key register "
+  description: FLASH non-secure key register
  fields:
    - name: NSKEY
      description: Flash memory non-secure key
      bit_offset: 0
      bit_size: 32
 fieldset/NSSR:
-  description: "FLASH non-secure status register "
+  description: FLASH non-secure status register
  fields:
    - name: EOP
      description: Non-secure end of operation
@ -392,35 +392,35 @@ fieldset/NSSR:
      bit_offset: 21
      bit_size: 1
 fieldset/OEM1KEYR1:
-  description: "FLASH OEM1 key register 1 "
+  description: FLASH OEM1 key register 1
  fields:
    - name: OEM1KEY
      description: OEM1 least significant bytes key
      bit_offset: 0
      bit_size: 32
 fieldset/OEM1KEYR2:
-  description: "FLASH OEM1 key register 2 "
+  description: FLASH OEM1 key register 2
  fields:
    - name: OEM1KEY
      description: OEM1 most significant bytes key
      bit_offset: 0
      bit_size: 32
 fieldset/OEM2KEYR1:
-  description: "FLASH OEM2 key register 1 "
+  description: FLASH OEM2 key register 1
  fields:
    - name: OEM2KEY
      description: OEM2 least significant bytes key
      bit_offset: 0
      bit_size: 32
 fieldset/OEM2KEYR2:
-  description: "FLASH OEM2 key register 2 "
+  description: FLASH OEM2 key register 2
  fields:
    - name: OEM2KEY
      description: OEM2 most significant bytes key
      bit_offset: 0
      bit_size: 32
 fieldset/OPSR:
-  description: "FLASH operation status register "
+  description: FLASH operation status register
  fields:
    - name: ADDR_OP
      description: "Interrupted operation address\r This field indicates which address in the Flash memory was accessed when reset occurred. The address is given by bank from address 0x0 0000 to 0xF FFF0."
@ -441,14 +441,14 @@ fieldset/OPSR:
      bit_size: 3
      enum: CODE_OP
 fieldset/OPTKEYR:
-  description: "FLASH option key register "
+  description: FLASH option key register
  fields:
    - name: OPTKEY
      description: Option byte key
      bit_offset: 0
      bit_size: 32
 fieldset/OPTR:
-  description: "FLASH option register "
+  description: FLASH option register
  fields:
    - name: RDP
      description: "Readout protection level\r Others: Level 1 (memories readout protection active)\r Note: Refer to for more details."
@ -557,14 +557,14 @@ fieldset/OPTR:
      bit_offset: 31
      bit_size: 1
 fieldset/PDKEY1R:
-  description: "FLASH bank 1 power-down key register "
+  description: FLASH bank 1 power-down key register
  fields:
    - name: PDKEY1
      description: Bank 1 power-down key
      bit_offset: 0
      bit_size: 32
 fieldset/PDKEY2R:
-  description: "FLASH bank 2 power-down key register "
+  description: FLASH bank 2 power-down key register
  fields:
    - name: PDKEY2
      description: Bank 2 power-down key
@ -1619,7 +1619,7 @@ fieldset/PRIV2BBR4:
      bit_offset: 31
      bit_size: 1
 fieldset/PRIVCFGR:
-  description: "FLASH privilege configuration register "
+  description: FLASH privilege configuration register
  fields:
    - name: SPRIV
      description: "Privileged protection for secure registers\r This bit can be accessed only when TrustZone is enabled (TZEN = 1). This bit can be read by both privileged or unprivileged, secure and non-secure access.\r The SPRIV bit can be written only by a secure privileged access. A non-secure write access on SPRIV bit is ignored. A secure unprivileged write access on SPRIV bit is ignored."
@ -2680,7 +2680,7 @@ fieldset/SEC2BBR4:
      bit_offset: 31
      bit_size: 1
 fieldset/SECBOOTADD0R:
-  description: "FLASH secure boot address 0 register "
+  description: FLASH secure boot address 0 register
  fields:
    - name: BOOT_LOCK
      description: "Boot lock\r When set, the boot is always forced to base address value programmed in SECBOOTADD0[24:0] option bytes whatever the boot selection option. When set, this bit can only be cleared by an RDP at level 0."
@ -2691,7 +2691,7 @@ fieldset/SECBOOTADD0R:
      bit_offset: 7
      bit_size: 25
 fieldset/SECCR:
-  description: "FLASH secure control register "
+  description: FLASH secure control register
  fields:
    - name: PG
      description: Secure programming
@ -2751,7 +2751,7 @@ fieldset/SECCR:
      bit_offset: 31
      bit_size: 1
 fieldset/SECHDPCR:
-  description: "FLASH secure HDP control register "
+  description: FLASH secure HDP control register
  fields:
    - name: HDP1_ACCDIS
      description: "HDP1 area access disable\r When set, this bit is only cleared by a system reset."
@ -2764,14 +2764,14 @@ fieldset/SECHDPCR:
      bit_size: 1
      enum: HDP_ACCDIS
 fieldset/SECKEYR:
-  description: "FLASH secure key register "
+  description: FLASH secure key register
  fields:
    - name: SECKEY
      description: Flash memory secure key
      bit_offset: 0
      bit_size: 32
 fieldset/SECSR:
-  description: "FLASH secure status register "
+  description: FLASH secure status register
  fields:
    - name: EOP
      description: "Secure end of operation\r This bit is set by hardware when one or more Flash memory secure operation (program/erase) has been completed successfully. This bit is set only if the secure end of operation interrupts are enabled (EOPIE = 1 in FLASH_SECCR). This bit is cleared by writing 1."
@ -2810,7 +2810,7 @@ fieldset/SECSR:
      bit_offset: 17
      bit_size: 1
 fieldset/SECWM1R1:
-  description: "FLASH secure watermark1 register 1 "
+  description: FLASH secure watermark1 register 1
  fields:
    - name: SECWM1_PSTRT
      description: "Start page of first secure area\r This field contains the first page of the secure area in bank 1."
@ -2821,7 +2821,7 @@ fieldset/SECWM1R1:
      bit_offset: 16
      bit_size: 7
 fieldset/SECWM1R2:
-  description: "FLASH secure watermark1 register 2 "
+  description: FLASH secure watermark1 register 2
  fields:
    - name: HDP1_PEND
      description: "End page of first hide protection area\r This field contains the last page of the HDP area in bank 1."
@ -2832,7 +2832,7 @@ fieldset/SECWM1R2:
      bit_offset: 31
      bit_size: 1
 fieldset/SECWM2R1:
-  description: "FLASH secure watermark2 register 1 "
+  description: FLASH secure watermark2 register 1
  fields:
    - name: SECWM2_PSTRT
      description: "Start page of second secure area\r This field contains the first page of the secure area in bank 2."
@ -2843,7 +2843,7 @@ fieldset/SECWM2R1:
      bit_offset: 16
      bit_size: 7
 fieldset/SECWM2R2:
-  description: "FLASH secure watermark2 register 2 "
+  description: FLASH secure watermark2 register 2
  fields:
    - name: HDP2_PEND
      description: "End page of hide protection second area\r HDP2_PEND contains the last page of the HDP area in bank 2."
@ -2854,7 +2854,7 @@ fieldset/SECWM2R2:
      bit_offset: 31
      bit_size: 1
 fieldset/WRP1AR:
-  description: "FLASH WRP1 area A address register "
+  description: FLASH WRP1 area A address register
  fields:
    - name: WRP1A_PSTRT
      description: "bank 1 WPR first area A start page\r This field contains the first page of the first WPR area for bank 1."
@ -2870,7 +2870,7 @@ fieldset/WRP1AR:
      bit_size: 1
      enum: WRPAR_UNLOCK
 fieldset/WRP1BR:
-  description: "FLASH WRP1 area B address register "
+  description: FLASH WRP1 area B address register
  fields:
    - name: WRP1B_PSTRT
      description: "Bank 1 WRP second area B start page\r This field contains the first page of the second WRP area for bank 1."
@ -2886,7 +2886,7 @@ fieldset/WRP1BR:
      bit_size: 1
      enum: WRPBR_UNLOCK
 fieldset/WRP2AR:
-  description: "FLASH WPR2 area A address register "
+  description: FLASH WPR2 area A address register
  fields:
    - name: WRP2A_PSTRT
      description: "Bank 2 WPR first area A start page\r This field contains the first page of the first WRP area for bank 2."
@ -2902,7 +2902,7 @@ fieldset/WRP2AR:
      bit_size: 1
      enum: WRPAR_UNLOCK
 fieldset/WRP2BR:
-  description: "FLASH WPR2 area B address register "
+  description: FLASH WPR2 area B address register
  fields:
    - name: WRP2B_PSTRT
      description: "Bank 2 WPR second area B start page\r This field contains the first page of the second WRP area for bank 2."
@ -2948,19 +2948,19 @@ enum/BOR_LEV:
  bit_size: 3
  variants:
    - name: B_0x0
-      description: "BOR level 0 (reset level threshold around 1.7 V) "
+      description: BOR level 0 (reset level threshold around 1.7 V)
      value: 0
    - name: B_0x1
-      description: "BOR level 1 (reset level threshold around 2.0 V) "
+      description: BOR level 1 (reset level threshold around 2.0 V)
      value: 1
    - name: B_0x2
-      description: "BOR level 2 (reset level threshold around 2.2 V) "
+      description: BOR level 2 (reset level threshold around 2.2 V)
      value: 2
    - name: B_0x3
-      description: "BOR level 3 (reset level threshold around 2.5 V) "
+      description: BOR level 3 (reset level threshold around 2.5 V)
      value: 3
    - name: B_0x4
-      description: "BOR level 4 (reset level threshold around 2.8 V) "
+      description: BOR level 4 (reset level threshold around 2.8 V)
      value: 4
 enum/CODE_OP:
  bit_size: 3
@ -3017,19 +3017,19 @@ enum/IO_VDDIO_HSLV:
  bit_size: 1
  variants:
    - name: B_0x0
-      description: "High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V) "
+      description: High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V)
      value: 0
    - name: B_0x1
-      description: "High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) "
+      description: High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V)
      value: 1
 enum/IO_VDD_HSLV:
  bit_size: 1
  variants:
    - name: B_0x0
-      description: "High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V) "
+      description: High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V)
      value: 0
    - name: B_0x1
-      description: "High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V) "
+      description: High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V)
      value: 1
 enum/IWDG_STDBY:
  bit_size: 1
--- a/data/registers/fsmc_v1.yaml
+++ b/data/registers/fsmc_v1.yaml
@ -38,26 +38,10 @@ block/FSMC:
      description: PC Card/NAND Flash control register 2
      byte_offset: 96
      fieldset: PCR
    - name: PCR3
      description: PC Card/NAND Flash control register 3
      byte_offset: 128
      fieldset: PCR
    - name: PCR4
      description: PC Card/NAND Flash control register 4
      byte_offset: 160
      fieldset: PCR
    - name: SR2
      description: FIFO status and interrupt register 2
      byte_offset: 100
      fieldset: SR
    - name: SR3
      description: FIFO status and interrupt register 3
      byte_offset: 132
      fieldset: SR
    - name: SR4
      description: FIFO status and interrupt register 4
      byte_offset: 164
      fieldset: SR
    - name: PMEM2
      description: Common memory space timing register 2
      byte_offset: 104
@ -71,6 +55,14 @@ block/FSMC:
      byte_offset: 116
      access: Read
      fieldset: ECCR
    - name: PCR3
      description: PC Card/NAND Flash control register 3
      byte_offset: 128
      fieldset: PCR
    - name: SR3
      description: FIFO status and interrupt register 3
      byte_offset: 132
      fieldset: SR
    - name: PMEM3
      description: Common memory space timing register 3
      byte_offset: 136
@ -84,6 +76,14 @@ block/FSMC:
      byte_offset: 148
      access: Read
      fieldset: ECCR
    - name: PCR4
      description: PC Card/NAND Flash control register 4
      byte_offset: 160
      fieldset: PCR
    - name: SR4
      description: FIFO status and interrupt register 4
      byte_offset: 164
      fieldset: SR
    - name: PMEM4
      description: Common memory space timing register 4
      byte_offset: 168
@ -141,7 +141,6 @@ block/FSMC:
      byte_offset: 344
      access: Read
      fieldset: SDSR
 fieldset/BCR:
  description: SRAM/NOR-Flash chip-select control register
  fields:
--- a/data/registers/gpio_v1.yaml
+++ b/data/registers/gpio_v1.yaml
@ -72,7 +72,7 @@ fieldset/CR:
        stride: 4
      enum: MODE
    - name: CNF_IN
-      description: Port n configuration bits, for input mode
+      description: "Port n configuration bits, for input mode"
      bit_offset: 2
      bit_size: 2
      array:
@ -80,7 +80,7 @@ fieldset/CR:
        stride: 4
      enum: CNF_IN
    - name: CNF_OUT
-      description: Port n configuration bits, for output mode
+      description: "Port n configuration bits, for output mode"
      bit_offset: 2
      bit_size: 2
      array:
--- a/data/registers/otgfs_v1.yaml
+++ b/data/registers/otgfs_v1.yaml
--- a/data/registers/pwr_u5.yaml
+++ b/data/registers/pwr_u5.yaml
@ -3,82 +3,82 @@ block/PWR:
  description: Power control
  items:
    - name: CR1
-      description: "PWR control register 1 "
+      description: PWR control register 1
      byte_offset: 0
      fieldset: CR1
    - name: CR2
-      description: "PWR control register 2 "
+      description: PWR control register 2
      byte_offset: 4
      fieldset: CR2
    - name: CR3
-      description: "PWR control register 3 "
+      description: PWR control register 3
      byte_offset: 8
      fieldset: CR3
    - name: VOSR
-      description: "PWR voltage scaling register "
+      description: PWR voltage scaling register
      byte_offset: 12
      fieldset: VOSR
    - name: SVMCR
-      description: "PWR supply voltage monitoring control register "
+      description: PWR supply voltage monitoring control register
      byte_offset: 16
      fieldset: SVMCR
    - name: WUCR1
-      description: "PWR wakeup control register 1 "
+      description: PWR wakeup control register 1
      byte_offset: 20
      fieldset: WUCR1
    - name: WUCR2
-      description: "PWR wakeup control register 2 "
+      description: PWR wakeup control register 2
      byte_offset: 24
      fieldset: WUCR2
    - name: WUCR3
-      description: "PWR wakeup control register 3 "
+      description: PWR wakeup control register 3
      byte_offset: 28
      fieldset: WUCR3
    - name: BDCR1
-      description: "PWR Backup domain control register 1 "
+      description: PWR Backup domain control register 1
      byte_offset: 32
      fieldset: BDCR1
    - name: BDCR2
-      description: "PWR Backup domain control register 2 "
+      description: PWR Backup domain control register 2
      byte_offset: 36
      fieldset: BDCR2
    - name: DBPR
-      description: "PWR disable Backup domain register "
+      description: PWR disable Backup domain register
      byte_offset: 40
      fieldset: DBPR
    - name: UCPDR
-      description: "PWR USB Type-C™ and Power Delivery register "
+      description: PWR USB Type-C™ and Power Delivery register
      byte_offset: 44
      fieldset: UCPDR
    - name: SECCFGR
-      description: "PWR security configuration register "
+      description: PWR security configuration register
      byte_offset: 48
      fieldset: SECCFGR
    - name: PRIVCFGR
-      description: "PWR privilege control register "
+      description: PWR privilege control register
      byte_offset: 52
      fieldset: PRIVCFGR
    - name: SR
-      description: "PWR status register "
+      description: PWR status register
      byte_offset: 56
      fieldset: SR
    - name: SVMSR
      byte_offset: 60
      fieldset: SVMSR
    - name: BDSR
-      description: "PWR Backup domain status register "
+      description: PWR Backup domain status register
      byte_offset: 64
      fieldset: BDSR
    - name: WUSR
-      description: "PWR wakeup status register "
+      description: PWR wakeup status register
      byte_offset: 68
      fieldset: WUSR
    - name: WUSCR
-      description: "PWR wakeup status clear register "
+      description: PWR wakeup status clear register
      byte_offset: 72
      fieldset: WUSCR
    - name: APCR
-      description: "PWR apply pull configuration register "
+      description: PWR apply pull configuration register
      byte_offset: 76
      fieldset: APCR
    - name: PUCR
@ -96,14 +96,14 @@ block/PWR:
      byte_offset: 84
      fieldset: PCR
 fieldset/APCR:
-  description: "PWR apply pull configuration register "
+  description: PWR apply pull configuration register
  fields:
    - name: APC
      description: "Apply pull-up and pull-down configuration\r When this bit is set, the I/O pull-up and pull-down configurations defined in PUCRx and PDCRx are applied. When this bit is cleared, PUCRx and PDCRx are not applied to the I/Os."
      bit_offset: 0
      bit_size: 1
 fieldset/BDCR1:
-  description: "PWR Backup domain control register 1 "
+  description: PWR Backup domain control register 1
  fields:
    - name: BREN
      description: "Backup RAM retention in Standby and VBAT modes\r When this bit is set, the backup RAM content is kept in Standby and VBAT modes.\r If BREN is reset, the backup RAM can still be used in Run, Sleep and Stop modes. However, its content is lost in Standby, Shutdown and VBAT modes. This bit can be written only when the regulator is LDO, which must be configured before switching to SMPS.\r Note: Backup RAM cannot be preserved in Shutdown mode."
@ -114,7 +114,7 @@ fieldset/BDCR1:
      bit_offset: 4
      bit_size: 1
 fieldset/BDCR2:
-  description: "PWR Backup domain control register 2 "
+  description: PWR Backup domain control register 2
  fields:
    - name: VBE
      description: VBAT charging enable
@ -127,7 +127,7 @@ fieldset/BDCR2:
      bit_size: 1
      enum: VBRS
 fieldset/BDSR:
-  description: "PWR Backup domain status register "
+  description: PWR Backup domain status register
  fields:
    - name: VBATH
      description: Backup domain voltage level monitoring versus high threshold
@ -145,7 +145,7 @@ fieldset/BDSR:
      bit_size: 1
      enum: TEMPH
 fieldset/CR1:
-  description: "PWR control register 1 "
+  description: PWR control register 1
  fields:
    - name: LPMS
      description: "Low-power mode selection\r These bits select the low-power mode entered when the CPU enters the Deepsleep mode.\r 10x: Standby mode (Standby mode also entered if LPMS = 11X in CR1\r with BREN = 1 in BDCR1)\r 11x: Shutdown mode if BREN = 0 in BDCR1"
@ -187,7 +187,7 @@ fieldset/CR1:
      bit_size: 1
      enum: SRAMPD
 fieldset/CR2:
-  description: "PWR control register 2 "
+  description: PWR control register 2
  fields:
    - name: SRAM1PDS1
      description: "SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)"
@ -300,7 +300,7 @@ fieldset/CR2:
      bit_size: 1
      enum: SRDRUN
 fieldset/CR3:
-  description: "PWR control register 3 "
+  description: PWR control register 3
  fields:
    - name: REGSEL
      description: "Regulator selection\r Note: REGSEL is reserved and must be kept at reset value in packages without SMPS."
@ -312,7 +312,7 @@ fieldset/CR3:
      bit_offset: 2
      bit_size: 1
 fieldset/DBPR:
-  description: "PWR disable Backup domain register "
+  description: PWR disable Backup domain register
  fields:
    - name: DBP
      description: "Disable Backup domain write protection\r In reset state, all registers and SRAM in Backup domain are protected against parasitic write access. This bit must be set to enable the write access to these registers."
@ -330,7 +330,7 @@ fieldset/PCR:
        len: 16
        stride: 1
 fieldset/PRIVCFGR:
-  description: "PWR privilege control register "
+  description: PWR privilege control register
  fields:
    - name: SPRIV
      description: "PWR secure functions privilege configuration\r This bit is set and reset by software. It can be written only by a secure privileged access."
@ -343,7 +343,7 @@ fieldset/PRIVCFGR:
      bit_size: 1
      enum: NSPRIV
 fieldset/SECCFGR:
-  description: "PWR security configuration register "
+  description: PWR security configuration register
  fields:
    - name: WUP1SEC
      description: WUP1 secure protection
@ -406,7 +406,7 @@ fieldset/SECCFGR:
      bit_size: 1
      enum: APCSEC
 fieldset/SR:
-  description: "PWR status register "
+  description: PWR status register
  fields:
    - name: CSSF
      description: "Clear Stop and Standby flags\r This bit is protected against non-secure access when LPMSEC = 1 in SECCFGR.\r This bit is protected against unprivileged access when LPMSEC = 1 and SPRIV = 1 in PRIVCFGR, or when LPMSEC = 0 and NSPRIV = 1.\r Writing 1 to this bit clears the STOPF and SBF flags."
@ -423,7 +423,7 @@ fieldset/SR:
      bit_size: 1
      enum: SBF
 fieldset/SVMCR:
-  description: "PWR supply voltage monitoring control register "
+  description: PWR supply voltage monitoring control register
  fields:
    - name: PVDE
      description: Power voltage detector enable
@ -509,7 +509,7 @@ fieldset/SVMSR:
      bit_size: 1
      enum: VDDARDY
 fieldset/UCPDR:
-  description: "PWR USB Type-C™ and Power Delivery register "
+  description: PWR USB Type-C™ and Power Delivery register
  fields:
    - name: UCPD_DBDIS
      description: "UCPD dead battery disable\r After exiting reset, the USB Type-C “dead battery” behavior is enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all cases, either to stop this pull-down or to handover control to the UCPD (the UCPD must be initialized before doing the disable)."
@ -521,7 +521,7 @@ fieldset/UCPDR:
      bit_offset: 1
      bit_size: 1
 fieldset/VOSR:
-  description: "PWR voltage scaling register "
+  description: PWR voltage scaling register
  fields:
    - name: BOOSTRDY
      description: "EPOD booster ready\r This bit is set to 1 by hardware when the power booster startup time is reached. The system clock frequency can be switched higher than 50 MHz only after this bit is set."
@ -543,7 +543,7 @@ fieldset/VOSR:
      bit_offset: 18
      bit_size: 1
 fieldset/WUCR1:
-  description: "PWR wakeup control register 1 "
+  description: PWR wakeup control register 1
  fields:
    - name: WUPEN1
      description: Wakeup pin WKUP1 enable
@ -578,7 +578,7 @@ fieldset/WUCR1:
      bit_offset: 7
      bit_size: 1
 fieldset/WUCR2:
-  description: "PWR wakeup control register 2 "
+  description: PWR wakeup control register 2
  fields:
    - name: WUPP1
      description: "Wakeup pin WKUP1 polarity.\r This bit must be configured when WUPEN1 = 0."
@ -621,7 +621,7 @@ fieldset/WUCR2:
      bit_size: 1
      enum: WUPP
 fieldset/WUCR3:
-  description: "PWR wakeup control register 3 "
+  description: PWR wakeup control register 3
  fields:
    - name: WUSEL1
      description: "Wakeup pin WKUP1 selection\r This field must be configured when WUPEN1 = 0."
@ -664,7 +664,7 @@ fieldset/WUCR3:
      bit_size: 2
      enum: WUSEL
 fieldset/WUSCR:
-  description: "PWR wakeup status clear register "
+  description: PWR wakeup status clear register
  fields:
    - name: CWUF1
      description: "Wakeup flag 1\r Writing 1 to this bit clears the WUF1 flag in WUSR."
@ -699,7 +699,7 @@ fieldset/WUSCR:
      bit_offset: 7
      bit_size: 1
 fieldset/WUSR:
-  description: "PWR wakeup status register "
+  description: PWR wakeup status register
  fields:
    - name: WUF1
      description: "Wakeup flag 1\r This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by writing 1 in the CWUF1 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN1 = 0."
@ -902,25 +902,25 @@ enum/PVDLS:
  bit_size: 3
  variants:
    - name: B_0x0
-      description: "VPVD0 around 2.0 V "
+      description: VPVD0 around 2.0 V
      value: 0
    - name: B_0x1
-      description: "VPVD1 around 2.2 V "
+      description: VPVD1 around 2.2 V
      value: 1
    - name: B_0x2
-      description: "VPVD2 around 2.4 V "
+      description: VPVD2 around 2.4 V
      value: 2
    - name: B_0x3
-      description: "VPVD3 around 2.5 V "
+      description: VPVD3 around 2.5 V
      value: 3
    - name: B_0x4
-      description: "VPVD4 around 2.6 V "
+      description: VPVD4 around 2.6 V
      value: 4
    - name: B_0x5
-      description: "VPVD5 around 2.8 V "
+      description: VPVD5 around 2.8 V
      value: 5
    - name: B_0x6
-      description: "VPVD6 around 2.9 V "
+      description: VPVD6 around 2.9 V
      value: 6
    - name: B_0x7
      description: External input analog voltage PVD_IN (compared internally to VREFINT)
@ -1067,7 +1067,7 @@ enum/VBATH:
      description: Backup domain voltage level < high threshold
      value: 0
    - name: B_0x1
-      description: "Backup domain voltage level ≥ high threshold "
+      description: Backup domain voltage level ≥ high threshold
      value: 1
 enum/VBE:
  bit_size: 1
@ -1100,10 +1100,10 @@ enum/VDDARDY:
  bit_size: 1
  variants:
    - name: B_0x0
-      description: "VDDA is below the threshold of the VDDA voltage monitor 2 (around 1.8 V). "
+      description: VDDA is below the threshold of the VDDA voltage monitor 2 (around 1.8 V).
      value: 0
    - name: B_0x1
-      description: "VDDA is equal or above the threshold of the VDDA voltage monitor 2 (around 1.8 V). "
+      description: VDDA is equal or above the threshold of the VDDA voltage monitor 2 (around 1.8 V).
      value: 1
 enum/VDDIORDY:
  bit_size: 1
--- a/data/registers/rcc_g0.yaml
+++ b/data/registers/rcc_g0.yaml
--- a/data/registers/rcc_h7.yaml
+++ b/data/registers/rcc_h7.yaml
@ -322,7 +322,7 @@ fieldset/AHB1ENR:
      bit_offset: 17
      bit_size: 1
    - name: USB2OTGHSULPIEN
-      description: " Enable USB_PHY2 clocks "
+      description: Enable USB_PHY2 clocks
      bit_offset: 18
      bit_size: 1
    - name: USB1OTGEN
--- a/data/registers/rcc_h7ab.yaml
+++ b/data/registers/rcc_h7ab.yaml
@ -246,7 +246,7 @@ fieldset/AHB1ENR:
      bit_offset: 17
      bit_size: 1
    - name: USB2OTGHSULPIEN
-      description: " Enable USB_PHY2 clocks "
+      description: Enable USB_PHY2 clocks
      bit_offset: 18
      bit_size: 1
    - name: USB1OTGEN
@ -700,14 +700,14 @@ fieldset/AHB4ENR:
      description: CRC peripheral clock enable
      bit_offset: 19
      bit_size: 1
    - name: BDMAEN
      description: BDMA and DMAMUX2 Clock Enable
      bit_offset: 21
      bit_size: 1
    - name: BDMA2EN
      description: BDMA2 and DMAMUX2 Clock Enable
      bit_offset: 21
      bit_size: 1
    - name: BDMAEN
      description: BDMA and DMAMUX2 Clock Enable
      bit_offset: 21
      bit_size: 1
    - name: ADC3EN
      description: ADC3 Peripheral Clocks Enable
      bit_offset: 24
@ -771,14 +771,14 @@ fieldset/AHB4LPENR:
      description: CRC peripheral clock enable during CSleep mode
      bit_offset: 19
      bit_size: 1
    - name: BDMALPEN
      description: BDMA Clock Enable During CSleep Mode
      bit_offset: 21
      bit_size: 1
    - name: BDMA2LPEN
      description: BDMA2 Clock Enable During CSleep Mode
      bit_offset: 21
      bit_size: 1
    - name: BDMALPEN
      description: BDMA Clock Enable During CSleep Mode
      bit_offset: 21
      bit_size: 1
    - name: ADC3LPEN
      description: ADC3 Peripheral Clocks Enable During CSleep Mode
      bit_offset: 24
@ -842,14 +842,14 @@ fieldset/AHB4RSTR:
      description: CRC block reset
      bit_offset: 19
      bit_size: 1
    - name: BDMARST
      description: BDMA block reset
      bit_offset: 21
      bit_size: 1
    - name: BDMA2RST
      description: BDMA2 block reset
      bit_offset: 21
      bit_size: 1
    - name: BDMARST
      description: BDMA block reset
      bit_offset: 21
      bit_size: 1
    - name: ADC3RST
      description: ADC3 block reset
      bit_offset: 24
@ -2163,14 +2163,14 @@ fieldset/D2CFGR:
 fieldset/D3AMR:
  description: RCC D3 Autonomous mode Register
  fields:
    - name: BDMAAMEN
      description: BDMA and DMAMUX Autonomous mode enable
      bit_offset: 0
      bit_size: 1
    - name: BDMA2AMEN
      description: BDMA2 and DMAMUX Autonomous mode enable
      bit_offset: 0
      bit_size: 1
    - name: BDMAAMEN
      description: BDMA and DMAMUX Autonomous mode enable
      bit_offset: 0
      bit_size: 1
    - name: LPUART1AMEN
      description: LPUART1 Autonomous mode enable
      bit_offset: 3
--- a/data/registers/rcc_l5.yaml
+++ b/data/registers/rcc_l5.yaml
--- a/data/registers/rcc_u5.yaml
+++ b/data/registers/rcc_u5.yaml
@ -3,151 +3,151 @@ block/RCC:
  description: Reset and clock control
  items:
    - name: CR
-      description: "RCC clock control register "
+      description: RCC clock control register
      byte_offset: 0
      fieldset: CR
    - name: ICSCR1
-      description: "RCC internal clock sources calibration register 1 "
+      description: RCC internal clock sources calibration register 1
      byte_offset: 8
      fieldset: ICSCR1
    - name: ICSCR2
-      description: "RCC internal clock sources calibration register 2 "
+      description: RCC internal clock sources calibration register 2
      byte_offset: 12
      fieldset: ICSCR2
    - name: ICSCR3
-      description: "RCC internal clock sources calibration register 3 "
+      description: RCC internal clock sources calibration register 3
      byte_offset: 16
      fieldset: ICSCR3
    - name: CRRCR
-      description: "RCC clock recovery RC register "
+      description: RCC clock recovery RC register
      byte_offset: 20
      fieldset: CRRCR
    - name: CFGR1
-      description: "RCC clock configuration register 1 "
+      description: RCC clock configuration register 1
      byte_offset: 28
      fieldset: CFGR1
    - name: CFGR2
-      description: "RCC clock configuration register 2 "
+      description: RCC clock configuration register 2
      byte_offset: 32
      fieldset: CFGR2
    - name: CFGR3
-      description: "RCC clock configuration register 3 "
+      description: RCC clock configuration register 3
      byte_offset: 36
      fieldset: CFGR3
    - name: PLL1CFGR
-      description: "RCC PLL1 configuration register "
+      description: RCC PLL1 configuration register
      byte_offset: 40
      fieldset: PLL1CFGR
    - name: PLL2CFGR
-      description: "RCC PLL2 configuration register "
+      description: RCC PLL2 configuration register
      byte_offset: 44
      fieldset: PLL2CFGR
    - name: PLL3CFGR
-      description: "RCC PLL3 configuration register "
+      description: RCC PLL3 configuration register
      byte_offset: 48
      fieldset: PLL3CFGR
    - name: PLL1DIVR
-      description: "RCC PLL1 dividers register "
+      description: RCC PLL1 dividers register
      byte_offset: 52
      fieldset: PLL1DIVR
    - name: PLL1FRACR
-      description: "RCC PLL1 fractional divider register "
+      description: RCC PLL1 fractional divider register
      byte_offset: 56
      fieldset: PLL1FRACR
    - name: PLL2DIVR
-      description: "RCC PLL2 dividers configuration register "
+      description: RCC PLL2 dividers configuration register
      byte_offset: 60
      fieldset: PLL2DIVR
    - name: PLL2FRACR
-      description: "RCC PLL2 fractional divider register "
+      description: RCC PLL2 fractional divider register
      byte_offset: 64
      fieldset: PLL2FRACR
    - name: PLL3DIVR
-      description: "RCC PLL3 dividers configuration register "
+      description: RCC PLL3 dividers configuration register
      byte_offset: 68
      fieldset: PLL3DIVR
    - name: PLL3FRACR
-      description: "RCC PLL3 fractional divider register "
+      description: RCC PLL3 fractional divider register
      byte_offset: 72
      fieldset: PLL3FRACR
    - name: CIER
-      description: "RCC clock interrupt enable register "
+      description: RCC clock interrupt enable register
      byte_offset: 80
      fieldset: CIER
    - name: CIFR
-      description: "RCC clock interrupt flag register "
+      description: RCC clock interrupt flag register
      byte_offset: 84
      fieldset: CIFR
    - name: CICR
-      description: "RCC clock interrupt clear register "
+      description: RCC clock interrupt clear register
      byte_offset: 88
      fieldset: CICR
    - name: AHB1RSTR
-      description: "RCC AHB1 peripheral reset register "
+      description: RCC AHB1 peripheral reset register
      byte_offset: 96
      fieldset: AHB1RSTR
    - name: AHB2RSTR1
-      description: "RCC AHB2 peripheral reset register 1 "
+      description: RCC AHB2 peripheral reset register 1
      byte_offset: 100
      fieldset: AHB2RSTR1
    - name: AHB2RSTR2
-      description: "RCC AHB2 peripheral reset register 2 "
+      description: RCC AHB2 peripheral reset register 2
      byte_offset: 104
      fieldset: AHB2RSTR2
    - name: AHB3RSTR
-      description: "RCC AHB3 peripheral reset register "
+      description: RCC AHB3 peripheral reset register
      byte_offset: 108
      fieldset: AHB3RSTR
    - name: APB1RSTR1
-      description: "RCC APB1 peripheral reset register 1 "
+      description: RCC APB1 peripheral reset register 1
      byte_offset: 116
      fieldset: APB1RSTR1
    - name: APB1RSTR2
-      description: "RCC APB1 peripheral reset register 2 "
+      description: RCC APB1 peripheral reset register 2
      byte_offset: 120
      fieldset: APB1RSTR2
    - name: APB2RSTR
-      description: "RCC APB2 peripheral reset register "
+      description: RCC APB2 peripheral reset register
      byte_offset: 124
      fieldset: APB2RSTR
    - name: APB3RSTR
-      description: "RCC APB3 peripheral reset register "
+      description: RCC APB3 peripheral reset register
      byte_offset: 128
      fieldset: APB3RSTR
    - name: AHB1ENR
-      description: "RCC AHB1 peripheral clock enable register "
+      description: RCC AHB1 peripheral clock enable register
      byte_offset: 136
      fieldset: AHB1ENR
    - name: AHB2ENR1
-      description: "RCC AHB2 peripheral clock enable register 1 "
+      description: RCC AHB2 peripheral clock enable register 1
      byte_offset: 140
      fieldset: AHB2ENR1
    - name: AHB2ENR2
-      description: "RCC AHB2 peripheral clock enable register 2 "
+      description: RCC AHB2 peripheral clock enable register 2
      byte_offset: 144
      fieldset: AHB2ENR2
    - name: AHB3ENR
-      description: "RCC AHB3 peripheral clock enable register "
+      description: RCC AHB3 peripheral clock enable register
      byte_offset: 148
      fieldset: AHB3ENR
    - name: APB1ENR1
-      description: "RCC APB1 peripheral clock enable register 1 "
+      description: RCC APB1 peripheral clock enable register 1
      byte_offset: 156
      fieldset: APB1ENR1
    - name: APB1ENR2
-      description: "RCC APB1 peripheral clock enable register 2 "
+      description: RCC APB1 peripheral clock enable register 2
      byte_offset: 160
      fieldset: APB1ENR2
    - name: APB2ENR
-      description: "RCC APB2 peripheral clock enable register "
+      description: RCC APB2 peripheral clock enable register
      byte_offset: 164
      fieldset: APB2ENR
    - name: APB3ENR
-      description: "RCC APB3 peripheral clock enable register "
+      description: RCC APB3 peripheral clock enable register
      byte_offset: 168
      fieldset: APB3ENR
    - name: AHB1SMENR
-      description: "RCC AHB1 peripheral clocks enable in Sleep and Stop modes register\t"
+      description: RCC AHB1 peripheral clocks enable in Sleep and Stop modes register
      byte_offset: 176
      fieldset: AHB1SMENR
    - name: AHB2SMENR1
@ -159,7 +159,7 @@ block/RCC:
      byte_offset: 184
      fieldset: AHB2SMENR2
    - name: AHB3SMENR
-      description: "RCC AHB3 peripheral clocks enable in Sleep and Stop modes register\t"
+      description: RCC AHB3 peripheral clocks enable in Sleep and Stop modes register
      byte_offset: 188
      fieldset: AHB3SMENR
    - name: APB1SMENR1
@ -171,47 +171,47 @@ block/RCC:
      byte_offset: 200
      fieldset: APB1SMENR2
    - name: APB2SMENR
-      description: "RCC APB2 peripheral clocks enable in Sleep and Stop modes register\t"
+      description: RCC APB2 peripheral clocks enable in Sleep and Stop modes register
      byte_offset: 204
      fieldset: APB2SMENR
    - name: APB3SMENR
-      description: "RCC APB3 peripheral clock enable in Sleep and Stop modes register\t"
+      description: RCC APB3 peripheral clock enable in Sleep and Stop modes register
      byte_offset: 208
      fieldset: APB3SMENR
    - name: SRDAMR
-      description: "RCC SmartRun domain peripheral autonomous mode register\t"
+      description: RCC SmartRun domain peripheral autonomous mode register
      byte_offset: 216
      fieldset: SRDAMR
    - name: CCIPR1
-      description: "RCC peripherals independent clock configuration register 1\t"
+      description: RCC peripherals independent clock configuration register 1
      byte_offset: 224
      fieldset: CCIPR1
    - name: CCIPR2
-      description: "RCC peripherals independent clock configuration register 2\t"
+      description: RCC peripherals independent clock configuration register 2
      byte_offset: 228
      fieldset: CCIPR2
    - name: CCIPR3
-      description: "RCC peripherals independent clock configuration register 3\t"
+      description: RCC peripherals independent clock configuration register 3
      byte_offset: 232
      fieldset: CCIPR3
    - name: BDCR
-      description: "RCC Backup domain control register "
+      description: RCC Backup domain control register
      byte_offset: 240
      fieldset: BDCR
    - name: CSR
-      description: "RCC control/status register "
+      description: RCC control/status register
      byte_offset: 244
      fieldset: CSR
    - name: SECCFGR
-      description: "RCC secure configuration register "
+      description: RCC secure configuration register
      byte_offset: 272
      fieldset: SECCFGR
    - name: PRIVCFGR
-      description: "RCC privilege configuration register "
+      description: RCC privilege configuration register
      byte_offset: 276
      fieldset: PRIVCFGR
 fieldset/AHB1ENR:
-  description: "RCC AHB1 peripheral clock enable register "
+  description: RCC AHB1 peripheral clock enable register
  fields:
    - name: GPDMA1EN
      description: "GPDMA1 clock enable\r Set and cleared by software."
@ -266,7 +266,7 @@ fieldset/AHB1ENR:
      bit_offset: 31
      bit_size: 1
 fieldset/AHB1RSTR:
-  description: "RCC AHB1 peripheral reset register "
+  description: RCC AHB1 peripheral reset register
  fields:
    - name: GPDMA1RST
      description: "GPDMA1 reset\r Set and cleared by software."
@ -301,7 +301,7 @@ fieldset/AHB1RSTR:
      bit_offset: 18
      bit_size: 1
 fieldset/AHB1SMENR:
-  description: "RCC AHB1 peripheral clocks enable in Sleep and Stop modes register\t"
+  description: RCC AHB1 peripheral clocks enable in Sleep and Stop modes register
  fields:
    - name: GPDMA1SMEN
      description: "GPDMA1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
@ -360,7 +360,7 @@ fieldset/AHB1SMENR:
      bit_offset: 31
      bit_size: 1
 fieldset/AHB2ENR1:
-  description: "RCC AHB2 peripheral clock enable register 1 "
+  description: RCC AHB2 peripheral clock enable register 1
  fields:
    - name: GPIOAEN
      description: "IO port A clock enable\r Set and cleared by software."
@ -459,7 +459,7 @@ fieldset/AHB2ENR1:
      bit_offset: 31
      bit_size: 1
 fieldset/AHB2ENR2:
-  description: "RCC AHB2 peripheral clock enable register 2 "
+  description: RCC AHB2 peripheral clock enable register 2
  fields:
    - name: FSMCEN
      description: "FSMC clock enable\r Set and cleared by software."
@ -474,7 +474,7 @@ fieldset/AHB2ENR2:
      bit_offset: 8
      bit_size: 1
 fieldset/AHB2RSTR1:
-  description: "RCC AHB2 peripheral reset register 1 "
+  description: RCC AHB2 peripheral reset register 1
  fields:
    - name: GPIOARST
      description: "IO port A reset\r Set and cleared by software."
@ -565,7 +565,7 @@ fieldset/AHB2RSTR1:
      bit_offset: 28
      bit_size: 1
 fieldset/AHB2RSTR2:
-  description: "RCC AHB2 peripheral reset register 2 "
+  description: RCC AHB2 peripheral reset register 2
  fields:
    - name: FSMCRST
      description: "Flexible memory controller reset\r Set and cleared by software."
@ -694,7 +694,7 @@ fieldset/AHB2SMENR2:
      bit_offset: 8
      bit_size: 1
 fieldset/AHB3ENR:
-  description: "RCC AHB3 peripheral clock enable register "
+  description: RCC AHB3 peripheral clock enable register
  fields:
    - name: LPGPIO1EN
      description: "LPGPIO1 enable\r Set and cleared by software."
@ -729,7 +729,7 @@ fieldset/AHB3ENR:
      bit_offset: 31
      bit_size: 1
 fieldset/AHB3RSTR:
-  description: "RCC AHB3 peripheral reset register "
+  description: RCC AHB3 peripheral reset register
  fields:
    - name: LPGPIO1RST
      description: "LPGPIO1 reset\r Set and cleared by software."
@ -752,7 +752,7 @@ fieldset/AHB3RSTR:
      bit_offset: 10
      bit_size: 1
 fieldset/AHB3SMENR:
-  description: "RCC AHB3 peripheral clocks enable in Sleep and Stop modes register\t"
+  description: RCC AHB3 peripheral clocks enable in Sleep and Stop modes register
  fields:
    - name: LPGPIO1SMEN
      description: "LPGPIO1 enable during Sleep and Stop modes\r Set and cleared by software."
@ -787,7 +787,7 @@ fieldset/AHB3SMENR:
      bit_offset: 31
      bit_size: 1
 fieldset/APB1ENR1:
-  description: "RCC APB1 peripheral clock enable register 1 "
+  description: RCC APB1 peripheral clock enable register 1
  fields:
    - name: TIM2EN
      description: "TIM2 clock enable\r Set and cleared by software."
@ -850,7 +850,7 @@ fieldset/APB1ENR1:
      bit_offset: 24
      bit_size: 1
 fieldset/APB1ENR2:
-  description: "RCC APB1 peripheral clock enable register 2 "
+  description: RCC APB1 peripheral clock enable register 2
  fields:
    - name: I2C4EN
      description: "I2C4 clock enable\r Set and cleared by software"
@ -869,7 +869,7 @@ fieldset/APB1ENR2:
      bit_offset: 23
      bit_size: 1
 fieldset/APB1RSTR1:
-  description: "RCC APB1 peripheral reset register 1 "
+  description: RCC APB1 peripheral reset register 1
  fields:
    - name: TIM2RST
      description: "TIM2 reset\r Set and cleared by software."
@ -928,7 +928,7 @@ fieldset/APB1RSTR1:
      bit_offset: 24
      bit_size: 1
 fieldset/APB1RSTR2:
-  description: "RCC APB1 peripheral reset register 2 "
+  description: RCC APB1 peripheral reset register 2
  fields:
    - name: I2C4RST
      description: "I2C4 reset\r Set and cleared by software"
@ -1029,7 +1029,7 @@ fieldset/APB1SMENR2:
      bit_offset: 23
      bit_size: 1
 fieldset/APB2ENR:
-  description: "RCC APB2 peripheral clock enable register "
+  description: RCC APB2 peripheral clock enable register
  fields:
    - name: TIM1EN
      description: "TIM1 clock enable\r Set and cleared by software."
@ -1068,7 +1068,7 @@ fieldset/APB2ENR:
      bit_offset: 22
      bit_size: 1
 fieldset/APB2RSTR:
-  description: "RCC APB2 peripheral reset register "
+  description: RCC APB2 peripheral reset register
  fields:
    - name: TIM1RST
      description: "TIM1 reset\r Set and cleared by software."
@ -1107,7 +1107,7 @@ fieldset/APB2RSTR:
      bit_offset: 22
      bit_size: 1
 fieldset/APB2SMENR:
-  description: "RCC APB2 peripheral clocks enable in Sleep and Stop modes register\t"
+  description: RCC APB2 peripheral clocks enable in Sleep and Stop modes register
  fields:
    - name: TIM1SMEN
      description: "TIM1 clocks enable during Sleep and Stop modes\r Set and cleared by software."
@ -1146,7 +1146,7 @@ fieldset/APB2SMENR:
      bit_offset: 22
      bit_size: 1
 fieldset/APB3ENR:
-  description: "RCC APB3 peripheral clock enable register "
+  description: RCC APB3 peripheral clock enable register
  fields:
    - name: SYSCFGEN
      description: "SYSCFG clock enable\r Set and cleared by software."
@ -1193,7 +1193,7 @@ fieldset/APB3ENR:
      bit_offset: 21
      bit_size: 1
 fieldset/APB3RSTR:
-  description: "RCC APB3 peripheral reset register "
+  description: RCC APB3 peripheral reset register
  fields:
    - name: SYSCFGRST
      description: "SYSCFG reset\r Set and cleared by software."
@ -1236,7 +1236,7 @@ fieldset/APB3RSTR:
      bit_offset: 20
      bit_size: 1
 fieldset/APB3SMENR:
-  description: "RCC APB3 peripheral clock enable in Sleep and Stop modes register\t"
+  description: RCC APB3 peripheral clock enable in Sleep and Stop modes register
  fields:
    - name: SYSCFGSMEN
      description: "SYSCFG clocks enable during Sleep and Stop modes\r Set and cleared by software."
@ -1283,7 +1283,7 @@ fieldset/APB3SMENR:
      bit_offset: 21
      bit_size: 1
 fieldset/BDCR:
-  description: "RCC Backup domain control register "
+  description: RCC Backup domain control register
  fields:
    - name: LSEON
      description: "LSE oscillator enable\r Set and cleared by software."
@ -1358,7 +1358,7 @@ fieldset/BDCR:
      bit_size: 1
      enum: LSIPREDIV
 fieldset/CCIPR1:
-  description: "RCC peripherals independent clock configuration register 1\t"
+  description: RCC peripherals independent clock configuration register 1
  fields:
    - name: USART1SEL
      description: "USART1 kernel clock source selection\r This bits are used to select the USART1 kernel clock source.\r Note: The USART1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE."
@ -1436,7 +1436,7 @@ fieldset/CCIPR1:
      bit_size: 3
      enum: TIMICSEL
 fieldset/CCIPR2:
-  description: "RCC peripherals independent clock configuration register 2\t"
+  description: RCC peripherals independent clock configuration register 2
  fields:
    - name: MDF1SEL
      description: "MDF1 kernel clock source selection\r These bits are used to select the MDF1 kernel clock source.\r others: reserved"
@ -1474,7 +1474,7 @@ fieldset/CCIPR2:
      bit_size: 2
      enum: OCTOSPISEL
 fieldset/CCIPR3:
-  description: "RCC peripherals independent clock configuration register 3\t"
+  description: RCC peripherals independent clock configuration register 3
  fields:
    - name: LPUART1SEL
      description: "LPUART1 kernel clock source selection\r These bits are used to select the LPUART1 kernel clock source.\r others: reserved\r Note: The LPUART1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI16, LSE or MSIK."
@ -1517,7 +1517,7 @@ fieldset/CCIPR3:
      bit_size: 3
      enum: ADFSEL
 fieldset/CFGR1:
-  description: "RCC clock configuration register 1 "
+  description: RCC clock configuration register 1
  fields:
    - name: SW
      description: "system clock switch\r Set and cleared by software to select system clock source (SYSCLK).\r Configured by hardware to force MSIS oscillator selection when exiting Standby or Shutdown mode. Configured by hardware to force MSIS or HSI16 oscillator selection when exiting Stop mode or in case of HSE oscillator failure, depending on STOPWUCK value."
@ -1550,7 +1550,7 @@ fieldset/CFGR1:
      bit_size: 3
      enum: MCOPRE
 fieldset/CFGR2:
-  description: "RCC clock configuration register 2 "
+  description: RCC clock configuration register 2
  fields:
    - name: HPRE
      description: "AHB prescaler\r Set and cleared by software to control the division factor of the AHB clock (HCLK).\r Depending on the device voltage range, the software must set these bits correctly to ensure that the system frequency does not exceed the maximum allowed frequency (for more details, refer to ). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account.\r 0xxx: SYSCLK not divided"
@ -1588,7 +1588,7 @@ fieldset/CFGR2:
      bit_offset: 20
      bit_size: 1
 fieldset/CFGR3:
-  description: "RCC clock configuration register 3 "
+  description: RCC clock configuration register 3
  fields:
    - name: PPRE3
      description: "APB3 prescaler\r Set and cleared by software to control the division factor of the APB3 clock (PCLK3).\r 0xx: HCLK not divided"
@ -1604,7 +1604,7 @@ fieldset/CFGR3:
      bit_offset: 17
      bit_size: 1
 fieldset/CICR:
-  description: "RCC clock interrupt clear register "
+  description: RCC clock interrupt clear register
  fields:
    - name: LSIRDYC
      description: "LSI ready interrupt clear\r Writing this bit to 1 clears the LSIRDYF flag. Writing 0 has no effect."
@ -1650,7 +1650,7 @@ fieldset/CICR:
      bit_offset: 12
      bit_size: 1
 fieldset/CIER:
-  description: "RCC clock interrupt enable register "
+  description: RCC clock interrupt enable register
  fields:
    - name: LSIRDYIE
      description: "LSI ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization."
@ -1692,7 +1692,7 @@ fieldset/CIER:
      bit_offset: 12
      bit_size: 1
 fieldset/CIFR:
-  description: "RCC clock interrupt flag register "
+  description: RCC clock interrupt flag register
  fields:
    - name: LSIRDYF
      description: "LSI ready interrupt flag\r Set by hardware when the LSI clock becomes stable and LSIRDYIE is set.\r Cleared by software setting the LSIRDYC bit."
@ -1738,7 +1738,7 @@ fieldset/CIFR:
      bit_offset: 12
      bit_size: 1
 fieldset/CR:
-  description: "RCC clock control register "
+  description: RCC clock control register
  fields:
    - name: MSISON
      description: "MSIS clock enable\r Set and cleared by software.\r Cleared by hardware to stop the MSIS oscillator when entering Stop, Standby or Shutdown mode.\r Set by hardware to force the MSIS oscillator ON when exiting Standby or Shutdown mode.\r Set by hardware to force the MSIS oscillator ON when STOPWUCK = 0 when exiting Stop modes or in case of a failure of the HSE oscillator.\r Set by hardware when used directly or indirectly as system clock."
@ -1838,14 +1838,14 @@ fieldset/CR:
        len: 3
        stride: 2
 fieldset/CRRCR:
-  description: "RCC clock recovery RC register "
+  description: RCC clock recovery RC register
  fields:
    - name: HSI48CAL
      description: "HSI48 clock calibration\r These bits are initialized at startup with the factory-programmed HSI48 calibration trim value."
      bit_offset: 0
      bit_size: 9
 fieldset/CSR:
-  description: "RCC control/status register "
+  description: RCC control/status register
  fields:
    - name: MSIKSRANGE
      description: "MSIK range after Standby mode\r Set by software to chose the MSIK frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4 MHz. MSIKSRANGE can be written only when MSIRGSEL = 1.\r others: reserved\r Note: Changing the MSIKSRANGE does not change the current MSIK frequency."
@ -1890,7 +1890,7 @@ fieldset/CSR:
      bit_offset: 31
      bit_size: 1
 fieldset/ICSCR1:
-  description: "RCC internal clock sources calibration register 1 "
+  description: RCC internal clock sources calibration register 1
  fields:
    - name: MSICAL3
      description: "MSIRC3 clock calibration for MSI ranges 12 to 15\r These bits are initialized at startup with the factory-programmed MSIRC3 calibration trim value for ranges 12 to 15. When MSITRIM3 is written, MSICAL3 is updated with the sum of MSITRIM3[4:0] and the factory calibration trim value MSIRC2[4:0].\r There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level."
@ -1929,7 +1929,7 @@ fieldset/ICSCR1:
      bit_size: 4
      enum: MSIRANGE
 fieldset/ICSCR2:
-  description: "RCC internal clock sources calibration register 2 "
+  description: RCC internal clock sources calibration register 2
  fields:
    - name: MSITRIM3
      description: "MSI clock trimming for ranges 12 to 15\r These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC3[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI."
@ -1948,7 +1948,7 @@ fieldset/ICSCR2:
      bit_offset: 15
      bit_size: 5
 fieldset/ICSCR3:
-  description: "RCC internal clock sources calibration register 3 "
+  description: RCC internal clock sources calibration register 3
  fields:
    - name: HSICAL
      description: "HSI clock calibration\r These bits are initialized at startup with the factory-programmed HSI calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value."
@ -1959,7 +1959,7 @@ fieldset/ICSCR3:
      bit_offset: 16
      bit_size: 5
 fieldset/PLL1CFGR:
-  description: "RCC PLL1 configuration register "
+  description: RCC PLL1 configuration register
  fields:
    - name: PLLSRC
      description: "PLL1 entry clock source\r Set and cleared by software to select PLL1 clock source. These bits can be written only when the PLL1 is disabled.\r In order to save power, when no PLL1 is used, the value of PLL1SRC must be 0."
@ -1998,7 +1998,7 @@ fieldset/PLL1CFGR:
      bit_offset: 18
      bit_size: 1
 fieldset/PLL1DIVR:
-  description: "RCC PLL1 dividers register "
+  description: RCC PLL1 dividers register
  fields:
    - name: PLLN
      description: "Multiplication factor for PLL1 VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ...\r ...\r Others: reserved\r VCO output frequency = Fref1_ck x PLL1N, when fractional value 0 has been loaded into PLL1FRACN, with:\r PLL1N between 4 and 512\r input frequency Fref1_ck between 4 and 16 MHz"
@ -2017,14 +2017,14 @@ fieldset/PLL1DIVR:
      bit_offset: 24
      bit_size: 7
 fieldset/PLL1FRACR:
-  description: "RCC PLL1 fractional divider register "
+  description: RCC PLL1 fractional divider register
  fields:
    - name: PLLFRACN
      description: "Fractional part of the multiplication factor for PLL1 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO.\r These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO.\r VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with:\r PLL1N must be between 4 and 512.\r PLL1FRACN can be between 0 and 213- 1.\r The input frequency Fref1_ck must be between 4 and 16 MHz.\r To change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:\r Set the bit PLL1FRACEN to 0.\r Write the new fractional value into PLL1FRACN.\r Set the bit PLL1FRACEN to 1."
      bit_offset: 3
      bit_size: 13
 fieldset/PLL2CFGR:
-  description: "RCC PLL2 configuration register "
+  description: RCC PLL2 configuration register
  fields:
    - name: PLLSRC
      description: "PLL2 entry clock source\r Set and cleared by software to select PLL2 clock source. These bits can be written only when the PLL2 is disabled.\r In order to save power, when no PLL2 is used, the value of PLL2SRC must be 0."
@ -2058,7 +2058,7 @@ fieldset/PLL2CFGR:
      bit_offset: 18
      bit_size: 1
 fieldset/PLL2DIVR:
-  description: "RCC PLL2 dividers configuration register "
+  description: RCC PLL2 dividers configuration register
  fields:
    - name: PLLN
      description: "Multiplication factor for PLL2 VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL is disabled (PLL2ON = 0 and PLL2RDY = 0).\r ...\r ...\r Others: reserved\r VCO output frequency = Fref2_ck x PLL2N, when fractional value 0 has been loaded into PLL2FRACN, with:\r PLL2N between 4 and 512\r input frequency Fref2_ck between 1MHz and 16MHz"
@ -2077,14 +2077,14 @@ fieldset/PLL2DIVR:
      bit_offset: 24
      bit_size: 7
 fieldset/PLL2FRACR:
-  description: "RCC PLL2 fractional divider register "
+  description: RCC PLL2 fractional divider register
  fields:
    - name: PLLFRACN
      description: "Fractional part of the multiplication factor for PLL2 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO.\r These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO.\r VCO output frequency = Fref2_ck x (PLL2N + (PLL2FRACN / 213)), with\r PLL2N must be between 4 and 512.\r PLL2FRACN can be between 0 and 213 - 1.\r The input frequency Fref2_ck must be between 4 and 16 MHz.\r In order to change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:\r Set the bit PLL2FRACEN to 0.\r Write the new fractional value into PLL2FRACN.\r Set the bit PLL2FRACEN to 1."
      bit_offset: 3
      bit_size: 13
 fieldset/PLL3CFGR:
-  description: "RCC PLL3 configuration register "
+  description: RCC PLL3 configuration register
  fields:
    - name: PLLSRC
      description: "PLL3 entry clock source\r Set and cleared by software to select PLL3 clock source. These bits can be written only when the PLL3 is disabled.\r In order to save power, when no PLL3 is used, the value of PLL3SRC must be 00."
@ -2121,7 +2121,7 @@ fieldset/PLL3CFGR:
      bit_offset: 18
      bit_size: 1
 fieldset/PLL3DIVR:
-  description: "RCC PLL3 dividers configuration register "
+  description: RCC PLL3 dividers configuration register
  fields:
    - name: PLLN
      description: "Multiplication factor for PLL3 VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL is disabled (PLL3ON = 0 and PLL3RDY = 0).\r ...\r ...\r Others: reserved\r VCO output frequency = Fref3_ck x PLL3N, when fractional value 0 has been loaded into PLL3FRACN, with:\r PLL3N between 4 and 512\r input frequency Fref3_ck between 4 and 16MHz"
@ -2140,14 +2140,14 @@ fieldset/PLL3DIVR:
      bit_offset: 24
      bit_size: 7
 fieldset/PLL3FRACR:
-  description: "RCC PLL3 fractional divider register "
+  description: RCC PLL3 fractional divider register
  fields:
    - name: PLLFRACN
      description: "Fractional part of the multiplication factor for PLL3 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO.\r These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO.\r VCO output frequency = Fref3_ck x (PLL3N + (PLL3FRACN / 213)), with:\r PLL3N must be between 4 and 512.\r PLL3FRACN can be between 0 and 213 - 1.\r The input frequency Fref3_ck must be between 4 and 16 MHz.\r In order to change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:\r Set the bit PLL3FRACEN to 0.\r Write the new fractional value into PLL3FRACN.\r Set the bit PLL3FRACEN to 1."
      bit_offset: 3
      bit_size: 13
 fieldset/PRIVCFGR:
-  description: "RCC privilege configuration register "
+  description: RCC privilege configuration register
  fields:
    - name: SPRIV
      description: "RCC secure functions privilege configuration\r Set and reset by software. This bit can be written only by a secure privileged access."
@ -2160,7 +2160,7 @@ fieldset/PRIVCFGR:
      bit_size: 1
      enum: PRIV
 fieldset/SECCFGR:
-  description: "RCC secure configuration register "
+  description: RCC secure configuration register
  fields:
    - name: HSISEC
      description: "HSI clock configuration and status bits security\r Set and reset by software."
@ -2221,7 +2221,7 @@ fieldset/SECCFGR:
      bit_size: 1
      enum: SECURITY
 fieldset/SRDAMR:
-  description: "RCC SmartRun domain peripheral autonomous mode register\t"
+  description: RCC SmartRun domain peripheral autonomous mode register
  fields:
    - name: SPI3AMEN
      description: "SPI3 autonomous mode enable in Stop 0,1, 2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
@ -2339,7 +2339,7 @@ enum/FDCANSEL:
  bit_size: 2
  variants:
    - name: HSE
-      description: "HSE clock selected "
+      description: HSE clock selected
      value: 0
    - name: PLL1_Q
      description: PLL1 Q (pll1_q_ck) selected
@ -2573,7 +2573,7 @@ enum/MSIPLLSEL:
  bit_size: 1
  variants:
    - name: MSIK
-      description: "PLL mode applied to MSIK (MSI kernel) clock output "
+      description: PLL mode applied to MSIK (MSI kernel) clock output
      value: 0
    - name: MSIS
      description: PLL mode applied to MSIS (MSI system) clock output
@ -2582,52 +2582,52 @@ enum/MSIRANGE:
  bit_size: 4
  variants:
    - name: RANGE_48MHZ
-      description: "range 0 around 48 MHz "
+      description: range 0 around 48 MHz
      value: 0
    - name: RANGE_24MHZ
-      description: "range 1 around 24 MHz "
+      description: range 1 around 24 MHz
      value: 1
    - name: RANGE_16MHZ
-      description: "range 2 around 16 MHz "
+      description: range 2 around 16 MHz
      value: 2
    - name: RANGE_12MHZ
-      description: "range 3 around 12 MHz "
+      description: range 3 around 12 MHz
      value: 3
    - name: RANGE_4MHZ
-      description: "range 4 around 4 MHz (reset value) "
+      description: range 4 around 4 MHz (reset value)
      value: 4
    - name: RANGE_2MHZ
-      description: "range 5 around 2 MHz "
+      description: range 5 around 2 MHz
      value: 5
    - name: RANGE_1_33MHZ
-      description: "range 6 around 1.33 MHz "
+      description: range 6 around 1.33 MHz
      value: 6
    - name: RANGE_1MHZ
-      description: "range 7 around 1 MHz "
+      description: range 7 around 1 MHz
      value: 7
    - name: RANGE_3_072MHZ
-      description: "range 8 around 3.072 MHz "
+      description: range 8 around 3.072 MHz
      value: 8
    - name: RANGE_1_536MHZ
-      description: "range 9 around 1.536 MHz "
+      description: range 9 around 1.536 MHz
      value: 9
    - name: RANGE_1_024MHZ
-      description: "range 10 around 1.024 MHz "
+      description: range 10 around 1.024 MHz
      value: 10
    - name: RANGE_768KHZ
-      description: "range 11 around 768 kHz "
+      description: range 11 around 768 kHz
      value: 11
    - name: RANGE_400KHZ
-      description: "range 12 around 400 kHz "
+      description: range 12 around 400 kHz
      value: 12
    - name: RANGE_200KHZ
-      description: "range 13 around 200 kHz "
+      description: range 13 around 200 kHz
      value: 13
    - name: RANGE_133KHZ
      description: range 14 around 133 kHz
      value: 14
    - name: RANGE_100KHZ
-      description: "range 15 around 100 kHz "
+      description: range 15 around 100 kHz
      value: 15
 enum/MSIRGSEL:
  bit_size: 1
@ -2642,19 +2642,19 @@ enum/MSIXSRANGE:
  bit_size: 4
  variants:
    - name: RANGE_4MHZ
-      description: "range 4 around 4M Hz (reset value) "
+      description: range 4 around 4M Hz (reset value)
      value: 4
    - name: RANGE_2MHZ
-      description: "range 5 around 2 MHz "
+      description: range 5 around 2 MHz
      value: 5
    - name: RANGE_1_5MHZ
-      description: "range 6 around 1.5 MHz "
+      description: range 6 around 1.5 MHz
      value: 6
    - name: RANGE_1MHZ
-      description: "range 7 around 1 MHz "
+      description: range 7 around 1 MHz
      value: 7
    - name: RANGE_3_072MHZ
-      description: "range 8 around 3.072 MHz "
+      description: range 8 around 3.072 MHz
      value: 8
 enum/OCTOSPISEL:
  bit_size: 2
@ -2771,7 +2771,7 @@ enum/RNGSEL:
  bit_size: 2
  variants:
    - name: HSI48
-      description: "HSI48 selected "
+      description: HSI48 selected
      value: 0
    - name: HSI48_DIV2
      description: "HSI48 / 2 selected, can be used in Range 4"
--- a/data/registers/sdmmc_v1.yaml
+++ b/data/registers/sdmmc_v1.yaml
@ -195,13 +195,6 @@ fieldset/DTIMER:
      description: Data timeout period
      bit_offset: 0
      bit_size: 32
 fieldset/FIFOR:
  description: data FIFO register
  fields:
    - name: FIFOData
      description: Receive and transmit FIFO data
      bit_offset: 0
      bit_size: 32
 fieldset/FIFOCNT:
  description: FIFO counter register
  fields:
@ -209,6 +202,13 @@ fieldset/FIFOCNT:
      description: Remaining number of words to be written to or read from the FIFO
      bit_offset: 0
      bit_size: 24
 fieldset/FIFOR:
  description: data FIFO register
  fields:
    - name: FIFOData
      description: Receive and transmit FIFO data
      bit_offset: 0
      bit_size: 32
 fieldset/ICR:
  description: interrupt clear register
  fields:
--- a/data/registers/syscfg_f2.yaml
+++ b/data/registers/syscfg_f2.yaml
@ -22,6 +22,27 @@ block/SYSCFG:
      byte_offset: 32
      access: Read
      fieldset: CMPCR
 fieldset/CMPCR:
  description: Compensation cell control register
  fields:
    - name: CMP_PD
      description: Compensation cell power-down
      bit_offset: 0
      bit_size: 1
    - name: READY
      description: Compensation cell ready flag
      bit_offset: 8
      bit_size: 1
 fieldset/EXTICR:
  description: external interrupt configuration register 1
  fields:
    - name: EXTI
      description: EXTI x configuration (x = 0 to 3)
      bit_offset: 0
      bit_size: 4
      array:
        len: 4
        stride: 4
 fieldset/MEMRMP:
  description: memory remap register
  fields:
@ -37,27 +58,6 @@ fieldset/PMC:
      description: Ethernet PHY interface selection
      bit_offset: 23
      bit_size: 1
 fieldset/EXTICR:
  description: external interrupt configuration register 1
  fields:
    - name: EXTI
      description: EXTI x configuration (x = 0 to 3)
      bit_offset: 0
      bit_size: 4
      array:
        len: 4
        stride: 4
 fieldset/CMPCR:
  description: Compensation cell control register
  fields:
    - name: CMP_PD
      description: Compensation cell power-down
      bit_offset: 0
      bit_size: 1
    - name: READY
      description: Compensation cell ready flag
      bit_offset: 8
      bit_size: 1
 enum/MEM_MODE:
  bit_size: 2
  variants:
--- a/data/registers/syscfg_h7.yaml
+++ b/data/registers/syscfg_h7.yaml
@ -242,7 +242,7 @@ fieldset/PWRCR:
  description: SYSCFG power control register
  fields:
    - name: ODEN
-      description: " Overdrive enable"
+      description: Overdrive enable
      bit_offset: 0
      bit_size: 4
 fieldset/UR0: