stm32-data/data/registers/pwr_u5.yaml

---
block/PWR:
  description: Power control
  items:
    - name: CR1
      description: PWR control register 1
      byte_offset: 0
      fieldset: CR1
    - name: CR2
      description: PWR control register 2
      byte_offset: 4
      fieldset: CR2
    - name: CR3
      description: PWR control register 3
      byte_offset: 8
      fieldset: CR3
    - name: VOSR
      description: PWR voltage scaling register
      byte_offset: 12
      fieldset: VOSR
    - name: SVMCR
      description: PWR supply voltage monitoring control register
      byte_offset: 16
      fieldset: SVMCR
    - name: WUCR1
      description: PWR wakeup control register 1
      byte_offset: 20
      fieldset: WUCR1
    - name: WUCR2
      description: PWR wakeup control register 2
      byte_offset: 24
      fieldset: WUCR2
    - name: WUCR3
      description: PWR wakeup control register 3
      byte_offset: 28
      fieldset: WUCR3
    - name: BDCR1
      description: PWR Backup domain control register 1
      byte_offset: 32
      fieldset: BDCR1
    - name: BDCR2
      description: PWR Backup domain control register 2
      byte_offset: 36
      fieldset: BDCR2
    - name: DBPR
      description: PWR disable Backup domain register
      byte_offset: 40
      fieldset: DBPR
    - name: UCPDR
      description: PWR USB Type-C™ and Power Delivery register
      byte_offset: 44
      fieldset: UCPDR
    - name: SECCFGR
      description: PWR security configuration register
      byte_offset: 48
      fieldset: SECCFGR
    - name: PRIVCFGR
      description: PWR privilege control register
      byte_offset: 52
      fieldset: PRIVCFGR
    - name: SR
      description: PWR status register
      byte_offset: 56
      fieldset: SR
    - name: SVMSR
      byte_offset: 60
      fieldset: SVMSR
    - name: BDSR
      description: PWR Backup domain status register
      byte_offset: 64
      fieldset: BDSR
    - name: WUSR
      description: PWR wakeup status register
      byte_offset: 68
      fieldset: WUSR
    - name: WUSCR
      description: PWR wakeup status clear register
      byte_offset: 72
      fieldset: WUSCR
    - name: APCR
      description: PWR apply pull configuration register
      byte_offset: 76
      fieldset: APCR
    - name: PUCR
      description: Power Port pull-up control register
      array:
        len: 9
        stride: 8
      byte_offset: 80
      fieldset: PCR
    - name: PDCR
      description: Power Port pull-down control register
      array:
        len: 9
        stride: 8
      byte_offset: 84
      fieldset: PCR
fieldset/APCR:
  description: PWR apply pull configuration register
  fields:
    - name: APC
      description: "Apply pull-up and pull-down configuration\r When this bit is set, the I/O pull-up and pull-down configurations defined in PUCRx and PDCRx are applied. When this bit is cleared, PUCRx and PDCRx are not applied to the I/Os."
      bit_offset: 0
      bit_size: 1
fieldset/BDCR1:
  description: PWR Backup domain control register 1
  fields:
    - name: BREN
      description: "Backup RAM retention in Standby and VBAT modes\r When this bit is set, the backup RAM content is kept in Standby and VBAT modes.\r If BREN is reset, the backup RAM can still be used in Run, Sleep and Stop modes. However, its content is lost in Standby, Shutdown and VBAT modes. This bit can be written only when the regulator is LDO, which must be configured before switching to SMPS.\r Note: Backup RAM cannot be preserved in Shutdown mode."
      bit_offset: 0
      bit_size: 1
    - name: MONEN
      description: Backup domain voltage and temperature monitoring enable
      bit_offset: 4
      bit_size: 1
fieldset/BDCR2:
  description: PWR Backup domain control register 2
  fields:
    - name: VBE
      description: VBAT charging enable
      bit_offset: 0
      bit_size: 1
      enum: VBE
    - name: VBRS
      description: VBAT charging resistor selection
      bit_offset: 1
      bit_size: 1
      enum: VBRS
fieldset/BDSR:
  description: PWR Backup domain status register
  fields:
    - name: VBATH
      description: Backup domain voltage level monitoring versus high threshold
      bit_offset: 1
      bit_size: 1
      enum: VBATH
    - name: TEMPL
      description: Temperature level monitoring versus low threshold
      bit_offset: 2
      bit_size: 1
      enum: TEMPL
    - name: TEMPH
      description: Temperature level monitoring versus high threshold
      bit_offset: 3
      bit_size: 1
      enum: TEMPH
fieldset/CR1:
  description: PWR control register 1
  fields:
    - name: LPMS
      description: "Low-power mode selection\r These bits select the low-power mode entered when the CPU enters the Deepsleep mode.\r 10x: Standby mode (Standby mode also entered if LPMS = 11X in CR1\r with BREN = 1 in BDCR1)\r 11x: Shutdown mode if BREN = 0 in BDCR1"
      bit_offset: 0
      bit_size: 3
      enum: LPMS
    - name: RRSB1
      description: "SRAM2 page 1 retention in Stop 3 and Standby modes\r This bit is used to keep the SRAM2 page 1 content in Stop 3 and Standby modes. The SRAM2 page 1 corresponds to the first 8 Kbytes of the SRAM2\r (from SRAM2 base address to SRAM2 base address + 0x1FFF).\r Note: This bit has no effect in Shutdown mode."
      bit_offset: 5
      bit_size: 1
      enum: RRSB
    - name: RRSB2
      description: "SRAM2 page 2 retention in Stop 3 and Standby modes\r This bit is used to keep the SRAM2 page 2 content in Stop 3 and Standby modes. The SRAM2 page 2 corresponds to the last 56 Kbytes of the SRAM2\r (from SRAM2 base address + 0x2000 to SRAM2 base address + 0xFFFF).\r Note: This bit has no effect in Shutdown mode."
      bit_offset: 6
      bit_size: 1
      enum: RRSB
    - name: ULPMEN
      description: "BOR ultra-low power mode\r This bit is used to reduce the consumption by configuring the BOR in discontinuous mode.\r This bit must be set to reach the lowest power consumption in the low-power modes."
      bit_offset: 7
      bit_size: 1
    - name: SRAM1PD
      description: "SRAM1 power down\r This bit is used to reduce the consumption by powering off the SRAM1."
      bit_offset: 8
      bit_size: 1
      enum: SRAMPD
    - name: SRAM2PD
      description: "SRAM2 power down\r This bit is used to reduce the consumption by powering off the SRAM2."
      bit_offset: 9
      bit_size: 1
      enum: SRAMPD
    - name: SRAM3PD
      description: "SRAM3 power down\r This bit is used to reduce the consumption by powering off the SRAM3."
      bit_offset: 10
      bit_size: 1
      enum: SRAMPD
    - name: SRAM4PD
      description: "SRAM4 power down\r This bit is used to reduce the consumption by powering off the SRAM4."
      bit_offset: 11
      bit_size: 1
      enum: SRAMPD
fieldset/CR2:
  description: PWR control register 2
  fields:
    - name: SRAM1PDS1
      description: "SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)"
      bit_offset: 0
      bit_size: 1
      enum: SRAMPDS
    - name: SRAM1PDS2
      description: "SRAM1 page 2 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)"
      bit_offset: 1
      bit_size: 1
      enum: SRAMPDS
    - name: SRAM1PDS3
      description: "SRAM1 page 3 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)"
      bit_offset: 2
      bit_size: 1
      enum: SRAMPDS
    - name: SRAM2PDS1
      description: "SRAM2 page 1 (8 Kbytes) power-down in Stop modes (Stop 0, 1, 2)\r Note: The SRAM2 page 1 retention in Stop 3 is controlled by RRSB1 bit in CR1."
      bit_offset: 4
      bit_size: 1
      enum: SRAMPDS
    - name: SRAM2PDS2
      description: "SRAM2 page 2 (56 Kbytes) power-down in Stop modes (Stop 0, 1, 2)\r Note: The SRAM2 page 2 retention in Stop 3 is controlled by RRSB2 bit in CR1."
      bit_offset: 5
      bit_size: 1
      enum: SRAMPDS
    - name: SRAM4PDS
      description: "SRAM4 power-down in Stop modes (Stop 0, 1, 2, 3)"
      bit_offset: 6
      bit_size: 1
      enum: SRAMPDS
    - name: ICRAMPDS
      description: "ICACHE SRAM power-down in Stop modes (Stop 0, 1, 2, 3)"
      bit_offset: 8
      bit_size: 1
      enum: ICRAMPDS
    - name: DC1RAMPDS
      description: "DCACHE1 SRAM power-down in Stop modes (Stop 0, 1, 2, 3)"
      bit_offset: 9
      bit_size: 1
      enum: DCRAMPDS
    - name: DMA2DRAMPDS
      description: "DMA2D SRAM power-down in Stop modes (Stop 0, 1, 2, 3)"
      bit_offset: 10
      bit_size: 1
      enum: DMADRAMPDS
    - name: PRAMPDS
      description: "FMAC, FDCAN and USB peripherals SRAM power-down in Stop modes (Stop 0, 1, 2, 3)"
      bit_offset: 11
      bit_size: 1
      enum: PRAMPDS
    - name: PKARAMPDS
      description: PKA SRAM power-down
      bit_offset: 12
      bit_size: 1
      enum: PKARAMPDS
    - name: SRAM4FWU
      description: "SRAM4 fast wakeup from Stop 0, Stop 1 and Stop 2 modes\r This bit is used to obtain the best trade-off between low-power consumption and wakeup time. SRAM4 wakeup time increases the wakeup time when exiting Stop 0, 1 and 2 modes, and also increases the LPDMA access time to SRAM4 during Stop modes."
      bit_offset: 13
      bit_size: 1
      enum: SRAMFWU
    - name: FLASHFWU
      description: "Flash memory fast wakeup from Stop 0 and Stop 1 modes\r This bit is used to obtain the best trade-off between low-power consumption and wakeup time when exiting the Stop 0 or Stop 1 modes.\r When this bit is set, the Flash memory remains in normal mode in Stop 0 and Stop 1 modes, which offers a faster startup time with higher consumption."
      bit_offset: 14
      bit_size: 1
      enum: FLASHFWU
    - name: SRAM3PDS1
      description: "SRAM3 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)"
      bit_offset: 16
      bit_size: 1
      enum: SRAMPDS
    - name: SRAM3PDS2
      description: "SRAM3 page 2 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)"
      bit_offset: 17
      bit_size: 1
      enum: SRAMPDS
    - name: SRAM3PDS3
      description: "SRAM3 page 3 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)"
      bit_offset: 18
      bit_size: 1
      enum: SRAMPDS
    - name: SRAM3PDS4
      description: "SRAM3 page 4 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)"
      bit_offset: 19
      bit_size: 1
      enum: SRAMPDS
    - name: SRAM3PDS5
      description: "SRAM3 page 5 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)"
      bit_offset: 20
      bit_size: 1
      enum: SRAMPDS
    - name: SRAM3PDS6
      description: "SRAM3 page 6 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)"
      bit_offset: 21
      bit_size: 1
      enum: SRAMPDS
    - name: SRAM3PDS7
      description: "SRAM3 page 7 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)"
      bit_offset: 22
      bit_size: 1
      enum: SRAMPDS
    - name: SRAM3PDS8
      description: "SRAM3 page 8 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)"
      bit_offset: 23
      bit_size: 1
      enum: SRAMPDS
    - name: SRDRUN
      description: SmartRun domain in Run mode
      bit_offset: 31
      bit_size: 1
      enum: SRDRUN
fieldset/CR3:
  description: PWR control register 3
  fields:
    - name: REGSEL
      description: "Regulator selection\r Note: REGSEL is reserved and must be kept at reset value in packages without SMPS."
      bit_offset: 1
      bit_size: 1
      enum: REGSEL
    - name: FSTEN
      description: Fast soft start
      bit_offset: 2
      bit_size: 1
fieldset/DBPR:
  description: PWR disable Backup domain register
  fields:
    - name: DBP
      description: "Disable Backup domain write protection\r In reset state, all registers and SRAM in Backup domain are protected against parasitic write access. This bit must be set to enable the write access to these registers."
      bit_offset: 0
      bit_size: 1
      enum: DBP
fieldset/PCR:
  description: Power Port pull control register
  fields:
    - name: P
      description: Port pull bit y (y=0..15)
      bit_offset: 0
      bit_size: 1
      array:
        len: 16
        stride: 1
fieldset/PRIVCFGR:
  description: PWR privilege control register
  fields:
    - name: SPRIV
      description: "PWR secure functions privilege configuration\r This bit is set and reset by software. It can be written only by a secure privileged access."
      bit_offset: 0
      bit_size: 1
      enum: SPRIV
    - name: NSPRIV
      description: "PWR non-secure functions privilege configuration\r This bit is set and reset by software. It can be written only by privileged access, secure or non-secure."
      bit_offset: 1
      bit_size: 1
      enum: NSPRIV
fieldset/SECCFGR:
  description: PWR security configuration register
  fields:
    - name: WUP1SEC
      description: WUP1 secure protection
      bit_offset: 0
      bit_size: 1
      enum: WUPSEC
    - name: WUP2SEC
      description: WUP2 secure protection
      bit_offset: 1
      bit_size: 1
      enum: WUPSEC
    - name: WUP3SEC
      description: WUP3 secure protection
      bit_offset: 2
      bit_size: 1
      enum: WUPSEC
    - name: WUP4SEC
      description: WUP4 secure protection
      bit_offset: 3
      bit_size: 1
      enum: WUPSEC
    - name: WUP5SEC
      description: WUP5 secure protection
      bit_offset: 4
      bit_size: 1
      enum: WUPSEC
    - name: WUP6SEC
      description: WUP6 secure protection
      bit_offset: 5
      bit_size: 1
      enum: WUPSEC
    - name: WUP7SEC
      description: WUP7 secure protection
      bit_offset: 6
      bit_size: 1
      enum: WUPSEC
    - name: WUP8SEC
      description: WUP8 secure protection
      bit_offset: 7
      bit_size: 1
      enum: WUPSEC
    - name: LPMSEC
      description: Low-power modes secure protection
      bit_offset: 12
      bit_size: 1
      enum: LPMSEC
    - name: VDMSEC
      description: Voltage detection and monitoring secure protection
      bit_offset: 13
      bit_size: 1
      enum: VDMSEC
    - name: VBSEC
      description: Backup domain secure protection
      bit_offset: 14
      bit_size: 1
      enum: VBSEC
    - name: APCSEC
      description: Pull-up/pull-down secure protection
      bit_offset: 15
      bit_size: 1
      enum: APCSEC
fieldset/SR:
  description: PWR status register
  fields:
    - name: CSSF
      description: "Clear Stop and Standby flags\r This bit is protected against non-secure access when LPMSEC = 1 in SECCFGR.\r This bit is protected against unprivileged access when LPMSEC = 1 and SPRIV = 1 in PRIVCFGR, or when LPMSEC = 0 and NSPRIV = 1.\r Writing 1 to this bit clears the STOPF and SBF flags."
      bit_offset: 0
      bit_size: 1
    - name: STOPF
      description: "Stop flag\r This bit is set by hardware when the device enters a Stop mode, and is cleared by software by writing 1 to the CSSF bit."
      bit_offset: 1
      bit_size: 1
      enum: STOPF
    - name: SBF
      description: "Standby flag\r This bit is set by hardware when the device enters the Standby mode, and is cleared by writing 1 to the CSSF bit, or by a power-on reset. It is not cleared by the system reset."
      bit_offset: 2
      bit_size: 1
      enum: SBF
fieldset/SVMCR:
  description: PWR supply voltage monitoring control register
  fields:
    - name: PVDE
      description: Power voltage detector enable
      bit_offset: 4
      bit_size: 1
      enum: PVDE
    - name: PVDLS
      description: "Power voltage detector level selection\r These bits select the voltage threshold detected by the power voltage detector:"
      bit_offset: 5
      bit_size: 3
      enum: PVDLS
    - name: UVMEN
      description: VDDUSB independent USB voltage monitor enable
      bit_offset: 24
      bit_size: 1
    - name: IO2VMEN
      description: VDDIO2 independent I/Os voltage monitor enable
      bit_offset: 25
      bit_size: 1
    - name: AVM1EN
      description: VDDA independent analog supply voltage monitor 1 enable (1.6 V threshold)
      bit_offset: 26
      bit_size: 1
    - name: AVM2EN
      description: VDDA independent analog supply voltage monitor 2 enable (1.8 V threshold)
      bit_offset: 27
      bit_size: 1
    - name: USV
      description: VDDUSB independent USB supply valid
      bit_offset: 28
      bit_size: 1
      enum: USV
    - name: IO2SV
      description: "VDDIO2 independent I/Os supply valid\r This bit is used to validate the VDDIO2 supply for electrical and logical isolation purpose.\r Setting this bit is mandatory to use PG[15:2]. If VDDIO2 is not always present in the application, the VDDIO2 voltage monitor can be used to determine whether this supply is ready or not."
      bit_offset: 29
      bit_size: 1
      enum: IOSV
    - name: ASV
      description: VDDA independent analog supply valid
      bit_offset: 30
      bit_size: 1
      enum: ASV
fieldset/SVMSR:
  fields:
    - name: REGS
      description: Regulator selection
      bit_offset: 1
      bit_size: 1
      enum: REGS
    - name: PVDO
      description: VDD voltage detector output
      bit_offset: 4
      bit_size: 1
      enum: PVDO
    - name: ACTVOSRDY
      description: Voltage level ready for currently used VOS
      bit_offset: 15
      bit_size: 1
      enum: ACTVOSRDY
    - name: ACTVOS
      description: "VOS currently applied to VCORE\r This field provides the last VOS value."
      bit_offset: 16
      bit_size: 2
      enum: ACTVOS
    - name: VDDUSBRDY
      description: VDDUSB ready
      bit_offset: 24
      bit_size: 1
      enum: VDDUSBRDY
    - name: VDDIO2RDY
      description: VDDIO2 ready
      bit_offset: 25
      bit_size: 1
      enum: VDDIORDY
    - name: VDDA1RDY
      description: VDDA ready versus 1.6V voltage monitor
      bit_offset: 26
      bit_size: 1
      enum: VDDARDY
    - name: VDDA2RDY
      description: VDDA ready versus 1.8 V voltage monitor
      bit_offset: 27
      bit_size: 1
      enum: VDDARDY
fieldset/UCPDR:
  description: PWR USB Type-C™ and Power Delivery register
  fields:
    - name: UCPD_DBDIS
      description: "UCPD dead battery disable\r After exiting reset, the USB Type-C “dead battery” behavior is enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all cases, either to stop this pull-down or to handover control to the UCPD (the UCPD must be initialized before doing the disable)."
      bit_offset: 0
      bit_size: 1
      enum: UCPD_DBDIS
    - name: UCPD_STBY
      description: "UCPD Standby mode\r When set, this bit is used to memorize the UCPD configuration in Standby mode.\r This bit must be written to 1 just before entering Standby mode when using UCPD.\r It must be written to 0 after exiting the Standby mode and before writing any UCPD registers."
      bit_offset: 1
      bit_size: 1
fieldset/VOSR:
  description: PWR voltage scaling register
  fields:
    - name: BOOSTRDY
      description: "EPOD booster ready\r This bit is set to 1 by hardware when the power booster startup time is reached. The system clock frequency can be switched higher than 50 MHz only after this bit is set."
      bit_offset: 14
      bit_size: 1
      enum: BOOSTRDY
    - name: VOSRDY
      description: Ready bit for VCORE voltage scaling output selection
      bit_offset: 15
      bit_size: 1
      enum: VOSRDY
    - name: VOS
      description: "Voltage scaling range selection\r This field is protected against non-secure access when SYSCLKSEC = 1 in RCC_SECCFGR. It is protected against unprivileged access when SYSCLKSEC = 1 in RCC_SECCFGR and SPRIV = 1 in PRIVCFGR, or when SYSCLKSEC = 0 and NSPRIV = 1."
      bit_offset: 16
      bit_size: 2
      enum: VOS
    - name: BOOSTEN
      description: EPOD booster enable
      bit_offset: 18
      bit_size: 1
fieldset/WUCR1:
  description: PWR wakeup control register 1
  fields:
    - name: WUPEN1
      description: Wakeup pin WKUP1 enable
      bit_offset: 0
      bit_size: 1
    - name: WUPEN2
      description: Wakeup pin WKUP2 enable
      bit_offset: 1
      bit_size: 1
    - name: WUPEN3
      description: Wakeup pin WKUP3 enable
      bit_offset: 2
      bit_size: 1
    - name: WUPEN4
      description: Wakeup pin WKUP4 enable
      bit_offset: 3
      bit_size: 1
    - name: WUPEN5
      description: Wakeup pin WKUP5 enable
      bit_offset: 4
      bit_size: 1
    - name: WUPEN6
      description: Wakeup pin WKUP6 enable
      bit_offset: 5
      bit_size: 1
    - name: WUPEN7
      description: Wakeup pin WKUP7 enable
      bit_offset: 6
      bit_size: 1
    - name: WUPEN8
      description: Wakeup pin WKUP8 enable
      bit_offset: 7
      bit_size: 1
fieldset/WUCR2:
  description: PWR wakeup control register 2
  fields:
    - name: WUPP1
      description: "Wakeup pin WKUP1 polarity.\r This bit must be configured when WUPEN1 = 0."
      bit_offset: 0
      bit_size: 1
      enum: WUPP
    - name: WUPP2
      description: "Wakeup pin WKUP2 polarity\r This bit must be configured when WUPEN2 = 0."
      bit_offset: 1
      bit_size: 1
      enum: WUPP
    - name: WUPP3
      description: "Wakeup pin WKUP3 polarity\r This bit must be configured when WUPEN3 = 0."
      bit_offset: 2
      bit_size: 1
      enum: WUPP
    - name: WUPP4
      description: "Wakeup pin WKUP4 polarity\r This bit must be configured when WUPEN4 = 0."
      bit_offset: 3
      bit_size: 1
      enum: WUPP
    - name: WUPP5
      description: "Wakeup pin WKUP5 polarity\r This bit must be configured when WUPEN5 = 0."
      bit_offset: 4
      bit_size: 1
      enum: WUPP
    - name: WUPP6
      description: "Wakeup pin WKUP6 polarity\r This bit must be configured when WUPEN6 = 0."
      bit_offset: 5
      bit_size: 1
      enum: WUPP
    - name: WUPP7
      description: "Wakeup pin WKUP7 polarity\r This bit must be configured when WUPEN7 = 0."
      bit_offset: 6
      bit_size: 1
      enum: WUPP
    - name: WUPP8
      description: "Wakeup pin WKUP8 polarity\r This bit must be configured when WUPEN8 = 0."
      bit_offset: 7
      bit_size: 1
      enum: WUPP
fieldset/WUCR3:
  description: PWR wakeup control register 3
  fields:
    - name: WUSEL1
      description: "Wakeup pin WKUP1 selection\r This field must be configured when WUPEN1 = 0."
      bit_offset: 0
      bit_size: 2
      enum: WUSEL
    - name: WUSEL2
      description: "Wakeup pin WKUP2 selection\r This field must be configured when WUPEN2 = 0."
      bit_offset: 2
      bit_size: 2
      enum: WUSEL
    - name: WUSEL3
      description: "Wakeup pin WKUP3 selection\r This field must be configured when WUPEN3 = 0."
      bit_offset: 4
      bit_size: 2
      enum: WUSEL
    - name: WUSEL4
      description: "Wakeup pin WKUP4 selection\r This field must be configured when WUPEN4 = 0."
      bit_offset: 6
      bit_size: 2
      enum: WUSEL
    - name: WUSEL5
      description: "Wakeup pin WKUP5 selection\r This field must be configured when WUPEN5 = 0."
      bit_offset: 8
      bit_size: 2
      enum: WUSEL
    - name: WUSEL6
      description: "Wakeup pin WKUP6 selection\r This field must be configured when WUPEN6 = 0."
      bit_offset: 10
      bit_size: 2
      enum: WUSEL
    - name: WUSEL7
      description: "Wakeup pin WKUP7 selection\r This field must be configured when WUPEN7 = 0."
      bit_offset: 12
      bit_size: 2
      enum: WUSEL
    - name: WUSEL8
      description: "Wakeup pin WKUP8 selection\r This field must be configured when WUPEN8 = 0."
      bit_offset: 14
      bit_size: 2
      enum: WUSEL
fieldset/WUSCR:
  description: PWR wakeup status clear register
  fields:
    - name: CWUF1
      description: "Wakeup flag 1\r Writing 1 to this bit clears the WUF1 flag in WUSR."
      bit_offset: 0
      bit_size: 1
    - name: CWUF2
      description: "Wakeup flag 2\r Writing 1 to this bit clears the WUF2 flag in WUSR."
      bit_offset: 1
      bit_size: 1
    - name: CWUF3
      description: "Wakeup flag 3\r Writing 1 to this bit clears the WUF3 flag in WUSR."
      bit_offset: 2
      bit_size: 1
    - name: CWUF4
      description: "Wakeup flag 4\r Writing 1 to this bit clears the WUF4 flag in WUSR."
      bit_offset: 3
      bit_size: 1
    - name: CWUF5
      description: "Wakeup flag 5\r Writing 1 to this bit clears the WUF5 flag in WUSR."
      bit_offset: 4
      bit_size: 1
    - name: CWUF6
      description: "Wakeup flag 6\r Writing 1 to this bit clears the WUF6 flag in WUSR."
      bit_offset: 5
      bit_size: 1
    - name: CWUF7
      description: "Wakeup flag 7\r Writing 1 to this bit clears the WUF7 flag in WUSR."
      bit_offset: 6
      bit_size: 1
    - name: CWUF8
      description: "Wakeup flag 8\r Writing 1 to this bit clears the WUF8 flag in WUSR."
      bit_offset: 7
      bit_size: 1
fieldset/WUSR:
  description: PWR wakeup status register
  fields:
    - name: WUF1
      description: "Wakeup flag 1\r This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by writing 1 in the CWUF1 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN1 = 0."
      bit_offset: 0
      bit_size: 1
    - name: WUF2
      description: "Wakeup flag 2\r This bit is set when a wakeup event is detected on WKUP2 pin. This bit is cleared by writing 1 in the CWUF2 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN2 = 0."
      bit_offset: 1
      bit_size: 1
    - name: WUF3
      description: "Wakeup flag 3\r This bit is set when a wakeup event is detected on WKUP3 pin. This bit is cleared by writing 1 in the CWUF3 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN3 = 0."
      bit_offset: 2
      bit_size: 1
    - name: WUF4
      description: "Wakeup flag 4\r This bit is set when a wakeup event is detected on WKUP4 pin. This bit is cleared by writing 1 in the CWUF4 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN4 = 0."
      bit_offset: 3
      bit_size: 1
    - name: WUF5
      description: "Wakeup flag 5\r This bit is set when a wakeup event is detected on WKUP5 pin. This bit is cleared by writing 1 in the CWUF5 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN5 = 0."
      bit_offset: 4
      bit_size: 1
    - name: WUF6
      description: "Wakeup flag 6\r This bit is set when a wakeup event is detected on WKUP6 pin. This bit is cleared by writing 1 in the CWUF6 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN6 = 0.\r If WUSEL = 11, this bit is cleared by hardware when all internal wakeup source are cleared."
      bit_offset: 5
      bit_size: 1
    - name: WUF7
      description: "Wakeup flag 7\r This bit is set when a wakeup event is detected on WKUP7 pin. This bit is cleared by writing 1 in the CWUF7 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN7 = 0.\r If WUSEL = 11, this bit is cleared by hardware when all internal wakeup source are cleared."
      bit_offset: 6
      bit_size: 1
    - name: WUF8
      description: "Wakeup flag 8\r This bit is set when a wakeup event is detected on WKUP8 pin. This bit is cleared by writing 1 in the CWUF8 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN8 = 0.\r If WUSEL = 11, this bit is cleared by hardware when all internal wakeup source are cleared."
      bit_offset: 7
      bit_size: 1
enum/ACTVOS:
  bit_size: 2
  variants:
    - name: B_0x0
      description: Range 4 (lowest power)
      value: 0
    - name: B_0x1
      description: Range 3
      value: 1
    - name: B_0x2
      description: Range 2
      value: 2
    - name: B_0x3
      description: Range 1 (highest frequency)
      value: 3
enum/ACTVOSRDY:
  bit_size: 1
  variants:
    - name: B_0x0
      description: "VCORE is above or below the current voltage scaling provided by ACTVOS[1:0]."
      value: 0
    - name: B_0x1
      description: "VCORE is equal to the current voltage scaling provided by ACTVOS[1:0]"
      value: 1
enum/APCSEC:
  bit_size: 1
  variants:
    - name: B_0x0
      description: APCR can be read and written with secure or non-secure access.
      value: 0
    - name: B_0x1
      description: APCR can be read and written only with secure access.
      value: 1
enum/ASV:
  bit_size: 1
  variants:
    - name: B_0x0
      description: "VDDA not present: logical and electrical isolation is applied to ignore this supply."
      value: 0
    - name: B_0x1
      description: VDDA valid
      value: 1
enum/BOOSTRDY:
  bit_size: 1
  variants:
    - name: B_0x0
      description: Power booster not ready
      value: 0
    - name: B_0x1
      description: Power booster ready
      value: 1
enum/DBP:
  bit_size: 1
  variants:
    - name: B_0x0
      description: Write access to Backup domain disabled
      value: 0
    - name: B_0x1
      description: Write access to Backup domain enabled
      value: 1
enum/DCRAMPDS:
  bit_size: 1
  variants:
    - name: B_0x0
      description: DCACHE1 SRAM content retained in Stop modes
      value: 0
    - name: B_0x1
      description: DCACHE1 SRAM content lost in Stop modes
      value: 1
enum/DMADRAMPDS:
  bit_size: 1
  variants:
    - name: B_0x0
      description: DMA2D SRAM content retained in Stop modes
      value: 0
    - name: B_0x1
      description: DMA2D SRAM content lost in Stop modes
      value: 1
enum/FLASHFWU:
  bit_size: 1
  variants:
    - name: B_0x0
      description: Flash memory enters low-power mode in Stop 0 and Stop 1 modes (lower-power consumption).
      value: 0
    - name: B_0x1
      description: Flash memory remains in normal mode in Stop 0 and Stop 1 modes (faster wakeup time).
      value: 1
enum/ICRAMPDS:
  bit_size: 1
  variants:
    - name: B_0x0
      description: ICACHE SRAM content retained in Stop modes
      value: 0
    - name: B_0x1
      description: ICACHE SRAM content lost in Stop modes
      value: 1
enum/IOSV:
  bit_size: 1
  variants:
    - name: B_0x0
      description: "VDDIO2 not present: logical and electrical isolation is applied to ignore this supply."
      value: 0
    - name: B_0x1
      description: VDDIO2 valid
      value: 1
enum/LPMS:
  bit_size: 3
  variants:
    - name: B_0x0
      description: Stop 0 mode
      value: 0
    - name: B_0x1
      description: Stop 1 mode
      value: 1
    - name: B_0x2
      description: Stop 2 mode
      value: 2
    - name: B_0x3
      description: Stop 3 mode
      value: 3
enum/LPMSEC:
  bit_size: 1
  variants:
    - name: B_0x0
      description: "CR1, CR2 and CSSF in the SR can be read and written with secure or non-secure access."
      value: 0
    - name: B_0x1
      description: "CR1, CR2, and CSSF in the SR can be read and written only with secure access."
      value: 1
enum/NSPRIV:
  bit_size: 1
  variants:
    - name: B_0x0
      description: Read and write to PWR non-secure functions can be done by privileged or unprivileged access.
      value: 0
    - name: B_0x1
      description: Read and write to PWR non-secure functions can be done by privileged access only.
      value: 1
enum/PKARAMPDS:
  bit_size: 1
  variants:
    - name: B_0x0
      description: PKA SRAM content retained in Stop modes
      value: 0
    - name: B_0x1
      description: PKA SRAM content lost in Stop modes
      value: 1
enum/PRAMPDS:
  bit_size: 1
  variants:
    - name: B_0x0
      description: "FMAC, FDCAN and USB peripherals SRAM content retained in Stop modes"
      value: 0
    - name: B_0x1
      description: "FMAC, FDCAN and USB peripherals SRAM content lost in Stop modes"
      value: 1
enum/PVDE:
  bit_size: 1
  variants:
    - name: B_0x0
      description: Power voltage detector disabled
      value: 0
    - name: B_0x1
      description: Power voltage detector enabled
      value: 1
enum/PVDLS:
  bit_size: 3
  variants:
    - name: B_0x0
      description: VPVD0 around 2.0 V
      value: 0
    - name: B_0x1
      description: VPVD1 around 2.2 V
      value: 1
    - name: B_0x2
      description: VPVD2 around 2.4 V
      value: 2
    - name: B_0x3
      description: VPVD3 around 2.5 V
      value: 3
    - name: B_0x4
      description: VPVD4 around 2.6 V
      value: 4
    - name: B_0x5
      description: VPVD5 around 2.8 V
      value: 5
    - name: B_0x6
      description: VPVD6 around 2.9 V
      value: 6
    - name: B_0x7
      description: External input analog voltage PVD_IN (compared internally to VREFINT)
      value: 7
enum/PVDO:
  bit_size: 1
  variants:
    - name: B_0x0
      description: "VDD is equal or above the PVD threshold selected by PVDLS[2:0]."
      value: 0
    - name: B_0x1
      description: "VDD is below the PVD threshold selected by PVDLS[2:0]."
      value: 1
enum/REGS:
  bit_size: 1
  variants:
    - name: B_0x0
      description: LDO selected
      value: 0
    - name: B_0x1
      description: SMPS selected
      value: 1
enum/REGSEL:
  bit_size: 1
  variants:
    - name: B_0x0
      description: LDO selected
      value: 0
    - name: B_0x1
      description: SMPS selected
      value: 1
enum/RRSB:
  bit_size: 1
  variants:
    - name: B_0x0
      description: SRAM2 page1 content not retained in Stop 3 and Standby modes
      value: 0
    - name: B_0x1
      description: SRAM2 page1 content retained in Stop 3 and Standby modes
      value: 1
enum/SBF:
  bit_size: 1
  variants:
    - name: B_0x0
      description: The device did not enter Standby mode.
      value: 0
    - name: B_0x1
      description: The device entered Standby mode.
      value: 1
enum/SPRIV:
  bit_size: 1
  variants:
    - name: B_0x0
      description: Read and write to PWR secure functions can be done by privileged or unprivileged access.
      value: 0
    - name: B_0x1
      description: Read and write to PWR secure functions can be done by privileged access only.
      value: 1
enum/SRAMFWU:
  bit_size: 1
  variants:
    - name: B_0x0
      description: "SRAM4 enters low-power mode in Stop 0, 1 and 2 modes (source biasing for lower-power consumption)."
      value: 0
    - name: B_0x1
      description: "SRAM4 remains in normal mode in Stop 0, 1 and 2 modes (higher consumption but no SRAM4 wakeup time)."
      value: 1
enum/SRAMPD:
  bit_size: 1
  variants:
    - name: B_0x0
      description: SRAM1 powered on
      value: 0
    - name: B_0x1
      description: SRAM1 powered off
      value: 1
enum/SRAMPDS:
  bit_size: 1
  variants:
    - name: B_0x0
      description: SRAM3 page 1 content retained in Stop modes
      value: 0
    - name: B_0x1
      description: SRAM3 page 1 content lost in Stop modes
      value: 1
enum/SRDRUN:
  bit_size: 1
  variants:
    - name: B_0x0
      description: "SmartRun domain AHB3 and APB3 clocks disabled by default in Stop 0,1, 2 modes"
      value: 0
    - name: B_0x1
      description: "SmartRun domain AHB3 and APB3 clocks kept enabled in Stop 0,1, 2 modes"
      value: 1
enum/STOPF:
  bit_size: 1
  variants:
    - name: B_0x0
      description: The device did not enter any Stop mode.
      value: 0
    - name: B_0x1
      description: The device entered a Stop mode.
      value: 1
enum/TEMPH:
  bit_size: 1
  variants:
    - name: B_0x0
      description: Temperature < high threshold
      value: 0
    - name: B_0x1
      description: Temperature ≥ high threshold
      value: 1
enum/TEMPL:
  bit_size: 1
  variants:
    - name: B_0x0
      description: Temperature > low threshold
      value: 0
    - name: B_0x1
      description: Temperature ≤ low threshold
      value: 1
enum/UCPD_DBDIS:
  bit_size: 1
  variants:
    - name: B_0x0
      description: UCPD dead battery pull-down behavior enabled on UCPDx_CC1 and UCPDx_CC2 pins
      value: 0
    - name: B_0x1
      description: UCPD dead battery pull-down behavior disabled on UCPDx_CC1 and UCPDx_CC2 pins
      value: 1
enum/USV:
  bit_size: 1
  variants:
    - name: B_0x0
      description: "VDDUSB not present: logical and electrical isolation is applied to ignore this supply."
      value: 0
    - name: B_0x1
      description: VDDUSB valid
      value: 1
enum/VBATH:
  bit_size: 1
  variants:
    - name: B_0x0
      description: Backup domain voltage level < high threshold
      value: 0
    - name: B_0x1
      description: Backup domain voltage level ≥ high threshold
      value: 1
enum/VBE:
  bit_size: 1
  variants:
    - name: B_0x0
      description: VBAT battery charging disabled
      value: 0
    - name: B_0x1
      description: VBAT battery charging enabled
      value: 1
enum/VBRS:
  bit_size: 1
  variants:
    - name: B_0x0
      description: Charge VBAT through a 5 kΩ resistor
      value: 0
    - name: B_0x1
      description: Charge VBAT through a 1.5 kΩ resistor
      value: 1
enum/VBSEC:
  bit_size: 1
  variants:
    - name: B_0x0
      description: "BDCR1, BDCR2 and DBPR can be read and written with secure or non-secure access."
      value: 0
    - name: B_0x1
      description: "BDCR1, BDCR2 and DBPR can be read and written only with secure access."
      value: 1
enum/VDDARDY:
  bit_size: 1
  variants:
    - name: B_0x0
      description: VDDA is below the threshold of the VDDA voltage monitor 2 (around 1.8 V).
      value: 0
    - name: B_0x1
      description: VDDA is equal or above the threshold of the VDDA voltage monitor 2 (around 1.8 V).
      value: 1
enum/VDDIORDY:
  bit_size: 1
  variants:
    - name: B_0x0
      description: VDDIO2 is below the threshold of the VDDIO2 voltage monitor.
      value: 0
    - name: B_0x1
      description: VDDIO2 is equal or above the threshold of the VDDIO2 voltage monitor.
      value: 1
enum/VDDUSBRDY:
  bit_size: 1
  variants:
    - name: B_0x0
      description: VDDUSB is below the threshold of the VDDUSB voltage monitor.
      value: 0
    - name: B_0x1
      description: VDDUSB is equal or above the threshold of the VDDUSB voltage monitor.
      value: 1
enum/VDMSEC:
  bit_size: 1
  variants:
    - name: B_0x0
      description: SVMCR and CR3 can be read and written with secure or non-secure access.
      value: 0
    - name: B_0x1
      description: SVMCR and CR3 can be read and written only with secure access.
      value: 1
enum/VOS:
  bit_size: 2
  variants:
    - name: B_0x0
      description: Range 4 (lowest power)
      value: 0
    - name: B_0x1
      description: Range 3
      value: 1
    - name: B_0x2
      description: Range 2
      value: 2
    - name: B_0x3
      description: Range 1 (highest frequency). This value cannot be written when VCOREMEN = 1 in TAMP_OR register.
      value: 3
enum/VOSRDY:
  bit_size: 1
  variants:
    - name: B_0x0
      description: "Not ready, voltage level < VOS selected level"
      value: 0
    - name: B_0x1
      description: "Ready, voltage level ≥ VOS selected level"
      value: 1
enum/WUPP:
  bit_size: 1
  variants:
    - name: B_0x0
      description: Detection on high level (rising edge)
      value: 0
    - name: B_0x1
      description: Detection on low level (falling edge)
      value: 1
enum/WUPSEC:
  bit_size: 1
  variants:
    - name: B_0x0
      description: "Bits related to the WKUP3 pin in WUCR1, WUCR2, WUCR3 and WUSCR can be read and written with secure or non-secure access."
      value: 0
    - name: B_0x1
      description: "Bits related to the WKUP3 pin in WUCR1, WUCR2, WUCR3 and WUSCR can be read and written only with secure access."
      value: 1
enum/WUSEL:
  bit_size: 2
  variants:
    - name: B_0x0
      description: WKUP7_0
      value: 0
    - name: B_0x1
      description: WKUP7_1
      value: 1
    - name: B_0x2
      description: WKUP7_2
      value: 2
    - name: B_0x3
      description: WKUP7_3
      value: 3