Add RCC register for STM32F4 and STM32L4
Register block based in STM32F427ZI and STM32L4R9. Use bool for reset registers. Define clock mapping for RNG peripherals. There are no 1 <-> 1 mapping of RNG peripheral to clock in the Cubedb sources. The mapping will pre-select the clock source for RNG for now.
This commit is contained in:
Ulf Lilleengen
parent
9cfdc5a647
commit
18a99a3a3b
1970
data/registers/rcc_f4.yaml
Normal file
1970
data/registers/rcc_f4.yaml
Normal file
File diff suppressed because it is too large
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@ -675,34 +675,42 @@ fieldset/CIER:
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description: LSI ready interrupt flag
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bit_offset: 0
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bit_size: 1
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enum: HSIRDYIE
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- name: LSERDYIE
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description: LSE ready interrupt flag
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bit_offset: 1
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bit_size: 1
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enum: HSIRDYIE
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- name: HSI16RDYIE
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description: HSI16 ready interrupt flag
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bit_offset: 2
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bit_size: 1
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enum: HSIRDYIE
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- name: HSERDYIE
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description: HSE ready interrupt flag
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bit_offset: 3
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bit_size: 1
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enum: HSIRDYIE
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- name: PLLRDYIE
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description: PLL ready interrupt flag
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bit_offset: 4
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bit_size: 1
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enum: HSIRDYIE
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- name: MSIRDYIE
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description: MSI ready interrupt flag
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bit_offset: 5
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bit_size: 1
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enum: HSIRDYIE
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- name: HSI48RDYIE
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description: HSI48 ready interrupt flag
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bit_offset: 6
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bit_size: 1
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enum: HSIRDYIE
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- name: CSSLSE
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description: LSE CSS interrupt flag
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bit_offset: 7
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bit_size: 1
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enum: CSSLSE
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fieldset/CIFR:
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description: Clock interrupt flag register
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fields:
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@ -758,10 +766,12 @@ fieldset/CR:
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description: 16 MHz high-speed internal clock enable
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bit_offset: 0
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bit_size: 1
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enum: PLLON
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- name: HSI16KERON
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description: High-speed internal clock enable bit for some IP kernels
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bit_offset: 1
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bit_size: 1
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enum: PLLON
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- name: HSI16RDYF
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description: Internal high-speed clock ready flag
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bit_offset: 2
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@ -784,6 +794,7 @@ fieldset/CR:
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description: MSI clock enable bit
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bit_offset: 8
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bit_size: 1
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enum: PLLON
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- name: MSIRDY
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description: MSI clock ready flag
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bit_offset: 9
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@ -793,6 +804,7 @@ fieldset/CR:
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description: HSE clock enable bit
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bit_offset: 16
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bit_size: 1
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enum: PLLON
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- name: HSERDY
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description: HSE clock ready flag
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bit_offset: 17
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@ -807,6 +819,7 @@ fieldset/CR:
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description: Clock security system on HSE enable bit
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bit_offset: 19
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bit_size: 1
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enum: PLLON
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- name: RTCPRE
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description: TC/LCD prescaler
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bit_offset: 20
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@ -816,6 +829,7 @@ fieldset/CR:
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description: PLL enable bit
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bit_offset: 24
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bit_size: 1
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enum: PLLON
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- name: PLLRDY
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description: PLL clock ready flag
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bit_offset: 25
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@ -847,6 +861,7 @@ fieldset/CSR:
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description: Internal low-speed oscillator enable
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bit_offset: 0
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bit_size: 1
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enum: CSSLSEON
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- name: LSIRDY
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description: Internal low-speed oscillator ready bit
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bit_offset: 1
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@ -856,6 +871,7 @@ fieldset/CSR:
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description: External low-speed oscillator enable bit
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bit_offset: 8
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bit_size: 1
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enum: CSSLSEON
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- name: LSERDY
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description: External low-speed oscillator ready bit
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bit_offset: 9
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@ -875,6 +891,7 @@ fieldset/CSR:
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description: CSSLSEON
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bit_offset: 13
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bit_size: 1
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enum: CSSLSEON
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- name: CSSLSED
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description: CSS on LSE failure detection flag
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bit_offset: 14
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@ -992,32 +1009,26 @@ fieldset/IOPRSTR:
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description: I/O port A reset
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bit_offset: 0
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bit_size: 1
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enum: IOPHRST
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- name: IOPBRST
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description: I/O port B reset
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bit_offset: 1
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bit_size: 1
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enum: IOPHRST
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- name: IOPCRST
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description: I/O port A reset
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bit_offset: 2
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bit_size: 1
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enum: IOPHRST
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- name: IOPDRST
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description: I/O port D reset
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bit_offset: 3
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bit_size: 1
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enum: IOPHRST
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- name: IOPERST
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description: I/O port E reset
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bit_offset: 4
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bit_size: 1
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enum: IOPHRST
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- name: IOPHRST
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description: I/O port H reset
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bit_offset: 7
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bit_size: 1
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enum: IOPHRST
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fieldset/IOPSMEN:
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description: GPIO clock enable in sleep mode register
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fields:
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@ -1066,6 +1077,15 @@ enum/CSSHSEF:
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- name: Clock
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description: Clock security interrupt caused by HSE clock failure
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value: 1
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enum/CSSLSE:
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bit_size: 1
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variants:
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- name: Disabled
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description: LSE CSS interrupt disabled
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value: 0
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- name: Enabled
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description: LSE CSS interrupt enabled
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value: 1
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enum/CSSLSED:
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bit_size: 1
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variants:
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@ -1084,6 +1104,15 @@ enum/CSSLSEF:
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- name: Failure
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description: Failure detected on LSE clock failure
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value: 1
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enum/CSSLSEON:
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bit_size: 1
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variants:
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- name: "Off"
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description: Oscillator OFF
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value: 0
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- name: "On"
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description: Oscillator ON
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value: 1
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enum/DBGRSTW:
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bit_size: 1
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variants:
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@ -1165,6 +1194,15 @@ enum/HSIDIVFR:
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- name: Div4
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description: 16 MHz HSI clock divided by 4
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value: 1
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enum/HSIRDYIE:
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bit_size: 1
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variants:
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- name: Disabled
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description: Ready interrupt disabled
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value: 0
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- name: Enabled
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description: Ready interrupt enabled
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value: 1
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enum/ICSEL:
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bit_size: 2
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variants:
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@ -1177,12 +1215,6 @@ enum/ICSEL:
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- name: HSI16
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description: HSI16 clock selected as peripheral clock
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value: 2
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enum/IOPHRST:
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bit_size: 1
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variants:
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- name: Reset
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description: Reset I/O port
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value: 1
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enum/LPTIMRSTW:
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bit_size: 1
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variants:
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@ -1375,6 +1407,15 @@ enum/PLLMUL:
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- name: Mul48
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description: PLL clock entry x 48
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value: 8
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enum/PLLON:
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bit_size: 1
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variants:
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- name: Disabled
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description: Clock disabled
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value: 0
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- name: Enabled
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description: Clock enabled
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value: 1
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enum/PLLRDYR:
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bit_size: 1
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variants:
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@ -6,7 +6,7 @@ board=$1
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peri=$2
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mkdir -p regs/$peri
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cargo build --release --manifest-path ../../../svd2rust/Cargo.toml
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cargo build --release --manifest-path ../../svd2rust/Cargo.toml
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transform="transform.yaml"
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@ -28,7 +28,7 @@ for f in `ls $query`; do
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f=${f#"stm32"}
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f=${f%".svd"}
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echo -n processing $f ...
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RUST_LOG=info ../../../svd2rust/target/release/svd4rust extract-peripheral --svd sources/svd/stm32$f.svd --transform $transform --peripheral $peri > regs/$peri/$f.yaml 2> regs/$peri/$f.yaml.out
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RUST_LOG=info ../../svd2rust/target/release/svd4rust extract-peripheral --svd sources/svd/stm32$f.svd --transform $transform --peripheral $peri > regs/$peri/$f.yaml 2> regs/$peri/$f.yaml.out
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if [ $? -ne 0 ]; then
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mv regs/$peri/$f.yaml.out regs/$peri/$f.err
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rm regs/$peri/$f.yaml
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20
parse.py
20
parse.py
@ -242,6 +242,8 @@ perimap = [
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('STM32L0.*:SYS:.*', 'syscfg_l0/SYSCFG'),
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('STM32H7.*:SYS:.*', 'syscfg_h7/SYSCFG'),
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('STM32L0.*:RCC:.*', 'rcc_l0/RCC'),
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('STM32L4.*:RCC:.*', 'rcc_l4/RCC'),
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('STM32F4.*:RCC:.*', 'rcc_f4/RCC'),
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('.*:STM32L0_dbgmcu_v1_0', 'dbg_l0/DBG'),
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('.*:STM32L0_crs_v1_0', 'crs_l0/CRS'),
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('.*SDMMC:sdmmc2_v1_0', 'sdmmc_v2/SDMMC'),
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@ -252,6 +254,13 @@ perimap = [
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('.*TIM\d.*:gptimer.*', 'timer_v1/TIM_GP16'),
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]
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rng_clock_map = [
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('STM32L0.*:RNG:.*', 'AHB'),
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('STM32L4.*:RNG:.*', 'AHB2'),
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('STM32F4.*:RNG:.*', 'AHB2'),
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('STM32H7.*:RNG:.*', 'AHB2'),
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]
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def match_peri(peri):
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for r, block in perimap:
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@ -266,6 +275,11 @@ def find_af(gpio_af, peri_name, pin_name, signal_name):
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return af[gpio_af][pin_name][peri_name + '_' + signal_name]
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return None
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def match_rng_clock(rcc):
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for r, clock in rng_clock_map:
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if re.match(r, rcc):
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return clock
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return None
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def parse_headers():
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os.makedirs('sources/headers_parsed', exist_ok=True)
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@ -458,6 +472,11 @@ def parse_chips():
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if len(chip['pins'][pname]) > 0:
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p['pins'] = chip['pins'][pname]
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# RNG Clock definitions are not easily determined, so lookup in mapping
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if block is not None and block.startswith("rng_"):
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if (clock := match_rng_clock(chip_name+':'+pname+':'+pkind)) != None:
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p['clock'] = clock
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peris[pname] = p
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@ -599,6 +618,7 @@ def parse_clocks():
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peripherals = peripherals.split(",")
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for p in peripherals:
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chip_clocks[p] = name
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clocks[ff] = chip_clocks
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@ -41,5 +41,8 @@ transforms:
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from: '[HL](IFCR|ISR)'
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to: $1
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- DeleteEnums:
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from: '.*[EN]'
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from: '.*EN'
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bit_size: 1
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- DeleteEnums:
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from: '.*RST'
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bit_size: 1
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