Add RCC register for STM32F4 and STM32L4

Register block based in STM32F427ZI and STM32L4R9.

Use bool for reset registers.

Define clock mapping for RNG peripherals. There are no 1 <-> 1 mapping
of RNG peripheral to clock in the Cubedb sources. The mapping will
pre-select the clock source for RNG for now.

data/registers/rcc_l0.yaml

@@ -675,34 +675,42 @@ fieldset/CIER:
       description: LSI ready interrupt flag
       bit_offset: 0
       bit_size: 1
+      enum: HSIRDYIE
     - name: LSERDYIE
       description: LSE ready interrupt flag
       bit_offset: 1
       bit_size: 1
+      enum: HSIRDYIE
     - name: HSI16RDYIE
       description: HSI16 ready interrupt flag
       bit_offset: 2
       bit_size: 1
+      enum: HSIRDYIE
     - name: HSERDYIE
       description: HSE ready interrupt flag
       bit_offset: 3
       bit_size: 1
+      enum: HSIRDYIE
     - name: PLLRDYIE
       description: PLL ready interrupt flag
       bit_offset: 4
       bit_size: 1
+      enum: HSIRDYIE
     - name: MSIRDYIE
       description: MSI ready interrupt flag
       bit_offset: 5
       bit_size: 1
+      enum: HSIRDYIE
     - name: HSI48RDYIE
       description: HSI48 ready interrupt flag
       bit_offset: 6
       bit_size: 1
+      enum: HSIRDYIE
     - name: CSSLSE
       description: LSE CSS interrupt flag
       bit_offset: 7
       bit_size: 1
+      enum: CSSLSE
 fieldset/CIFR:
   description: Clock interrupt flag register
   fields:
@@ -758,10 +766,12 @@ fieldset/CR:
       description: 16 MHz high-speed internal clock enable
       bit_offset: 0
       bit_size: 1
+      enum: PLLON
     - name: HSI16KERON
       description: High-speed internal clock enable bit for some IP kernels
       bit_offset: 1
       bit_size: 1
+      enum: PLLON
     - name: HSI16RDYF
       description: Internal high-speed clock ready flag
       bit_offset: 2
@@ -784,6 +794,7 @@ fieldset/CR:
       description: MSI clock enable bit
       bit_offset: 8
       bit_size: 1
+      enum: PLLON
     - name: MSIRDY
       description: MSI clock ready flag
       bit_offset: 9
@@ -793,6 +804,7 @@ fieldset/CR:
       description: HSE clock enable bit
       bit_offset: 16
       bit_size: 1
+      enum: PLLON
     - name: HSERDY
       description: HSE clock ready flag
       bit_offset: 17
@@ -807,6 +819,7 @@ fieldset/CR:
       description: Clock security system on HSE enable bit
       bit_offset: 19
       bit_size: 1
+      enum: PLLON
     - name: RTCPRE
       description: TC/LCD prescaler
       bit_offset: 20
@@ -816,6 +829,7 @@ fieldset/CR:
       description: PLL enable bit
       bit_offset: 24
       bit_size: 1
+      enum: PLLON
     - name: PLLRDY
       description: PLL clock ready flag
       bit_offset: 25
@@ -847,6 +861,7 @@ fieldset/CSR:
       description: Internal low-speed oscillator enable
       bit_offset: 0
       bit_size: 1
+      enum: CSSLSEON
     - name: LSIRDY
       description: Internal low-speed oscillator ready bit
       bit_offset: 1
@@ -856,6 +871,7 @@ fieldset/CSR:
       description: External low-speed oscillator enable bit
       bit_offset: 8
       bit_size: 1
+      enum: CSSLSEON
     - name: LSERDY
       description: External low-speed oscillator ready bit
       bit_offset: 9
@@ -875,6 +891,7 @@ fieldset/CSR:
       description: CSSLSEON
       bit_offset: 13
       bit_size: 1
+      enum: CSSLSEON
     - name: CSSLSED
       description: CSS on LSE failure detection flag
       bit_offset: 14
@@ -992,32 +1009,26 @@ fieldset/IOPRSTR:
       description: I/O port A reset
       bit_offset: 0
       bit_size: 1
-      enum: IOPHRST
     - name: IOPBRST
       description: I/O port B reset
       bit_offset: 1
       bit_size: 1
-      enum: IOPHRST
     - name: IOPCRST
       description: I/O port A reset
       bit_offset: 2
       bit_size: 1
-      enum: IOPHRST
     - name: IOPDRST
       description: I/O port D reset
       bit_offset: 3
       bit_size: 1
-      enum: IOPHRST
     - name: IOPERST
       description: I/O port E reset
       bit_offset: 4
       bit_size: 1
-      enum: IOPHRST
     - name: IOPHRST
       description: I/O port H reset
       bit_offset: 7
       bit_size: 1
-      enum: IOPHRST
 fieldset/IOPSMEN:
   description: GPIO clock enable in sleep mode register
   fields:
@@ -1066,6 +1077,15 @@ enum/CSSHSEF:
     - name: Clock
       description: Clock security interrupt caused by HSE clock failure
       value: 1
+enum/CSSLSE:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: LSE CSS interrupt disabled
+      value: 0
+    - name: Enabled
+      description: LSE CSS interrupt enabled
+      value: 1
 enum/CSSLSED:
   bit_size: 1
   variants:
@@ -1084,6 +1104,15 @@ enum/CSSLSEF:
     - name: Failure
       description: Failure detected on LSE clock failure
       value: 1
+enum/CSSLSEON:
+  bit_size: 1
+  variants:
+    - name: "Off"
+      description: Oscillator OFF
+      value: 0
+    - name: "On"
+      description: Oscillator ON
+      value: 1
 enum/DBGRSTW:
   bit_size: 1
   variants:
@@ -1165,6 +1194,15 @@ enum/HSIDIVFR:
     - name: Div4
       description: 16 MHz HSI clock divided by 4
       value: 1
+enum/HSIRDYIE:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: Ready interrupt disabled
+      value: 0
+    - name: Enabled
+      description: Ready interrupt enabled
+      value: 1
 enum/ICSEL:
   bit_size: 2
   variants:
@@ -1177,12 +1215,6 @@ enum/ICSEL:
     - name: HSI16
       description: HSI16 clock selected as peripheral clock
       value: 2
-enum/IOPHRST:
-  bit_size: 1
-  variants:
-    - name: Reset
-      description: Reset I/O port
-      value: 1
 enum/LPTIMRSTW:
   bit_size: 1
   variants:
@@ -1375,6 +1407,15 @@ enum/PLLMUL:
     - name: Mul48
       description: PLL clock entry x 48
       value: 8
+enum/PLLON:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: Clock disabled
+      value: 0
+    - name: Enabled
+      description: Clock enabled
+      value: 1
 enum/PLLRDYR:
   bit_size: 1
   variants:

extract.sh

@@ -6,7 +6,7 @@ board=$1
 peri=$2
 mkdir -p regs/$peri
 
-cargo build --release --manifest-path ../../../svd2rust/Cargo.toml 
+cargo build --release --manifest-path ../../svd2rust/Cargo.toml 
 
 transform="transform.yaml"
 
@@ -28,7 +28,7 @@ for f in `ls $query`; do
     f=${f#"stm32"}
     f=${f%".svd"}
     echo -n processing $f ...
-    RUST_LOG=info ../../../svd2rust/target/release/svd4rust extract-peripheral --svd sources/svd/stm32$f.svd --transform $transform --peripheral $peri > regs/$peri/$f.yaml 2> regs/$peri/$f.yaml.out
+    RUST_LOG=info ../../svd2rust/target/release/svd4rust extract-peripheral --svd sources/svd/stm32$f.svd --transform $transform --peripheral $peri > regs/$peri/$f.yaml 2> regs/$peri/$f.yaml.out
     if [ $? -ne 0 ]; then 
         mv regs/$peri/$f.yaml.out regs/$peri/$f.err
         rm regs/$peri/$f.yaml

parse.py

@@ -242,6 +242,8 @@ perimap = [
     ('STM32L0.*:SYS:.*', 'syscfg_l0/SYSCFG'),
     ('STM32H7.*:SYS:.*', 'syscfg_h7/SYSCFG'),
     ('STM32L0.*:RCC:.*', 'rcc_l0/RCC'),
+    ('STM32L4.*:RCC:.*', 'rcc_l4/RCC'),
+    ('STM32F4.*:RCC:.*', 'rcc_f4/RCC'),
     ('.*:STM32L0_dbgmcu_v1_0', 'dbg_l0/DBG'),
     ('.*:STM32L0_crs_v1_0', 'crs_l0/CRS'),
     ('.*SDMMC:sdmmc2_v1_0', 'sdmmc_v2/SDMMC'),
@@ -252,6 +254,13 @@ perimap = [
     ('.*TIM\d.*:gptimer.*', 'timer_v1/TIM_GP16'),
 ]
 
+rng_clock_map = [
+    ('STM32L0.*:RNG:.*', 'AHB'),
+    ('STM32L4.*:RNG:.*', 'AHB2'),
+    ('STM32F4.*:RNG:.*', 'AHB2'),
+    ('STM32H7.*:RNG:.*', 'AHB2'),
+]
+
 
 def match_peri(peri):
     for r, block in perimap:
@@ -266,6 +275,11 @@ def find_af(gpio_af, peri_name, pin_name, signal_name):
                  return af[gpio_af][pin_name][peri_name + '_' + signal_name]
      return None
               
+def match_rng_clock(rcc):
+    for r, clock in rng_clock_map:
+        if re.match(r, rcc):
+            return clock
+    return None
 
 def parse_headers():
     os.makedirs('sources/headers_parsed', exist_ok=True)
@@ -458,6 +472,11 @@ def parse_chips():
                 if len(chip['pins'][pname]) > 0:
                     p['pins'] = chip['pins'][pname]
 
+            # RNG Clock definitions are not easily determined, so lookup in mapping
+            if block is not None and block.startswith("rng_"):
+                if (clock := match_rng_clock(chip_name+':'+pname+':'+pkind)) != None:
+                    p['clock'] = clock
+
             peris[pname] = p
 
 
@@ -599,6 +618,7 @@ def parse_clocks():
                 peripherals = peripherals.split(",")
                 for p in peripherals:
                     chip_clocks[p] = name
+
         clocks[ff] = chip_clocks
 
 

transform-RCC.yaml

@@ -41,5 +41,8 @@ transforms:
       from: '[HL](IFCR|ISR)'
       to: $1
   - DeleteEnums:
-      from: '.*[EN]'
+      from: '.*EN'
+      bit_size: 1
+  - DeleteEnums:
+      from: '.*RST'
       bit_size: 1