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Generate ethernet peripherals for f2 and f4

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These are eth v1b, according to stm32-rs it should have the same register
changes as v1c, so I just copied it over.
This commit is contained in:
David Lenfesty 2022-04-26 10:09:28 -06:00
parent 05bf8c23c1
commit 121e5bc92b
2 changed files with 2221 additions and 0 deletions
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2220
data/registers/eth_v1b.yaml Normal file
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stm32data/__main__.py
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@ -232,6 +232,7 @@ perimap = [
('STM32WB.*:FLASH:.*', ('flash', 'wb55', 'FLASH')), ('STM32WB.*:FLASH:.*', ('flash', 'wb55', 'FLASH')),
('STM32G0.*:FLASH:.*', ('flash', 'g0', 'FLASH')), ('STM32G0.*:FLASH:.*', ('flash', 'g0', 'FLASH')),
('STM32F107.*:ETH:.*', ('eth', 'v1a', 'ETH')), ('STM32F107.*:ETH:.*', ('eth', 'v1a', 'ETH')),
('STM32F[24].*:ETH:.*', ('eth', 'v1b', 'ETH')),
('STM32F7.*:ETH:ETH:ethermac110_v2_0', ('eth', 'v1c', 'ETH')), ('STM32F7.*:ETH:ETH:ethermac110_v2_0', ('eth', 'v1c', 'ETH')),
('.*ETH:ethermac110_v3_0', ('eth', 'v2', 'ETH')), ('.*ETH:ethermac110_v3_0', ('eth', 'v2', 'ETH')),