rcc: make GPIOxEN/IOPxEN consistent.

data/registers/rcc_g0.yaml

@@ -32,10 +32,10 @@ block/RCC:
       byte_offset: 32
       access: Write
       fieldset: CICR
-    - name: IOPRSTR
+    - name: GPIORSTR
       description: GPIO reset register
       byte_offset: 36
-      fieldset: IOPRSTR
+      fieldset: GPIORSTR
     - name: AHBRSTR
       description: AHB peripheral reset register
       byte_offset: 40
@@ -48,10 +48,10 @@ block/RCC:
       description: APB peripheral reset register 2
       byte_offset: 48
       fieldset: APBRSTR2
-    - name: IOPENR
+    - name: GPIOENR
       description: GPIO clock enable register
       byte_offset: 52
-      fieldset: IOPENR
+      fieldset: GPIOENR
     - name: AHBENR
       description: AHB peripheral clock enable register
       byte_offset: 56
@@ -64,10 +64,10 @@ block/RCC:
       description: APB peripheral clock enable register 2
       byte_offset: 64
       fieldset: APBENR2
-    - name: IOPSMENR
+    - name: GPIOSMENR
       description: GPIO in Sleep mode clock enable register
       byte_offset: 68
-      fieldset: IOPSMENR
+      fieldset: GPIOSMENR
     - name: AHBSMENR
       description: AHB peripheral clock enable in Sleep mode register
       byte_offset: 72
@@ -846,7 +846,7 @@ fieldset/ICSCR:
       description: HSI16 clock trimming
       bit_offset: 8
       bit_size: 7
-fieldset/IOPENR:
+fieldset/GPIOENR:
   description: GPIO clock enable register
   fields:
     - name: GPIOAEN
@@ -869,7 +869,7 @@ fieldset/IOPENR:
       description: I/O port F clock enable
       bit_offset: 5
       bit_size: 1
-fieldset/IOPRSTR:
+fieldset/GPIORSTR:
   description: GPIO reset register
   fields:
     - name: GPIOARST
@@ -892,26 +892,26 @@ fieldset/IOPRSTR:
       description: I/O port F reset
       bit_offset: 5
       bit_size: 1
-fieldset/IOPSMENR:
+fieldset/GPIOSMENR:
   description: GPIO in Sleep mode clock enable register
   fields:
-    - name: IOPASMEN
+    - name: GPIOASMEN
       description: I/O port A clock enable during Sleep mode
       bit_offset: 0
       bit_size: 1
-    - name: IOPBSMEN
+    - name: GPIOBSMEN
       description: I/O port B clock enable during Sleep mode
       bit_offset: 1
       bit_size: 1
-    - name: IOPCSMEN
+    - name: GPIOCSMEN
       description: I/O port C clock enable during Sleep mode
       bit_offset: 2
       bit_size: 1
-    - name: IOPDSMEN
+    - name: GPIODSMEN
       description: I/O port D clock enable during Sleep mode
       bit_offset: 3
       bit_size: 1
-    - name: IOPFSMEN
+    - name: GPIOFSMEN
       description: I/O port F clock enable during Sleep mode
       bit_offset: 5
       bit_size: 1

data/registers/rcc_l0.yaml

@@ -29,10 +29,10 @@ block/RCC:
       byte_offset: 24
       access: Read
       fieldset: CICR
-    - name: IOPRSTR
+    - name: GPIORSTR
       description: GPIO reset register
       byte_offset: 28
-      fieldset: IOPRSTR
+      fieldset: GPIORSTR
     - name: AHBRSTR
       description: AHB peripheral reset register
       byte_offset: 32
@@ -45,10 +45,10 @@ block/RCC:
       description: APB1 peripheral reset register
       byte_offset: 40
       fieldset: APB1RSTR
-    - name: IOPENR
+    - name: GPIOENR
       description: GPIO clock enable register
       byte_offset: 44
-      fieldset: IOPENR
+      fieldset: GPIOENR
     - name: AHBENR
       description: AHB peripheral clock enable register
       byte_offset: 48
@@ -61,10 +61,10 @@ block/RCC:
       description: APB1 peripheral clock enable register
       byte_offset: 56
       fieldset: APB1ENR
-    - name: IOPSMEN
+    - name: GPIOSMEN
       description: GPIO clock enable in sleep mode register
       byte_offset: 60
-      fieldset: IOPSMEN
+      fieldset: GPIOSMEN
     - name: AHBSMENR
       description: AHB peripheral clock enable in sleep mode register
       byte_offset: 64
@@ -904,7 +904,7 @@ fieldset/ICSCR:
       description: MSI clock trimming
       bit_offset: 24
       bit_size: 8
-fieldset/IOPENR:
+fieldset/GPIOENR:
   description: GPIO clock enable register
   fields:
     - name: GPIOAEN
@@ -931,7 +931,7 @@ fieldset/IOPENR:
       description: I/O port H clock enable
       bit_offset: 7
       bit_size: 1
-fieldset/IOPRSTR:
+fieldset/GPIORSTR:
   description: GPIO reset register
   fields:
     - name: GPIOARST
@@ -958,30 +958,30 @@ fieldset/IOPRSTR:
       description: I/O port H reset
       bit_offset: 7
       bit_size: 1
-fieldset/IOPSMEN:
+fieldset/GPIOSMEN:
   description: GPIO clock enable in sleep mode register
   fields:
-    - name: IOPASMEN
+    - name: GPIOASMEN
       description: Port A clock enable during Sleep mode
       bit_offset: 0
       bit_size: 1
-    - name: IOPBSMEN
+    - name: GPIOBSMEN
       description: Port B clock enable during Sleep mode
       bit_offset: 1
       bit_size: 1
-    - name: IOPCSMEN
+    - name: GPIOCSMEN
       description: Port C clock enable during Sleep mode
       bit_offset: 2
       bit_size: 1
-    - name: IOPDSMEN
+    - name: GPIODSMEN
       description: Port D clock enable during Sleep mode
       bit_offset: 3
       bit_size: 1
-    - name: IOPESMEN
+    - name: GPIOESMEN
       description: Port E clock enable during Sleep mode
       bit_offset: 4
       bit_size: 1
-    - name: IOPHSMEN
+    - name: GPIOHSMEN
       description: Port H clock enable during Sleep mode
       bit_offset: 7
       bit_size: 1

stm32data/__main__.py

@@ -1118,8 +1118,8 @@ def parse_rcc_regs():
 
         for (key, body) in y.items():
             # Some chip families have a separate bus for GPIO so it's not attached to the AHB/APB
-            # bus but an IOPORT bus. Use the IOP as the clock for these chips.
-            if m := re.match('^fieldset/((A[PH]B\d?)|IOP)[LH]?ENR\d?$', key):
+            # bus but an GPIO bus. Use the GPIO as the clock for these chips.
+            if m := re.match('^fieldset/((A[PH]B\d?)|GPIO)[LH]?ENR\d?$', key):
                 reg = removeprefix(key, 'fieldset/')
                 clock = m.group(1)
                 for field in body['fields']: