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Fix F4 UART parsing

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chemicstry 2022-03-17 16:33:34 +02:00
parent 67a00a393e
commit 0f80d10a1f
1 changed files with 1 additions and 0 deletions
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stm32data/__main__.py
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@ -92,6 +92,7 @@ perimap = [
('.*:USART:sci3_v1_2', ('usart', 'v2', 'USART')), ('.*:USART:sci3_v1_2', ('usart', 'v2', 'USART')),
('.*:USART:sci3_v2_0', ('usart', 'v2', 'USART')), ('.*:USART:sci3_v2_0', ('usart', 'v2', 'USART')),
('.*:USART:sci3_v2_1', ('usart', 'v2', 'USART')), ('.*:USART:sci3_v2_1', ('usart', 'v2', 'USART')),
('.*:UART:sci2_v1_2_F4', ('usart', 'v1', 'USART')),
('.*:UART:sci2_v2_1', ('usart', 'v2', 'USART')), ('.*:UART:sci2_v2_1', ('usart', 'v2', 'USART')),
('.*:UART:sci2_v3_0', ('usart', 'v2', 'USART')), ('.*:UART:sci2_v3_0', ('usart', 'v2', 'USART')),
('.*:UART:sci2_v3_1', ('usart', 'v2', 'USART')), ('.*:UART:sci2_v3_1', ('usart', 'v2', 'USART')),