From 0f80d10a1f387ff63ba24b6ad7cdcc9e5ec5b9b6 Mon Sep 17 00:00:00 2001 From: chemicstry Date: Thu, 17 Mar 2022 16:33:34 +0200 Subject: [PATCH] Fix F4 UART parsing --- stm32data/__main__.py | 1 + 1 file changed, 1 insertion(+) diff --git a/stm32data/__main__.py b/stm32data/__main__.py index bedb622..191079d 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -92,6 +92,7 @@ perimap = [ ('.*:USART:sci3_v1_2', ('usart', 'v2', 'USART')), ('.*:USART:sci3_v2_0', ('usart', 'v2', 'USART')), ('.*:USART:sci3_v2_1', ('usart', 'v2', 'USART')), + ('.*:UART:sci2_v1_2_F4', ('usart', 'v1', 'USART')), ('.*:UART:sci2_v2_1', ('usart', 'v2', 'USART')), ('.*:UART:sci2_v3_0', ('usart', 'v2', 'USART')), ('.*:UART:sci2_v3_1', ('usart', 'v2', 'USART')),