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rcc: l0, l1, l4: add missing enums.

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Dario Nieuwenhuis 2022-01-04 23:56:52 +01:00
parent 7061d52abd
commit 0f04776eaa
3 changed files with 514 additions and 404 deletions
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495
data/registers/rcc_l0.yaml
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241
data/registers/rcc_l1.yaml
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@ -568,42 +568,52 @@ fieldset/CFGR:
description: System clock switch description: System clock switch
bit_offset: 0 bit_offset: 0
bit_size: 2 bit_size: 2
enum: SW
- name: SWS - name: SWS
description: System clock switch status description: System clock switch status
bit_offset: 2 bit_offset: 2
bit_size: 2 bit_size: 2
enum: SW
- name: HPRE - name: HPRE
description: AHB prescaler description: AHB prescaler
bit_offset: 4 bit_offset: 4
bit_size: 4 bit_size: 4
enum: HPRE
- name: PPRE1 - name: PPRE1
description: APB low-speed prescaler (APB1) description: APB low-speed prescaler (APB1)
bit_offset: 8 bit_offset: 8
bit_size: 3 bit_size: 3
enum: PPRE
- name: PPRE2 - name: PPRE2
description: APB high-speed prescaler (APB2) description: APB high-speed prescaler (APB2)
bit_offset: 11 bit_offset: 11
bit_size: 3 bit_size: 3
enum: PPRE
- name: PLLSRC - name: PLLSRC
description: PLL entry clock source description: PLL entry clock source
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
enum: PLLSRC
- name: PLLMUL - name: PLLMUL
description: PLL multiplication factor description: PLL multiplication factor
bit_offset: 18 bit_offset: 18
bit_size: 4 bit_size: 4
enum: PLLMUL
- name: PLLDIV - name: PLLDIV
description: PLL output division description: PLL output division
bit_offset: 22 bit_offset: 22
bit_size: 2 bit_size: 2
enum: PLLDIV
- name: MCOSEL - name: MCOSEL
description: Microcontroller clock output selection description: Microcontroller clock output selection
bit_offset: 24 bit_offset: 24
bit_size: 3 bit_size: 3
enum: MCOSEL
- name: MCOPRE - name: MCOPRE
description: Microcontroller clock output prescaler description: Microcontroller clock output prescaler
bit_offset: 28 bit_offset: 28
bit_size: 3 bit_size: 3
enum: MCOPRE
fieldset/CIR: fieldset/CIR:
description: Clock interrupt register description: Clock interrupt register
fields: fields:
@ -730,16 +740,13 @@ fieldset/CR:
description: Clock security system enable description: Clock security system enable
bit_offset: 28 bit_offset: 28
bit_size: 1 bit_size: 1
- name: RTCPRE0 - name: RTCPRE
description: RTCPRE0 description: RTC/LCD prescaler
bit_offset: 29 bit_offset: 29
bit_size: 1 bit_size: 2
- name: RTCPRE1 enum: RTCPRE
description: TC/LCD prescaler
bit_offset: 30
bit_size: 1
fieldset/CSR: fieldset/CSR:
description: Control/status register description: Control and status register
fields: fields:
- name: LSION - name: LSION
description: Internal low-speed oscillator enable description: Internal low-speed oscillator enable
@ -765,6 +772,7 @@ fieldset/CSR:
description: RTC and LCD clock source selection description: RTC and LCD clock source selection
bit_offset: 16 bit_offset: 16
bit_size: 2 bit_size: 2
enum: RTCSEL
- name: RTCEN - name: RTCEN
description: RTC clock enable description: RTC clock enable
bit_offset: 22 bit_offset: 22
@ -816,6 +824,7 @@ fieldset/ICSCR:
description: MSI clock ranges description: MSI clock ranges
bit_offset: 13 bit_offset: 13
bit_size: 3 bit_size: 3
enum: MSIRANGE
- name: MSICAL - name: MSICAL
description: MSI clock calibration description: MSI clock calibration
bit_offset: 16 bit_offset: 16
@ -824,3 +833,219 @@ fieldset/ICSCR:
description: MSI clock trimming description: MSI clock trimming
bit_offset: 24 bit_offset: 24
bit_size: 8 bit_size: 8
enum/HPRE:
bit_size: 4
variants:
- name: Div1
description: system clock not divided
value: 0
- name: Div2
description: system clock divided by 2
value: 8
- name: Div4
description: system clock divided by 4
value: 9
- name: Div8
description: system clock divided by 8
value: 10
- name: Div16
description: system clock divided by 16
value: 11
- name: Div64
description: system clock divided by 64
value: 12
- name: Div128
description: system clock divided by 128
value: 13
- name: Div256
description: system clock divided by 256
value: 14
- name: Div512
description: system clock divided by 512
value: 15
enum/MCOPRE:
bit_size: 3
variants:
- name: Div1
description: No division
value: 0
- name: Div2
description: Division by 2
value: 1
- name: Div4
description: Division by 4
value: 2
- name: Div8
description: Division by 8
value: 3
- name: Div16
description: Division by 16
value: 4
enum/MCOSEL:
bit_size: 4
variants:
- name: NoClock
description: No clock
value: 0
- name: SYSCLK
description: SYSCLK clock selected
value: 1
- name: HSI
description: HSI oscillator clock selected
value: 2
- name: MSI
description: MSI oscillator clock selected
value: 3
- name: HSE
description: HSE oscillator clock selected
value: 4
- name: PLL
description: PLL clock selected
value: 5
- name: LSI
description: LSI oscillator clock selected
value: 6
- name: LSE
description: LSE oscillator clock selected
value: 7
enum/MSIRANGE:
bit_size: 3
variants:
- name: Range0
description: range 0 around 65.536 kHz
value: 0
- name: Range1
description: range 1 around 131.072 kHz
value: 1
- name: Range2
description: range 2 around 262.144 kHz
value: 2
- name: Range3
description: range 3 around 524.288 kHz
value: 3
- name: Range4
description: range 4 around 1.048 MHz
value: 4
- name: Range5
description: range 5 around 2.097 MHz (reset value)
value: 5
- name: Range6
description: range 6 around 4.194 MHz
value: 6
- name: Range7
description: not allowed
value: 7
enum/PLLDIV:
bit_size: 2
variants:
- name: Div2
description: PLLVCO / 2
value: 1
- name: Div3
description: PLLVCO / 3
value: 2
- name: Div4
description: PLLVCO / 4
value: 3
enum/PLLMUL:
bit_size: 4
variants:
- name: Mul3
description: PLL clock entry x 3
value: 0
- name: Mul4
description: PLL clock entry x 4
value: 1
- name: Mul6
description: PLL clock entry x 6
value: 2
- name: Mul8
description: PLL clock entry x 8
value: 3
- name: Mul12
description: PLL clock entry x 12
value: 4
- name: Mul16
description: PLL clock entry x 16
value: 5
- name: Mul24
description: PLL clock entry x 24
value: 6
- name: Mul32
description: PLL clock entry x 32
value: 7
- name: Mul48
description: PLL clock entry x 48
value: 8
enum/PLLSRC:
bit_size: 1
variants:
- name: HSI
description: HSI selected as PLL input clock
value: 0
- name: HSE
description: HSE selected as PLL input clock
value: 1
enum/PPRE:
bit_size: 3
variants:
- name: Div1
description: HCLK not divided
value: 0
- name: Div2
description: HCLK divided by 2
value: 4
- name: Div4
description: HCLK divided by 4
value: 5
- name: Div8
description: HCLK divided by 8
value: 6
- name: Div16
description: HCLK divided by 16
value: 7
enum/RTCPRE:
bit_size: 2
variants:
- name: Div2
description: HSE divided by 2
value: 0
- name: Div4
description: HSE divided by 4
value: 1
- name: Div8
description: HSE divided by 8
value: 2
- name: Div16
description: HSE divided by 16
value: 3
enum/RTCSEL:
bit_size: 2
variants:
- name: NoClock
description: No clock
value: 0
- name: LSE
description: LSE oscillator clock used as RTC clock
value: 1
- name: LSI
description: LSI oscillator clock used as RTC clock
value: 2
- name: HSE
description: "HSE oscillator clock divided by a programmable prescaler (selection through the RTCPRE[1:0] bits in the RCC clock control register (RCC_CR)) used as the RTC clock"
value: 3
enum/SW:
bit_size: 2
variants:
- name: MSI
description: MSI oscillator used as system clock
value: 0
- name: HSI
description: HSI oscillator used as system clock
value: 1
- name: HSE
description: HSE oscillator used as system clock
value: 2
- name: PLL
description: PLL used as system clock
value: 3

182
data/registers/rcc_l4.yaml
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@ -1101,6 +1101,7 @@ fieldset/BDCR:
description: SE oscillator drive capability description: SE oscillator drive capability
bit_offset: 3 bit_offset: 3
bit_size: 2 bit_size: 2
enum: LSEDRV
- name: LSECSSON - name: LSECSSON
description: LSECSSON description: LSECSSON
bit_offset: 5 bit_offset: 5
@ -1113,6 +1114,7 @@ fieldset/BDCR:
description: RTC clock source selection description: RTC clock source selection
bit_offset: 8 bit_offset: 8
bit_size: 2 bit_size: 2
enum: RTCSEL
- name: RTCEN - name: RTCEN
description: RTC clock enable description: RTC clock enable
bit_offset: 15 bit_offset: 15
@ -1246,34 +1248,42 @@ fieldset/CFGR:
description: System clock switch description: System clock switch
bit_offset: 0 bit_offset: 0
bit_size: 2 bit_size: 2
enum: SW
- name: SWS - name: SWS
description: System clock switch status description: System clock switch status
bit_offset: 2 bit_offset: 2
bit_size: 2 bit_size: 2
enum: SW
- name: HPRE - name: HPRE
description: AHB prescaler description: AHB prescaler
bit_offset: 4 bit_offset: 4
bit_size: 4 bit_size: 4
enum: HPRE
- name: PPRE1 - name: PPRE1
description: PB low-speed prescaler (APB1) description: APB low-speed prescaler (APB1)
bit_offset: 8 bit_offset: 8
bit_size: 3 bit_size: 3
enum: PPRE
- name: PPRE2 - name: PPRE2
description: APB high-speed prescaler (APB2) description: APB high-speed prescaler (APB2)
bit_offset: 11 bit_offset: 11
bit_size: 3 bit_size: 3
enum: PPRE
- name: STOPWUCK - name: STOPWUCK
description: Wakeup from Stop and CSS backup clock selection description: Wakeup from Stop and CSS backup clock selection
bit_offset: 15 bit_offset: 15
bit_size: 1 bit_size: 1
enum: STOPWUCK
- name: MCOSEL - name: MCOSEL
description: Microcontroller clock output description: Microcontroller clock output selection
bit_offset: 24 bit_offset: 24
bit_size: 3 bit_size: 4
enum: MCOSEL
- name: MCOPRE - name: MCOPRE
description: Microcontroller clock output prescaler description: Microcontroller clock output prescaler
bit_offset: 28 bit_offset: 28
bit_size: 3 bit_size: 3
enum: MCOPRE
fieldset/CICR: fieldset/CICR:
description: Clock interrupt clear register description: Clock interrupt clear register
fields: fields:
@ -1587,6 +1597,7 @@ fieldset/PLLCFGR:
description: "Main PLL, PLLSAI1 and PLLSAI2 entry clock source" description: "Main PLL, PLLSAI1 and PLLSAI2 entry clock source"
bit_offset: 0 bit_offset: 0
bit_size: 2 bit_size: 2
enum: PLLSRC
- name: PLLM - name: PLLM
description: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock description: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock
bit_offset: 4 bit_offset: 4
@ -1701,6 +1712,99 @@ fieldset/PLLSAI2CFGR:
description: PLLSAI2 division factor for PLLSAI2CLK description: PLLSAI2 division factor for PLLSAI2CLK
bit_offset: 27 bit_offset: 27
bit_size: 5 bit_size: 5
enum/HPRE:
bit_size: 4
variants:
- name: Div1
description: system clock not divided
value: 0
- name: Div2
description: system clock divided by 2
value: 8
- name: Div4
description: system clock divided by 4
value: 9
- name: Div8
description: system clock divided by 8
value: 10
- name: Div16
description: system clock divided by 16
value: 11
- name: Div64
description: system clock divided by 64
value: 12
- name: Div128
description: system clock divided by 128
value: 13
- name: Div256
description: system clock divided by 256
value: 14
- name: Div512
description: system clock divided by 512
value: 15
enum/LSEDRV:
bit_size: 2
variants:
- name: Low
description: Lowest drive
value: 0
- name: MediumLow
description: Medium low drive
value: 1
- name: MediumHigh
description: Medium high drive
value: 2
- name: High
description: Highest drive
value: 3
enum/MCOPRE:
bit_size: 3
variants:
- name: Div1
description: No division
value: 0
- name: Div2
description: Division by 2
value: 1
- name: Div4
description: Division by 4
value: 2
- name: Div8
description: Division by 8
value: 3
- name: Div16
description: Division by 16
value: 4
enum/MCOSEL:
bit_size: 4
variants:
- name: NoClock
description: No clock
value: 0
- name: SYSCLK
description: SYSCLK clock selected
value: 1
- name: HSI16
description: HSI oscillator clock selected
value: 2
- name: MSI
description: MSI oscillator clock selected
value: 3
- name: HSE
description: HSE oscillator clock selected
value: 4
- name: PLL
description: PLL clock selected
value: 5
- name: LSI
description: LSI oscillator clock selected
value: 6
- name: LSE
description: LSE oscillator clock selected
value: 7
- name: HSI48
description: HSI48 oscillator clock selected
value: 8
enum/MSIRANGE: enum/MSIRANGE:
bit_size: 4 bit_size: 4
variants: variants:
@ -1740,3 +1844,75 @@ enum/MSIRANGE:
- name: Range48M - name: Range48M
description: range 11 around 48 MHz description: range 11 around 48 MHz
value: 11 value: 11
enum/PLLSRC:
bit_size: 2
variants:
- name: None
description: No clock sent to PLL
value: 0
- name: MSI
description: MSI selected as PLL input clock
value: 1
- name: HSI16
description: HSI selected as PLL input clock
value: 2
- name: HSE
description: HSE selected as PLL input clock
value: 3
enum/PPRE:
bit_size: 3
variants:
- name: Div1
description: HCLK not divided
value: 0
- name: Div2
description: HCLK divided by 2
value: 4
- name: Div4
description: HCLK divided by 4
value: 5
- name: Div8
description: HCLK divided by 8
value: 6
- name: Div16
description: HCLK divided by 16
value: 7
enum/RTCSEL:
bit_size: 2
variants:
- name: NoClock
description: No clock
value: 0
- name: LSE
description: LSE oscillator clock used as RTC clock
value: 1
- name: LSI
description: LSI oscillator clock used as RTC clock
value: 2
- name: HSE
description: HSE oscillator clock divided by 32 used as the RTC clock
value: 3
enum/STOPWUCK:
bit_size: 1
variants:
- name: MSI
description: Internal 64 KHz to 4 MHz (MSI) oscillator selected as wake-up from Stop clock
value: 0
- name: HSI16
description: Internal 16 MHz (HSI) oscillator selected as wake-up from Stop clock (or HSI16/4 if HSI16DIVEN=1)
value: 1
enum/SW:
bit_size: 2
variants:
- name: MSI
description: MSI oscillator used as system clock
value: 0
- name: HSI16
description: HSI oscillator used as system clock
value: 1
- name: HSE
description: HSE oscillator used as system clock
value: 2
- name: PLL
description: PLL used as system clock
value: 3