diff --git a/data/registers/rcc_l0.yaml b/data/registers/rcc_l0.yaml index 0faa3cc..a8fe1b4 100644 --- a/data/registers/rcc_l0.yaml +++ b/data/registers/rcc_l0.yaml @@ -93,27 +93,27 @@ fieldset/AHBENR: description: AHB peripheral clock enable register fields: - name: DMA1EN - description: DMA clock enable bit + description: DMA clock enable bit_offset: 0 bit_size: 1 - name: MIFEN - description: NVM interface clock enable bit + description: NVM interface clock enable bit_offset: 8 bit_size: 1 - name: CRCEN - description: CRC clock enable bit + description: CRC clock enable bit_offset: 12 bit_size: 1 - name: CRYPEN - description: Crypto clock enable bit + description: Crypto clock enable bit_offset: 24 bit_size: 1 - name: TOUCHEN - description: Touch Sensing clock enable bit + description: Touch Sensing clock enable bit_offset: 16 bit_size: 1 - name: RNGEN - description: Random Number Generator clock enable bit + description: Random Number Generator clock enable bit_offset: 20 bit_size: 1 fieldset/AHBRSTR: @@ -123,136 +123,130 @@ fieldset/AHBRSTR: description: DMA reset bit_offset: 0 bit_size: 1 - enum_write: CRYPRSTW - name: MIFRST description: Memory interface reset bit_offset: 8 bit_size: 1 - enum_write: CRYPRSTW - name: CRCRST description: Test integration module reset bit_offset: 12 bit_size: 1 - enum_write: CRYPRSTW - name: CRYPRST description: Crypto module reset bit_offset: 24 bit_size: 1 - enum_write: CRYPRSTW - name: TOUCHRST description: Touch Sensing reset bit_offset: 16 bit_size: 1 - enum_write: CRYPRSTW - name: RNGRST description: Random Number Generator module reset bit_offset: 20 bit_size: 1 - enum_write: CRYPRSTW fieldset/AHBSMENR: description: AHB peripheral clock enable in sleep mode register fields: - name: DMA1SMEN - description: DMA clock enable during sleep mode bit + description: DMA clock enable during sleep mode bit_offset: 0 bit_size: 1 - name: MIFSMEN - description: NVM interface clock enable during sleep mode bit + description: NVM interface clock enable during sleep mode bit_offset: 8 bit_size: 1 - name: SRAMSMEN - description: SRAM interface clock enable during sleep mode bit + description: SRAM interface clock enable during sleep mode bit_offset: 9 bit_size: 1 - name: CRCSMEN - description: CRC clock enable during sleep mode bit + description: CRC clock enable during sleep mode bit_offset: 12 bit_size: 1 - name: CRYPSMEN - description: Crypto clock enable during sleep mode bit + description: Crypto clock enable during sleep mode bit_offset: 24 bit_size: 1 - name: TOUCHSMEN - description: Touch Sensing clock enable during sleep mode bit + description: Touch Sensing clock enable during sleep mode bit_offset: 16 bit_size: 1 - name: RNGSMEN - description: Random Number Generator clock enable during sleep mode bit + description: Random Number Generator clock enable during sleep mode bit_offset: 20 bit_size: 1 fieldset/APB1ENR: description: APB1 peripheral clock enable register fields: - name: TIM2EN - description: Timer2 clock enable bit + description: Timer2 clock enable bit_offset: 0 bit_size: 1 - name: TIM6EN - description: Timer 6 clock enable bit + description: Timer 6 clock enable bit_offset: 4 bit_size: 1 - name: TIM7EN - description: Timer 7 clock enable bit + description: Timer 7 clock enable bit_offset: 5 bit_size: 1 - name: WWDGEN - description: Window watchdog clock enable bit + description: Window watchdog clock enable bit_offset: 11 bit_size: 1 - name: SPI2EN - description: SPI2 clock enable bit + description: SPI2 clock enable bit_offset: 14 bit_size: 1 - name: USART2EN - description: UART2 clock enable bit + description: UART2 clock enable bit_offset: 17 bit_size: 1 - name: LPUART1EN - description: LPUART1 clock enable bit + description: LPUART1 clock enable bit_offset: 18 bit_size: 1 - name: USART4EN - description: USART4 clock enable bit + description: USART4 clock enable bit_offset: 19 bit_size: 1 - name: USART5EN - description: USART5 clock enable bit + description: USART5 clock enable bit_offset: 20 bit_size: 1 - name: I2C1EN - description: I2C1 clock enable bit + description: I2C1 clock enable bit_offset: 21 bit_size: 1 - name: I2C2EN - description: I2C2 clock enable bit + description: I2C2 clock enable bit_offset: 22 bit_size: 1 - name: PWREN - description: Power interface clock enable bit + description: Power interface clock enable bit_offset: 28 bit_size: 1 - name: I2C3EN - description: I2C3 clock enable bit + description: I2C3 clock enable bit_offset: 30 bit_size: 1 - name: LPTIM1EN - description: Low power timer clock enable bit + description: Low power timer clock enable bit_offset: 31 bit_size: 1 - name: TIM3EN - description: Timer 3 clock enbale bit + description: Timer 3 clock enbale bit_offset: 1 bit_size: 1 - name: USBEN - description: USB clock enable bit + description: USB clock enable bit_offset: 23 bit_size: 1 - name: CRSEN - description: Clock recovery system clock enable bit + description: Clock recovery system clock enable bit_offset: 27 bit_size: 1 - name: DACEN - description: DAC interface clock enable bit + description: DAC interface clock enable bit_offset: 29 bit_size: 1 fieldset/APB1RSTR: @@ -262,204 +256,186 @@ fieldset/APB1RSTR: description: Timer 2 reset bit_offset: 0 bit_size: 1 - enum_write: LPTIMRSTW - name: TIM3RST description: Timer 3 reset bit_offset: 1 bit_size: 1 - enum_write: LPTIMRSTW - name: TIM6RST description: Timer 6 reset bit_offset: 4 bit_size: 1 - enum_write: LPTIMRSTW - name: TIM7RST description: Timer 7 reset bit_offset: 5 bit_size: 1 - enum_write: LPTIMRSTW - name: WWDGRST description: Window watchdog reset bit_offset: 11 bit_size: 1 - enum_write: LPTIMRSTW - name: SPI2RST description: SPI2 reset bit_offset: 14 bit_size: 1 - enum_write: LPTIMRSTW - name: USART2RST description: USART2 reset bit_offset: 17 bit_size: 1 - enum_write: LPTIMRSTW - name: LPUART1RST description: LPUART1 reset bit_offset: 18 bit_size: 1 - enum_write: LPTIMRSTW - name: USART4RST description: USART4 reset bit_offset: 19 bit_size: 1 - enum_write: LPTIMRSTW - name: USART5RST description: USART5 reset bit_offset: 20 bit_size: 1 - enum_write: LPTIMRSTW - name: I2C1RST description: I2C1 reset bit_offset: 21 bit_size: 1 - enum_write: LPTIMRSTW - name: I2C2RST description: I2C2 reset bit_offset: 22 bit_size: 1 - enum_write: LPTIMRSTW - name: PWRRST description: Power interface reset bit_offset: 28 bit_size: 1 - enum_write: LPTIMRSTW - name: LPTIM1RST description: Low power timer reset bit_offset: 31 bit_size: 1 - enum_write: LPTIMRSTW - name: I2C3RST description: I2C3 reset bit_offset: 30 bit_size: 1 - enum_write: LPTIMRSTW - name: USBRST description: USB reset bit_offset: 23 bit_size: 1 - enum_write: LPTIMRSTW - name: CRSRST description: Clock recovery system reset bit_offset: 27 bit_size: 1 - enum_write: LPTIMRSTW - name: DACRST description: DAC interface reset bit_offset: 29 bit_size: 1 - enum_write: LPTIMRSTW fieldset/APB1SMENR: description: APB1 peripheral clock enable in sleep mode register fields: - name: TIM2SMEN - description: Timer2 clock enable during sleep mode bit + description: Timer2 clock enable during sleep mode bit_offset: 0 bit_size: 1 - name: TIM3SMEN - description: Timer 3 clock enable during sleep mode bit + description: Timer 3 clock enable during sleep mode bit_offset: 1 bit_size: 1 - name: TIM6SMEN - description: Timer 6 clock enable during sleep mode bit + description: Timer 6 clock enable during sleep mode bit_offset: 4 bit_size: 1 - name: TIM7SMEN - description: Timer 7 clock enable during sleep mode bit + description: Timer 7 clock enable during sleep mode bit_offset: 5 bit_size: 1 - name: WWDGSMEN - description: Window watchdog clock enable during sleep mode bit + description: Window watchdog clock enable during sleep mode bit_offset: 11 bit_size: 1 - name: SPI2SMEN - description: SPI2 clock enable during sleep mode bit + description: SPI2 clock enable during sleep mode bit_offset: 14 bit_size: 1 - name: USART2SMEN - description: UART2 clock enable during sleep mode bit + description: UART2 clock enable during sleep mode bit_offset: 17 bit_size: 1 - name: LPUART1SMEN - description: LPUART1 clock enable during sleep mode bit + description: LPUART1 clock enable during sleep mode bit_offset: 18 bit_size: 1 - name: USART4SMEN - description: USART4 clock enabe during sleep mode bit + description: USART4 clock enabe during sleep mode bit_offset: 19 bit_size: 1 - name: USART5SMEN - description: USART5 clock enable during sleep mode bit + description: USART5 clock enable during sleep mode bit_offset: 20 bit_size: 1 - name: I2C1SMEN - description: I2C1 clock enable during sleep mode bit + description: I2C1 clock enable during sleep mode bit_offset: 21 bit_size: 1 - name: I2C2SMEN - description: I2C2 clock enable during sleep mode bit + description: I2C2 clock enable during sleep mode bit_offset: 22 bit_size: 1 - name: CRSSMEN - description: Clock recovery system clock enable during sleep mode bit + description: Clock recovery system clock enable during sleep mode bit_offset: 27 bit_size: 1 - name: PWRSMEN - description: Power interface clock enable during sleep mode bit + description: Power interface clock enable during sleep mode bit_offset: 28 bit_size: 1 - name: I2C3SMEN - description: I2C3 clock enable during sleep mode bit + description: I2C3 clock enable during sleep mode bit_offset: 30 bit_size: 1 - name: LPTIM1SMEN - description: Low power timer clock enable during sleep mode bit + description: Low power timer clock enable during sleep mode bit_offset: 31 bit_size: 1 - name: USBSMEN - description: USB clock enable during sleep mode bit + description: USB clock enable during sleep mode bit_offset: 23 bit_size: 1 - name: DACSMEN - description: DAC interface clock enable during sleep mode bit + description: DAC interface clock enable during sleep mode bit_offset: 29 bit_size: 1 fieldset/APB2ENR: description: APB2 peripheral clock enable register fields: - name: SYSCFGEN - description: System configuration controller clock enable bit + description: System configuration controller clock enable bit_offset: 0 bit_size: 1 - name: TIM21EN - description: TIM21 timer clock enable bit + description: TIM21 timer clock enable bit_offset: 2 bit_size: 1 - name: TIM22EN - description: TIM22 timer clock enable bit + description: TIM22 timer clock enable bit_offset: 5 bit_size: 1 - name: FWEN - description: Firewall clock enable bit + description: Firewall clock enable bit_offset: 7 bit_size: 1 - name: ADCEN - description: ADC clock enable bit + description: ADC clock enable bit_offset: 9 bit_size: 1 - name: SPI1EN - description: SPI1 clock enable bit + description: SPI1 clock enable bit_offset: 12 bit_size: 1 - name: USART1EN - description: USART1 clock enable bit + description: USART1 clock enable bit_offset: 14 bit_size: 1 - name: DBGEN - description: DBG clock enable bit + description: DBG clock enable bit_offset: 22 bit_size: 1 - name: MIFIEN - description: MiFaRe Firewall clock enable bit + description: MiFaRe Firewall clock enable bit_offset: 7 bit_size: 1 fieldset/APB2RSTR: @@ -469,103 +445,96 @@ fieldset/APB2RSTR: description: System configuration controller reset bit_offset: 0 bit_size: 1 - enum_write: DBGRSTW - name: TIM21RST description: TIM21 timer reset bit_offset: 2 bit_size: 1 - enum_write: DBGRSTW - name: TIM22RST description: TIM22 timer reset bit_offset: 5 bit_size: 1 - enum_write: DBGRSTW - name: ADCRST description: ADC interface reset bit_offset: 9 bit_size: 1 - enum_write: DBGRSTW - name: SPI1RST description: SPI 1 reset bit_offset: 12 bit_size: 1 - enum_write: DBGRSTW - name: USART1RST description: USART1 reset bit_offset: 14 bit_size: 1 - enum_write: DBGRSTW - name: DBGRST description: DBG reset bit_offset: 22 bit_size: 1 - enum_write: DBGRSTW fieldset/APB2SMENR: description: APB2 peripheral clock enable in sleep mode register fields: - name: SYSCFGSMEN - description: System configuration controller clock enable during sleep mode bit + description: System configuration controller clock enable during sleep mode bit_offset: 0 bit_size: 1 - name: TIM21SMEN - description: TIM21 timer clock enable during sleep mode bit + description: TIM21 timer clock enable during sleep mode bit_offset: 2 bit_size: 1 - name: TIM22SMEN - description: TIM22 timer clock enable during sleep mode bit + description: TIM22 timer clock enable during sleep mode bit_offset: 5 bit_size: 1 - name: ADCSMEN - description: ADC clock enable during sleep mode bit + description: ADC clock enable during sleep mode bit_offset: 9 bit_size: 1 - name: SPI1SMEN - description: SPI1 clock enable during sleep mode bit + description: SPI1 clock enable during sleep mode bit_offset: 12 bit_size: 1 - name: USART1SMEN - description: USART1 clock enable during sleep mode bit + description: USART1 clock enable during sleep mode bit_offset: 14 bit_size: 1 - name: DBGSMEN - description: DBG clock enable during sleep mode bit + description: DBG clock enable during sleep mode bit_offset: 22 bit_size: 1 fieldset/CCIPR: description: Clock configuration register fields: - name: USART1SEL - description: USART1 clock source selection bits + description: USART1 clock source selection bit_offset: 0 bit_size: 2 - enum: LPUARTSEL + enum: UARTSEL - name: USART2SEL - description: USART2 clock source selection bits + description: USART2 clock source selection bit_offset: 2 bit_size: 2 - enum: LPUARTSEL + enum: UARTSEL - name: LPUART1SEL - description: LPUART1 clock source selection bits + description: LPUART1 clock source selection bit_offset: 10 bit_size: 2 - enum: LPUARTSEL + enum: UARTSEL - name: I2C1SEL - description: I2C1 clock source selection bits + description: I2C1 clock source selection bit_offset: 12 bit_size: 2 enum: ICSEL - name: I2C3SEL - description: I2C3 clock source selection bits + description: I2C3 clock source selection bit_offset: 16 bit_size: 2 enum: ICSEL - name: LPTIM1SEL - description: Low Power Timer clock source selection bits + description: Low Power Timer clock source selection bit_offset: 18 bit_size: 2 enum: LPTIMSEL - name: HSI48MSEL - description: 48 MHz HSI48 clock source selection bit + description: 48 MHz HSI48 clock source selection bit_offset: 26 bit_size: 1 fieldset/CFGR: @@ -580,7 +549,7 @@ fieldset/CFGR: description: System clock switch status bit_offset: 2 bit_size: 2 - enum: SWS + enum: SW - name: HPRE description: AHB prescaler bit_offset: 4 @@ -633,47 +602,38 @@ fieldset/CICR: description: LSI ready Interrupt clear bit_offset: 0 bit_size: 1 - enum_write: CSSHSECW - name: LSERDYC description: LSE ready Interrupt clear bit_offset: 1 bit_size: 1 - enum_write: CSSHSECW - name: HSI16RDYC description: HSI16 ready Interrupt clear bit_offset: 2 bit_size: 1 - enum_write: CSSHSECW - name: HSERDYC description: HSE ready Interrupt clear bit_offset: 3 bit_size: 1 - enum_write: CSSHSECW - name: PLLRDYC description: PLL ready Interrupt clear bit_offset: 4 bit_size: 1 - enum_write: CSSHSECW - name: MSIRDYC description: MSI ready Interrupt clear bit_offset: 5 bit_size: 1 - enum_write: CSSHSECW - name: CSSLSEC description: LSE Clock Security System Interrupt clear bit_offset: 7 bit_size: 1 - enum_write: CSSHSECW - name: CSSHSEC description: Clock Security System Interrupt clear bit_offset: 8 bit_size: 1 - enum_write: CSSHSECW - name: HSI48RDYC description: HSI48 ready Interrupt clear bit_offset: 6 bit_size: 1 - enum_write: CSSHSECW fieldset/CIER: description: Clock interrupt enable register fields: @@ -681,42 +641,34 @@ fieldset/CIER: description: LSI ready interrupt flag bit_offset: 0 bit_size: 1 - enum: MSIRDYIE - name: LSERDYIE description: LSE ready interrupt flag bit_offset: 1 bit_size: 1 - enum: MSIRDYIE - name: HSI16RDYIE description: HSI16 ready interrupt flag bit_offset: 2 bit_size: 1 - enum: MSIRDYIE - name: HSERDYIE description: HSE ready interrupt flag bit_offset: 3 bit_size: 1 - enum: MSIRDYIE - name: PLLRDYIE description: PLL ready interrupt flag bit_offset: 4 bit_size: 1 - enum: MSIRDYIE - name: MSIRDYIE description: MSI ready interrupt flag bit_offset: 5 bit_size: 1 - enum: MSIRDYIE - name: CSSLSE description: LSE CSS interrupt flag bit_offset: 7 bit_size: 1 - enum: CSSLSE - name: HSI48RDYIE description: HSI48 ready interrupt flag bit_offset: 6 bit_size: 1 - enum: HSIRDYIE fieldset/CIFR: description: Clock interrupt flag register fields: @@ -724,47 +676,38 @@ fieldset/CIFR: description: LSI ready interrupt flag bit_offset: 0 bit_size: 1 - enum_read: MSIRDYFR - name: LSERDYF description: LSE ready interrupt flag bit_offset: 1 bit_size: 1 - enum_read: MSIRDYFR - name: HSI16RDYF description: HSI16 ready interrupt flag bit_offset: 2 bit_size: 1 - enum_read: MSIRDYFR - name: HSERDYF description: HSE ready interrupt flag bit_offset: 3 bit_size: 1 - enum_read: MSIRDYFR - name: PLLRDYF description: PLL ready interrupt flag bit_offset: 4 bit_size: 1 - enum_read: MSIRDYFR - name: MSIRDYF description: MSI ready interrupt flag bit_offset: 5 bit_size: 1 - enum_read: MSIRDYFR - name: CSSLSEF description: LSE Clock Security System Interrupt flag bit_offset: 7 bit_size: 1 - enum: CSSLSEF - name: CSSHSEF description: Clock Security System Interrupt flag bit_offset: 8 bit_size: 1 - enum: CSSHSEF - name: HSI48RDYF description: HSI48 ready interrupt flag bit_offset: 6 bit_size: 1 - enum_read: HSI48RDYFR fieldset/CR: description: Clock control register fields: @@ -780,7 +723,6 @@ fieldset/CR: description: Internal high-speed clock ready flag bit_offset: 2 bit_size: 1 - enum_read: HSIRDYFR - name: HSI16DIVEN description: HSI16DIVEN bit_offset: 3 @@ -789,36 +731,32 @@ fieldset/CR: description: HSI16DIVF bit_offset: 4 bit_size: 1 - enum_read: HSIDIVFR - name: HSI16OUTEN description: 16 MHz high-speed internal clock output enable bit_offset: 5 bit_size: 1 - name: MSION - description: MSI clock enable bit + description: MSI clock enable bit_offset: 8 bit_size: 1 - name: MSIRDY description: MSI clock ready flag bit_offset: 9 bit_size: 1 - enum_read: HSERDYR - name: HSEON - description: HSE clock enable bit + description: HSE clock enable bit_offset: 16 bit_size: 1 - name: HSERDY description: HSE clock ready flag bit_offset: 17 bit_size: 1 - enum_read: HSERDYR - name: HSEBYP - description: HSE clock bypass bit + description: HSE clock bypass bit_offset: 18 bit_size: 1 - enum: HSEBYP - name: CSSHSEON - description: Clock security system on HSE enable bit + description: Clock security system on HSE enable bit_offset: 19 bit_size: 1 - name: RTCPRE @@ -827,19 +765,18 @@ fieldset/CR: bit_size: 2 enum: RTCPRE - name: PLLON - description: PLL enable bit + description: PLL enable bit_offset: 24 bit_size: 1 - name: PLLRDY description: PLL clock ready flag bit_offset: 25 bit_size: 1 - enum_read: PLLRDYR fieldset/CRRCR: description: Clock recovery RC register fields: - name: HSI48ON - description: 48MHz HSI clock enable bit + description: 48MHz HSI clock enable bit_offset: 0 bit_size: 1 - name: HSI48RDY @@ -862,24 +799,21 @@ fieldset/CSR: bit_offset: 0 bit_size: 1 - name: LSIRDY - description: Internal low-speed oscillator ready bit + description: Internal low-speed oscillator ready bit_offset: 1 bit_size: 1 - enum: LSERDY - name: LSEON - description: External low-speed oscillator enable bit + description: External low-speed oscillator enable bit_offset: 8 bit_size: 1 - name: LSERDY - description: External low-speed oscillator ready bit + description: External low-speed oscillator ready bit_offset: 9 bit_size: 1 - enum: LSERDY - name: LSEBYP - description: External low-speed oscillator bypass bit + description: External low-speed oscillator bypass bit_offset: 10 bit_size: 1 - enum: LSEBYP - name: LSEDRV description: LSEDRV bit_offset: 11 @@ -893,71 +827,59 @@ fieldset/CSR: description: CSS on LSE failure detection flag bit_offset: 14 bit_size: 1 - enum: CSSLSED - name: RTCSEL - description: RTC and LCD clock source selection bits + description: RTC and LCD clock source selection bit_offset: 16 bit_size: 2 enum: RTCSEL - name: RTCEN - description: RTC clock enable bit + description: RTC clock enable bit_offset: 18 bit_size: 1 - name: RTCRST - description: RTC software reset bit + description: RTC software reset bit_offset: 19 bit_size: 1 - enum_write: RTCRSTW - name: RMVF description: Remove reset flag bit_offset: 23 bit_size: 1 - enum_write: RMVFW - name: FWRSTF description: Firewall reset flag bit_offset: 24 bit_size: 1 - enum_read: LPWRRSTFR - name: OBLRSTF description: OBLRSTF bit_offset: 25 bit_size: 1 - enum_read: LPWRRSTFR - name: PINRSTF description: PIN reset flag bit_offset: 26 bit_size: 1 - enum_read: LPWRRSTFR - name: PORRSTF description: POR/PDR reset flag bit_offset: 27 bit_size: 1 - enum_read: LPWRRSTFR - name: SFTRSTF description: Software reset flag bit_offset: 28 bit_size: 1 - enum_read: LPWRRSTFR - name: IWDGRSTF description: Independent watchdog reset flag bit_offset: 29 bit_size: 1 - enum_read: LPWRRSTFR - name: WWDGRSTF description: Window watchdog reset flag bit_offset: 30 bit_size: 1 - enum_read: LPWRRSTFR - name: LPWRRSTF description: Low-power reset flag bit_offset: 31 bit_size: 1 - enum_read: LPWRRSTFR - name: LPWRSTF description: Low-power reset flag bit_offset: 31 bit_size: 1 - enum_read: LPWRSTFR fieldset/ICSCR: description: Internal clock sources calibration register fields: @@ -986,27 +908,27 @@ fieldset/IOPENR: description: GPIO clock enable register fields: - name: GPIOAEN - description: IO port A clock enable bit + description: IO port A clock enable bit_offset: 0 bit_size: 1 - name: GPIOBEN - description: IO port B clock enable bit + description: IO port B clock enable bit_offset: 1 bit_size: 1 - name: GPIOCEN - description: IO port A clock enable bit + description: IO port A clock enable bit_offset: 2 bit_size: 1 - name: GPIODEN - description: I/O port D clock enable bit + description: I/O port D clock enable bit_offset: 3 bit_size: 1 - name: GPIOEEN - description: IO port E clock enable bit + description: IO port E clock enable bit_offset: 4 bit_size: 1 - name: GPIOHEN - description: I/O port H clock enable bit + description: I/O port H clock enable bit_offset: 7 bit_size: 1 fieldset/IOPRSTR: @@ -1040,83 +962,29 @@ fieldset/IOPSMEN: description: GPIO clock enable in sleep mode register fields: - name: IOPASMEN - description: Port A clock enable during Sleep mode bit + description: Port A clock enable during Sleep mode bit_offset: 0 bit_size: 1 - name: IOPBSMEN - description: Port B clock enable during Sleep mode bit + description: Port B clock enable during Sleep mode bit_offset: 1 bit_size: 1 - name: IOPCSMEN - description: Port C clock enable during Sleep mode bit + description: Port C clock enable during Sleep mode bit_offset: 2 bit_size: 1 - name: IOPDSMEN - description: Port D clock enable during Sleep mode bit + description: Port D clock enable during Sleep mode bit_offset: 3 bit_size: 1 - name: IOPESMEN - description: Port E clock enable during Sleep mode bit + description: Port E clock enable during Sleep mode bit_offset: 4 bit_size: 1 - name: IOPHSMEN - description: Port H clock enable during Sleep mode bit + description: Port H clock enable during Sleep mode bit_offset: 7 bit_size: 1 -enum/CRYPRSTW: - bit_size: 1 - variants: - - name: Reset - description: Reset the module - value: 1 -enum/CSSHSECW: - bit_size: 1 - variants: - - name: Clear - description: Clear interrupt flag - value: 1 -enum/CSSHSEF: - bit_size: 1 - variants: - - name: NoClock - description: No clock security interrupt caused by HSE clock failure - value: 0 - - name: Clock - description: Clock security interrupt caused by HSE clock failure - value: 1 -enum/CSSLSE: - bit_size: 1 - variants: - - name: Disabled - description: LSE CSS interrupt disabled - value: 0 - - name: Enabled - description: LSE CSS interrupt enabled - value: 1 -enum/CSSLSED: - bit_size: 1 - variants: - - name: NoFailure - description: No failure detected on LSE (32 kHz oscillator) - value: 0 - - name: Failure - description: Failure detected on LSE (32 kHz oscillator) - value: 1 -enum/CSSLSEF: - bit_size: 1 - variants: - - name: NoFailure - description: No failure detected on LSE clock failure - value: 0 - - name: Failure - description: Failure detected on LSE clock failure - value: 1 -enum/DBGRSTW: - bit_size: 1 - variants: - - name: Reset - description: Reset the module - value: 1 enum/HPRE: bit_size: 4 variants: @@ -1147,69 +1015,6 @@ enum/HPRE: - name: Div512 description: system clock divided by 512 value: 15 -enum/HSEBYP: - bit_size: 1 - variants: - - name: NotBypassed - description: HSE oscillator not bypassed - value: 0 - - name: Bypassed - description: HSE oscillator bypassed - value: 1 -enum/HSERDYR: - bit_size: 1 - variants: - - name: NotReady - description: Oscillator is not stable - value: 0 - - name: Ready - description: Oscillator is stable - value: 1 -enum/HSI16RDYFR: - bit_size: 1 - variants: - - name: NotReady - description: HSI 16 MHz oscillator not ready - value: 0 - - name: Ready - description: HSI 16 MHz oscillator ready - value: 1 -enum/HSI48RDYFR: - bit_size: 1 - variants: - - name: NotInterrupted - description: No clock ready interrupt - value: 0 - - name: Interrupted - description: Clock ready interrupt - value: 1 -enum/HSIDIVFR: - bit_size: 1 - variants: - - name: NotDivided - description: 16 MHz HSI clock not divided - value: 0 - - name: Div4 - description: 16 MHz HSI clock divided by 4 - value: 1 -enum/HSIRDYFR: - bit_size: 1 - variants: - - name: NotReady - description: HSI 16 MHz oscillator not ready - value: 0 - - name: Ready - description: HSI 16 MHz oscillator ready - value: 1 -enum/HSIRDYIE: - bit_size: 1 - variants: - - name: Disabled - description: Ready interrupt disabled - value: 0 - - name: Enabled - description: Ready interrupt enabled - value: 1 enum/ICSEL: bit_size: 2 variants: @@ -1222,12 +1027,6 @@ enum/ICSEL: - name: HSI16 description: HSI16 clock selected as peripheral clock value: 2 -enum/LPTIMRSTW: - bit_size: 1 - variants: - - name: Reset - description: Reset the module - value: 1 enum/LPTIMSEL: bit_size: 2 variants: @@ -1243,7 +1042,7 @@ enum/LPTIMSEL: - name: LSE description: LSE clock selected as Timer clock value: 3 -enum/LPUARTSEL: +enum/UARTSEL: bit_size: 2 variants: - name: APB @@ -1258,33 +1057,6 @@ enum/LPUARTSEL: - name: LSE description: LSE clock selected as peripheral clock value: 3 -enum/LPWRRSTFR: - bit_size: 1 - variants: - - name: NoReset - description: No reset has occured - value: 0 - - name: Reset - description: A reset has occured - value: 1 -enum/LPWRSTFR: - bit_size: 1 - variants: - - name: NoReset - description: No reset has occured - value: 0 - - name: Reset - description: A reset has occured - value: 1 -enum/LSEBYP: - bit_size: 1 - variants: - - name: NotBypassed - description: LSE oscillator not bypassed - value: 0 - - name: Bypassed - description: LSE oscillator bypassed - value: 1 enum/LSEDRV: bit_size: 2 variants: @@ -1300,15 +1072,6 @@ enum/LSEDRV: - name: High description: Highest drive value: 3 -enum/LSERDY: - bit_size: 1 - variants: - - name: NotReady - description: Oscillator not ready - value: 0 - - name: Ready - description: Oscillator ready - value: 1 enum/MCOPRE: bit_size: 3 variants: @@ -1381,24 +1144,6 @@ enum/MSIRANGE: - name: Range7 description: not allowed value: 7 -enum/MSIRDYFR: - bit_size: 1 - variants: - - name: NotInterrupted - description: No clock ready interrupt - value: 0 - - name: Interrupted - description: Clock ready interrupt - value: 1 -enum/MSIRDYIE: - bit_size: 1 - variants: - - name: Disabled - description: Ready interrupt disabled - value: 0 - - name: Enabled - description: Ready interrupt enabled - value: 1 enum/PLLDIV: bit_size: 2 variants: @@ -1441,15 +1186,6 @@ enum/PLLMUL: - name: Mul48 description: PLL clock entry x 48 value: 8 -enum/PLLRDYR: - bit_size: 1 - variants: - - name: Unlocked - description: PLL unlocked - value: 0 - - name: Locked - description: PLL locked - value: 1 enum/PLLSRC: bit_size: 1 variants: @@ -1477,12 +1213,6 @@ enum/PPRE: - name: Div16 description: HCLK divided by 16 value: 7 -enum/RMVFW: - bit_size: 1 - variants: - - name: Clear - description: Clears the reset flag - value: 1 enum/RTCPRE: bit_size: 2 variants: @@ -1498,12 +1228,6 @@ enum/RTCPRE: - name: Div16 description: HSE divided by 16 value: 3 -enum/RTCRSTW: - bit_size: 1 - variants: - - name: Reset - description: Resets the RTC peripheral - value: 1 enum/RTCSEL: bit_size: 2 variants: @@ -1543,18 +1267,3 @@ enum/SW: - name: PLL description: PLL used as system clock value: 3 -enum/SWS: - bit_size: 2 - variants: - - name: MSI - description: MSI oscillator used as system clock - value: 0 - - name: HSI16 - description: HSI oscillator used as system clock - value: 1 - - name: HSE - description: HSE oscillator used as system clock - value: 2 - - name: PLL - description: PLL used as system clock - value: 3 diff --git a/data/registers/rcc_l1.yaml b/data/registers/rcc_l1.yaml index 0fd7cd5..da22f2f 100644 --- a/data/registers/rcc_l1.yaml +++ b/data/registers/rcc_l1.yaml @@ -568,42 +568,52 @@ fieldset/CFGR: description: System clock switch bit_offset: 0 bit_size: 2 + enum: SW - name: SWS description: System clock switch status bit_offset: 2 bit_size: 2 + enum: SW - name: HPRE description: AHB prescaler bit_offset: 4 bit_size: 4 + enum: HPRE - name: PPRE1 description: APB low-speed prescaler (APB1) bit_offset: 8 bit_size: 3 + enum: PPRE - name: PPRE2 description: APB high-speed prescaler (APB2) bit_offset: 11 bit_size: 3 + enum: PPRE - name: PLLSRC description: PLL entry clock source bit_offset: 16 bit_size: 1 + enum: PLLSRC - name: PLLMUL description: PLL multiplication factor bit_offset: 18 bit_size: 4 + enum: PLLMUL - name: PLLDIV description: PLL output division bit_offset: 22 bit_size: 2 + enum: PLLDIV - name: MCOSEL description: Microcontroller clock output selection bit_offset: 24 bit_size: 3 + enum: MCOSEL - name: MCOPRE description: Microcontroller clock output prescaler bit_offset: 28 bit_size: 3 + enum: MCOPRE fieldset/CIR: description: Clock interrupt register fields: @@ -730,16 +740,13 @@ fieldset/CR: description: Clock security system enable bit_offset: 28 bit_size: 1 - - name: RTCPRE0 - description: RTCPRE0 + - name: RTCPRE + description: RTC/LCD prescaler bit_offset: 29 - bit_size: 1 - - name: RTCPRE1 - description: TC/LCD prescaler - bit_offset: 30 - bit_size: 1 + bit_size: 2 + enum: RTCPRE fieldset/CSR: - description: Control/status register + description: Control and status register fields: - name: LSION description: Internal low-speed oscillator enable @@ -765,6 +772,7 @@ fieldset/CSR: description: RTC and LCD clock source selection bit_offset: 16 bit_size: 2 + enum: RTCSEL - name: RTCEN description: RTC clock enable bit_offset: 22 @@ -816,6 +824,7 @@ fieldset/ICSCR: description: MSI clock ranges bit_offset: 13 bit_size: 3 + enum: MSIRANGE - name: MSICAL description: MSI clock calibration bit_offset: 16 @@ -824,3 +833,219 @@ fieldset/ICSCR: description: MSI clock trimming bit_offset: 24 bit_size: 8 +enum/HPRE: + bit_size: 4 + variants: + - name: Div1 + description: system clock not divided + value: 0 + - name: Div2 + description: system clock divided by 2 + value: 8 + - name: Div4 + description: system clock divided by 4 + value: 9 + - name: Div8 + description: system clock divided by 8 + value: 10 + - name: Div16 + description: system clock divided by 16 + value: 11 + - name: Div64 + description: system clock divided by 64 + value: 12 + - name: Div128 + description: system clock divided by 128 + value: 13 + - name: Div256 + description: system clock divided by 256 + value: 14 + - name: Div512 + description: system clock divided by 512 + value: 15 +enum/MCOPRE: + bit_size: 3 + variants: + - name: Div1 + description: No division + value: 0 + - name: Div2 + description: Division by 2 + value: 1 + - name: Div4 + description: Division by 4 + value: 2 + - name: Div8 + description: Division by 8 + value: 3 + - name: Div16 + description: Division by 16 + value: 4 +enum/MCOSEL: + bit_size: 4 + variants: + - name: NoClock + description: No clock + value: 0 + - name: SYSCLK + description: SYSCLK clock selected + value: 1 + - name: HSI + description: HSI oscillator clock selected + value: 2 + - name: MSI + description: MSI oscillator clock selected + value: 3 + - name: HSE + description: HSE oscillator clock selected + value: 4 + - name: PLL + description: PLL clock selected + value: 5 + - name: LSI + description: LSI oscillator clock selected + value: 6 + - name: LSE + description: LSE oscillator clock selected + value: 7 +enum/MSIRANGE: + bit_size: 3 + variants: + - name: Range0 + description: range 0 around 65.536 kHz + value: 0 + - name: Range1 + description: range 1 around 131.072 kHz + value: 1 + - name: Range2 + description: range 2 around 262.144 kHz + value: 2 + - name: Range3 + description: range 3 around 524.288 kHz + value: 3 + - name: Range4 + description: range 4 around 1.048 MHz + value: 4 + - name: Range5 + description: range 5 around 2.097 MHz (reset value) + value: 5 + - name: Range6 + description: range 6 around 4.194 MHz + value: 6 + - name: Range7 + description: not allowed + value: 7 +enum/PLLDIV: + bit_size: 2 + variants: + - name: Div2 + description: PLLVCO / 2 + value: 1 + - name: Div3 + description: PLLVCO / 3 + value: 2 + - name: Div4 + description: PLLVCO / 4 + value: 3 +enum/PLLMUL: + bit_size: 4 + variants: + - name: Mul3 + description: PLL clock entry x 3 + value: 0 + - name: Mul4 + description: PLL clock entry x 4 + value: 1 + - name: Mul6 + description: PLL clock entry x 6 + value: 2 + - name: Mul8 + description: PLL clock entry x 8 + value: 3 + - name: Mul12 + description: PLL clock entry x 12 + value: 4 + - name: Mul16 + description: PLL clock entry x 16 + value: 5 + - name: Mul24 + description: PLL clock entry x 24 + value: 6 + - name: Mul32 + description: PLL clock entry x 32 + value: 7 + - name: Mul48 + description: PLL clock entry x 48 + value: 8 +enum/PLLSRC: + bit_size: 1 + variants: + - name: HSI + description: HSI selected as PLL input clock + value: 0 + - name: HSE + description: HSE selected as PLL input clock + value: 1 +enum/PPRE: + bit_size: 3 + variants: + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 +enum/RTCPRE: + bit_size: 2 + variants: + - name: Div2 + description: HSE divided by 2 + value: 0 + - name: Div4 + description: HSE divided by 4 + value: 1 + - name: Div8 + description: HSE divided by 8 + value: 2 + - name: Div16 + description: HSE divided by 16 + value: 3 +enum/RTCSEL: + bit_size: 2 + variants: + - name: NoClock + description: No clock + value: 0 + - name: LSE + description: LSE oscillator clock used as RTC clock + value: 1 + - name: LSI + description: LSI oscillator clock used as RTC clock + value: 2 + - name: HSE + description: "HSE oscillator clock divided by a programmable prescaler (selection through the RTCPRE[1:0] bits in the RCC clock control register (RCC_CR)) used as the RTC clock" + value: 3 +enum/SW: + bit_size: 2 + variants: + - name: MSI + description: MSI oscillator used as system clock + value: 0 + - name: HSI + description: HSI oscillator used as system clock + value: 1 + - name: HSE + description: HSE oscillator used as system clock + value: 2 + - name: PLL + description: PLL used as system clock + value: 3 diff --git a/data/registers/rcc_l4.yaml b/data/registers/rcc_l4.yaml index 81fb843..30da215 100644 --- a/data/registers/rcc_l4.yaml +++ b/data/registers/rcc_l4.yaml @@ -1101,6 +1101,7 @@ fieldset/BDCR: description: SE oscillator drive capability bit_offset: 3 bit_size: 2 + enum: LSEDRV - name: LSECSSON description: LSECSSON bit_offset: 5 @@ -1113,6 +1114,7 @@ fieldset/BDCR: description: RTC clock source selection bit_offset: 8 bit_size: 2 + enum: RTCSEL - name: RTCEN description: RTC clock enable bit_offset: 15 @@ -1246,34 +1248,42 @@ fieldset/CFGR: description: System clock switch bit_offset: 0 bit_size: 2 + enum: SW - name: SWS description: System clock switch status bit_offset: 2 bit_size: 2 + enum: SW - name: HPRE description: AHB prescaler bit_offset: 4 bit_size: 4 + enum: HPRE - name: PPRE1 - description: PB low-speed prescaler (APB1) + description: APB low-speed prescaler (APB1) bit_offset: 8 bit_size: 3 + enum: PPRE - name: PPRE2 description: APB high-speed prescaler (APB2) bit_offset: 11 bit_size: 3 + enum: PPRE - name: STOPWUCK description: Wakeup from Stop and CSS backup clock selection bit_offset: 15 bit_size: 1 + enum: STOPWUCK - name: MCOSEL - description: Microcontroller clock output + description: Microcontroller clock output selection bit_offset: 24 - bit_size: 3 + bit_size: 4 + enum: MCOSEL - name: MCOPRE description: Microcontroller clock output prescaler bit_offset: 28 bit_size: 3 + enum: MCOPRE fieldset/CICR: description: Clock interrupt clear register fields: @@ -1587,6 +1597,7 @@ fieldset/PLLCFGR: description: "Main PLL, PLLSAI1 and PLLSAI2 entry clock source" bit_offset: 0 bit_size: 2 + enum: PLLSRC - name: PLLM description: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock bit_offset: 4 @@ -1701,6 +1712,99 @@ fieldset/PLLSAI2CFGR: description: PLLSAI2 division factor for PLLSAI2CLK bit_offset: 27 bit_size: 5 +enum/HPRE: + bit_size: 4 + variants: + - name: Div1 + description: system clock not divided + value: 0 + - name: Div2 + description: system clock divided by 2 + value: 8 + - name: Div4 + description: system clock divided by 4 + value: 9 + - name: Div8 + description: system clock divided by 8 + value: 10 + - name: Div16 + description: system clock divided by 16 + value: 11 + - name: Div64 + description: system clock divided by 64 + value: 12 + - name: Div128 + description: system clock divided by 128 + value: 13 + - name: Div256 + description: system clock divided by 256 + value: 14 + - name: Div512 + description: system clock divided by 512 + value: 15 +enum/LSEDRV: + bit_size: 2 + variants: + - name: Low + description: Lowest drive + value: 0 + - name: MediumLow + description: Medium low drive + value: 1 + - name: MediumHigh + description: Medium high drive + value: 2 + - name: High + description: Highest drive + value: 3 +enum/MCOPRE: + bit_size: 3 + variants: + - name: Div1 + description: No division + value: 0 + - name: Div2 + description: Division by 2 + value: 1 + - name: Div4 + description: Division by 4 + value: 2 + - name: Div8 + description: Division by 8 + value: 3 + - name: Div16 + description: Division by 16 + value: 4 +enum/MCOSEL: + bit_size: 4 + variants: + - name: NoClock + description: No clock + value: 0 + - name: SYSCLK + description: SYSCLK clock selected + value: 1 + - name: HSI16 + description: HSI oscillator clock selected + value: 2 + - name: MSI + description: MSI oscillator clock selected + value: 3 + - name: HSE + description: HSE oscillator clock selected + value: 4 + - name: PLL + description: PLL clock selected + value: 5 + - name: LSI + description: LSI oscillator clock selected + value: 6 + - name: LSE + description: LSE oscillator clock selected + value: 7 + - name: HSI48 + description: HSI48 oscillator clock selected + value: 8 enum/MSIRANGE: bit_size: 4 variants: @@ -1740,3 +1844,75 @@ enum/MSIRANGE: - name: Range48M description: range 11 around 48 MHz value: 11 +enum/PLLSRC: + bit_size: 2 + variants: + - name: None + description: No clock sent to PLL + value: 0 + - name: MSI + description: MSI selected as PLL input clock + value: 1 + - name: HSI16 + description: HSI selected as PLL input clock + value: 2 + - name: HSE + description: HSE selected as PLL input clock + value: 3 +enum/PPRE: + bit_size: 3 + variants: + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 +enum/RTCSEL: + bit_size: 2 + variants: + - name: NoClock + description: No clock + value: 0 + - name: LSE + description: LSE oscillator clock used as RTC clock + value: 1 + - name: LSI + description: LSI oscillator clock used as RTC clock + value: 2 + - name: HSE + description: HSE oscillator clock divided by 32 used as the RTC clock + value: 3 +enum/STOPWUCK: + bit_size: 1 + variants: + - name: MSI + description: Internal 64 KHz to 4 MHz (MSI) oscillator selected as wake-up from Stop clock + value: 0 + - name: HSI16 + description: Internal 16 MHz (HSI) oscillator selected as wake-up from Stop clock (or HSI16/4 if HSI16DIVEN=1) + value: 1 +enum/SW: + bit_size: 2 + variants: + - name: MSI + description: MSI oscillator used as system clock + value: 0 + - name: HSI16 + description: HSI oscillator used as system clock + value: 1 + - name: HSE + description: HSE oscillator used as system clock + value: 2 + - name: PLL + description: PLL used as system clock + value: 3