Merge pull request #400 from eZioPan/dcache_remove_32bit
dcache remove 32bit
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commit
07e666fa9d
2
Cargo.lock
generated
2
Cargo.lock
generated
@ -85,7 +85,7 @@ checksum = "d468802bab17cbc0cc575e9b053f41e72aa36bfa6b7f55e3529ffa43161b97fa"
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[[package]]
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name = "chiptool"
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version = "0.1.0"
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source = "git+https://github.com/embassy-rs/chiptool?rev=689341ad3437280d3553cef319d1e77470f2e704#689341ad3437280d3553cef319d1e77470f2e704"
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source = "git+https://github.com/embassy-rs/chiptool?rev=247ccbe44669ac716393247e56693a396e641e4a#247ccbe44669ac716393247e56693a396e641e4a"
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dependencies = [
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"anyhow",
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"clap",
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@ -20,7 +20,6 @@ block/DCACHE:
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- name: RHMONR
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description: DCACHE read-hit monitor register.
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byte_offset: 16
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fieldset: RHMONR
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- name: RMMONR
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description: DCACHE read-miss monitor register.
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byte_offset: 20
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@ -28,7 +27,6 @@ block/DCACHE:
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- name: WHMONR
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description: DCACHE write-hit monitor register.
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byte_offset: 32
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fieldset: WHMONR
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- name: WMMONR
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description: DCACHE write-miss monitor register.
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byte_offset: 36
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@ -140,13 +138,6 @@ fieldset/IER:
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description: interrupt enable on command end Set by software to enable an interrupt generation at the end of a cache command (clean and/or invalidate an address range).
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bit_offset: 4
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bit_size: 1
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fieldset/RHMONR:
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description: DCACHE read-hit monitor register.
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fields:
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- name: RHITMON
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description: cache read-hit monitor counter.
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bit_offset: 0
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bit_size: 32
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fieldset/RMMONR:
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description: DCACHE read-miss monitor register.
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fields:
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@ -177,13 +168,6 @@ fieldset/SR:
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description: command end flag Cleared by writing DCACHE_FCR.CCMDENDF = 1.
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bit_offset: 4
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bit_size: 1
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fieldset/WHMONR:
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description: DCACHE write-hit monitor register.
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fields:
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- name: WHITMON
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description: cache write-hit monitor counter.
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bit_offset: 0
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bit_size: 32
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fieldset/WMMONR:
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description: DCACHE write-miss monitor register.
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fields:
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3
transforms/DCACHE.yaml
Normal file
3
transforms/DCACHE.yaml
Normal file
@ -0,0 +1,3 @@
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transforms:
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- !DeleteFieldsets
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from: (R|W)HMONR
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