fix RCC MCO register for f1 CL variants

data/registers/rcc_f1.yaml

@@ -873,7 +873,7 @@ enum/I2S2SRC:
       description: PLL3 VCO clock selected as I2S clock entry
       value: 1
 enum/MCO:
-  bit_size: 4
+  bit_size: 3
   variants:
     - name: NoMCO
       description: "MCO output disabled, no clock on MCO"
@@ -888,7 +888,7 @@ enum/MCO:
       description: HSE oscillator clock selected
       value: 6
     - name: PLL
-      description: "PLL clock selected (divided by 1 or 2, depending en PLLNODIV)"
+      description: "PLL clock divided by 2 selected"
       value: 7
 enum/OTGFSPRE:
   bit_size: 1