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Merge pull request #288 from xoviat/rcc

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rcc: more mux and enum cleanup
This commit is contained in:
xoviat 2023-10-15 23:13:43 +00:00 committed by GitHub
commit 01a757e40d
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29 changed files with 250 additions and 202 deletions
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26
data/registers/rcc_c0.yaml
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@ -685,10 +685,10 @@ fieldset/ICSCR:
enum/ADCSEL:
bit_size: 2
variants:
- name: SYSCLK
- name: SYS
description: System clock
value: 0
- name: HSIKER
- name: HSI
description: HSIKER
value: 2
enum/HPRE:
@ -778,22 +778,22 @@ enum/HSIKERDIV:
enum/I2C1SEL:
bit_size: 2
variants:
- name: PCLK
- name: PCLK1
description: PCLK
value: 0
- name: SYSCLK
- name: SYS
description: SYSCLK
value: 1
- name: HSIKER
- name: HSI
description: HSIKER
value: 2
enum/I2S1SEL:
bit_size: 2
variants:
- name: SYSCLK
- name: SYS
description: SYSCLK
value: 0
- name: HSIKER
- name: HSI
description: HSIKER
value: 2
- name: I2S_CKIN
@ -853,10 +853,10 @@ enum/MCOPRE:
enum/MCOSEL:
bit_size: 4
variants:
- name: NoClock
- name: DISABLE
description: No clock, MCO output disabled
value: 0
- name: SYSCLK
- name: SYS
description: SYSCLK selected as MCO source
value: 1
- name: HSI48
@ -892,7 +892,7 @@ enum/PPRE:
enum/RTCSEL:
bit_size: 2
variants:
- name: NoClock
- name: DISABLE
description: No clock used as RTC clock
value: 0
- name: LSE
@ -949,13 +949,13 @@ enum/SYSDIV:
enum/USART1SEL:
bit_size: 2
variants:
- name: PCLK
- name: PCLK1
description: PCLK
value: 0
- name: SYSCLK
- name: SYS
description: SYSCLK
value: 1
- name: HSIKER
- name: HSI
description: HSIKER
value: 2
- name: LSE

10
data/registers/rcc_f0.yaml
View File

@ -799,7 +799,7 @@ enum/ICSW:
- name: HSI
description: HSI clock selected as I2C clock source
value: 0
- name: SYSCLK
- name: SYS
description: SYSCLK clock selected as I2C clock source
value: 1
enum/LSEDRV:
@ -859,7 +859,7 @@ enum/MCOSEL:
- name: LSE
description: External low speed (LSE) oscillator clock selected
value: 3
- name: SYSCLK
- name: SYS
description: System clock selected
value: 4
- name: HSI
@ -1027,7 +1027,7 @@ enum/PREDIV:
enum/RTCSEL:
bit_size: 2
variants:
- name: NoClock
- name: DISABLE
description: No clock
value: 0
- name: LSE
@ -1057,10 +1057,10 @@ enum/SW:
enum/USARTSW:
bit_size: 2
variants:
- name: PCLK
- name: PCLK1
description: PCLK selected as USART clock source
value: 0
- name: SYSCLK
- name: SYS
description: SYSCLK selected as USART clock source
value: 1
- name: LSE

2
data/registers/rcc_f1.yaml
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@ -801,7 +801,7 @@ enum/PPRE:
enum/RTCSEL:
bit_size: 2
variants:
- name: NoClock
- name: DISABLE
description: No clock
value: 0
- name: LSE

2
data/registers/rcc_f100.yaml
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@ -823,7 +823,7 @@ enum/PREDIV1:
enum/RTCSEL:
bit_size: 2
variants:
- name: NoClock
- name: DISABLE
description: No clock
value: 0
- name: LSE

2
data/registers/rcc_f1cl.yaml
View File

@ -913,7 +913,7 @@ enum/PREDIV1SRC:
enum/RTCSEL:
bit_size: 2
variants:
- name: NoClock
- name: DISABLE
description: No clock
value: 0
- name: LSE

2
data/registers/rcc_f2.yaml
View File

@ -1950,7 +1950,7 @@ enum/PPRE:
enum/RTCSEL:
bit_size: 2
variants:
- name: NoClock
- name: DISABLE
description: No clock
value: 0
- name: LSE

12
data/registers/rcc_f3.yaml
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@ -938,13 +938,13 @@ enum/ICSW:
- name: HSI
description: HSI clock selected as I2C clock source
value: 0
- name: SYSCLK
- name: SYS
description: SYSCLK clock selected as I2C clock source
value: 1
enum/ISSRC:
bit_size: 1
variants:
- name: SYSCLK
- name: SYS
description: System clock used as I2S clock source
value: 0
- name: CKIN
@ -1004,7 +1004,7 @@ enum/MCOSEL:
- name: LSE
description: External low speed (LSE) oscillator clock selected
value: 3
- name: SYSCLK
- name: SYS
description: System clock selected
value: 4
- name: HSI
@ -1166,7 +1166,7 @@ enum/PREDIV:
enum/RTCSEL:
bit_size: 2
variants:
- name: NoClock
- name: DISABLE
description: No clock
value: 0
- name: LSE
@ -1253,10 +1253,10 @@ enum/TIMSW:
enum/USARTSW:
bit_size: 2
variants:
- name: PCLK
- name: PCLK1
description: PCLK selected as USART clock source
value: 0
- name: SYSCLK
- name: SYS
description: SYSCLK selected as USART clock source
value: 1
- name: LSE

14
data/registers/rcc_f3_v2.yaml
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@ -914,13 +914,13 @@ enum/ICSW:
- name: HSI
description: HSI clock selected as I2C clock source
value: 0
- name: SYSCLK
- name: SYS
description: SYSCLK clock selected as I2C clock source
value: 1
enum/ISSRC:
bit_size: 1
variants:
- name: SYSCLK
- name: SYS
description: System clock used as I2S clock source
value: 0
- name: CKIN
@ -971,7 +971,7 @@ enum/MCOPRE:
enum/MCOSEL:
bit_size: 3
variants:
- name: NoMCO
- name: DISABLE
description: MCO output disabled, no clock on MCO
value: 0
- name: LSI
@ -980,7 +980,7 @@ enum/MCOSEL:
- name: LSE
description: External low speed (LSE) oscillator clock selected
value: 3
- name: SYSCLK
- name: SYS
description: System clock selected
value: 4
- name: HSI
@ -1142,7 +1142,7 @@ enum/PREDIV:
enum/RTCSEL:
bit_size: 2
variants:
- name: NoClock
- name: DISABLE
description: No clock
value: 0
- name: LSE
@ -1229,10 +1229,10 @@ enum/TIMSW:
enum/USARTSW:
bit_size: 2
variants:
- name: PCLK
- name: PCLK1
description: PCLK selected as USART clock source
value: 0
- name: SYSCLK
- name: SYS
description: SYSCLK selected as USART clock source
value: 1
- name: LSE

6
data/registers/rcc_f4.yaml
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@ -1766,7 +1766,7 @@ enum/CKDFSDMASEL:
enum/CKDFSDMSEL:
bit_size: 1
variants:
- name: APB2
- name: PCLK2
description: APB2 clock used as Kernel clock
value: 0
- name: SYSCLK
@ -1859,7 +1859,7 @@ enum/ISSRC:
enum/LPTIMSEL:
bit_size: 2
variants:
- name: APB1
- name: PCLK1
description: APB1 clock (PCLK1) selected as LPTILM1 clock
value: 0
- name: LSI
@ -3365,7 +3365,7 @@ enum/PPRE:
enum/RTCSEL:
bit_size: 2
variants:
- name: NoClock
- name: DISABLE
description: No clock
value: 0
- name: LSE

4
data/registers/rcc_f410.yaml
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@ -849,7 +849,7 @@ enum/ISSRC:
enum/LPTIMSEL:
bit_size: 2
variants:
- name: APB1
- name: PCLK1
description: APB1 clock (PCLK1) selected as LPTILM1 clock
value: 0
- name: LSI
@ -1896,7 +1896,7 @@ enum/PPRE:
enum/RTCSEL:
bit_size: 2
variants:
- name: NoClock
- name: DISABLE
description: No clock
value: 0
- name: LSE

10
data/registers/rcc_f7.yaml
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@ -1716,7 +1716,7 @@ enum/CKMSEL:
enum/DFSDMSEL:
bit_size: 1
variants:
- name: APB2
- name: PCLK2
description: APB2 clock (PCLK2) selected as DFSDM1 Kernel clock source
value: 0
- name: SYSCLK
@ -1785,7 +1785,7 @@ enum/ISSRC:
enum/LPTIMSEL:
bit_size: 2
variants:
- name: APB1
- name: PCLK1
description: APB1 clock (PCLK1) selected as LPTILM1 clock
value: 0
- name: LSI
@ -3090,7 +3090,7 @@ enum/PPRE:
enum/RTCSEL:
bit_size: 2
variants:
- name: NoClock
- name: DISABLE
description: No clock
value: 0
- name: LSE
@ -3159,7 +3159,7 @@ enum/TIMPRE:
enum/USART1SEL:
bit_size: 2
variants:
- name: APB2
- name: PCLK2
description: APB2 clock (PCLK2) is selected as USART clock
value: 0
- name: SYSCLK
@ -3174,7 +3174,7 @@ enum/USART1SEL:
enum/USART2SEL:
bit_size: 2
variants:
- name: APB1
- name: PCLK1
description: APB1 clock (PCLK1) is selected as USART clock
value: 0
- name: SYSCLK

102
data/registers/rcc_g0.yaml
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@ -1179,13 +1179,13 @@ fieldset/PLLCFGR:
enum/ADCSEL:
bit_size: 2
variants:
- name: SYSCLK
- name: SYS
description: SYSCLK used as ADC clock source
value: 0
- name: PLLPCLK
- name: PLL1_P
description: PLLPCLK used as ADC clock source
value: 1
- name: HSI16
- name: HSI
description: HSI16 used as ADC clock source
value: 2
enum/CECSEL:
@ -1200,10 +1200,10 @@ enum/CECSEL:
enum/FDCANSEL:
bit_size: 2
variants:
- name: PCLK
- name: PCLK1
description: PCLK used as FDCAN clock source
value: 0
- name: PLLQCLK
- name: PLL1_Q
description: PLLQCLK used as FDCAN clock source
value: 1
- name: HSE
@ -1269,25 +1269,25 @@ enum/HSIDIV:
enum/I2C1SEL:
bit_size: 2
variants:
- name: PCLK
- name: PCLK1
description: PCLK used as I2C1 clock source
value: 0
- name: SYSCLK
- name: SYS
description: SYSCLK used as I2C1 clock source
value: 1
- name: HSI16
- name: HSI
description: HSI16 used as I2C1 clock source
value: 2
enum/I2C2I2S1SEL:
bit_size: 2
variants:
- name: PCLK
- name: PCLK1
description: PCLK used as I2C2/I2S2 clock source
value: 0
- name: SYSCLK
- name: SYS
description: SYSCLK used as I2C2/I2S2 clock source
value: 1
- name: HSI16
- name: HSI
description: HSI16 used as I2C2/I2S2 clock source
value: 2
- name: I2S_CKIN
@ -1296,13 +1296,13 @@ enum/I2C2I2S1SEL:
enum/I2S1SEL:
bit_size: 2
variants:
- name: SYSCLK
- name: SYS
description: SYSCLK used as I2S1 clock source
value: 0
- name: PLLPCLK
- name: PLL1_P
description: PLLPCLK used as I2S1 clock source
value: 1
- name: HSI16
- name: HSI
description: HSI used as I2S1 clock source
value: 2
- name: I2S_CKIN
@ -1311,13 +1311,13 @@ enum/I2S1SEL:
enum/I2S2SEL:
bit_size: 2
variants:
- name: SYSCLK
- name: SYS
description: SYSCLK used as I2S2 clock source
value: 0
- name: PLLPCLK
- name: PLL1_P
description: PLLPCLK used as I2S2 clock source
value: 1
- name: HSI16
- name: HSI
description: HSI used as I2S2 clock source
value: 2
- name: I2S_CKIN
@ -1326,13 +1326,13 @@ enum/I2S2SEL:
enum/LPTIM1SEL:
bit_size: 2
variants:
- name: PCLK
- name: PCLK1
description: PCLK used as LPTIM1 clock source
value: 0
- name: LSI
description: LSI used as LPTIM1 clock source
value: 1
- name: HSI16
- name: HSI
description: HSI16 used as LPTIM1 clock source
value: 2
- name: LSE
@ -1341,13 +1341,13 @@ enum/LPTIM1SEL:
enum/LPTIM2SEL:
bit_size: 2
variants:
- name: PCLK
- name: PCLK1
description: PCLK used as LPTIM2 clock source
value: 0
- name: LSI
description: LSI used as LPTIM2 clock source
value: 1
- name: HSI16
- name: HSI
description: HSI16 used as LPTIM2 clock source
value: 2
- name: LSE
@ -1356,13 +1356,13 @@ enum/LPTIM2SEL:
enum/LPUART1SEL:
bit_size: 2
variants:
- name: PCLK
- name: PCLK1
description: PCLK used as LPUART1 clock source
value: 0
- name: SYSCLK
- name: SYS
description: SYSCLK used as LPUART1 clock source
value: 1
- name: HSI16
- name: HSI
description: HSI16 used as LPUART1 clock source
value: 2
- name: LSE
@ -1371,13 +1371,13 @@ enum/LPUART1SEL:
enum/LPUART2SEL:
bit_size: 2
variants:
- name: PCLK
- name: PCLK1
description: PCLK used as LPUART2 clock source
value: 0
- name: SYSCLK
- name: SYS
description: SYSCLK used as LPUART2 clock source
value: 1
- name: HSI16
- name: HSI
description: HSI16 used as LPUART2 clock source
value: 2
- name: LSE
@ -1437,16 +1437,16 @@ enum/MCOPRE:
enum/MCOSEL:
bit_size: 4
variants:
- name: NoClock
- name: DISABLE
description: No clock, MCO output disabled
value: 0
- name: SYSCLK
- name: SYS
description: SYSCLK selected as MCO source
value: 1
- name: HSI48
description: HSI48 selected as MCO source
value: 2
- name: HSI16
- name: HSI
description: HSI16 selected as MCO source
value: 3
- name: HSE
@ -1461,10 +1461,10 @@ enum/MCOSEL:
- name: LSE
description: LSE selected as MCO source
value: 7
- name: PLLPCLK
- name: PLL1_P
description: PLLPCLK selected as MCO source
value: 8
- name: PLLQCLK
- name: PLL1_Q
description: PLLQCLK selected as MCO source
value: 9
- name: RTCCLK
@ -1755,10 +1755,10 @@ enum/PLLR:
enum/PLLSRC:
bit_size: 2
variants:
- name: NoClock
- name: DISABLE
description: No clock selected as PLL entry clock source
value: 0
- name: HSI16
- name: HSI
description: HSI16 selected as PLL entry clock source
value: 2
- name: HSE
@ -1800,22 +1800,22 @@ enum/RNGDIV:
enum/RNGSEL:
bit_size: 2
variants:
- name: NoClock
- name: DISABLE
description: No clock used as RNG clock source
value: 0
- name: HSI16_Div8
description: HSI divided by 8 used as RNG clock source
value: 1
- name: SYSCLK
- name: SYS
description: SYSCLK used as RNG clock source
value: 2
- name: PLLQCLK
- name: PLL1_Q
description: PLLQCLK used as RNG clock source
value: 3
enum/RTCSEL:
bit_size: 2
variants:
- name: NoClock
- name: DISABLE
description: No clock used as RTC clock
value: 0
- name: LSE
@ -1836,7 +1836,7 @@ enum/SW:
- name: HSE
description: HSE selected as system clock
value: 1
- name: PLLRCLK
- name: PLL1_R
description: PLLRCLK selected as system clock
value: 2
- name: LSI
@ -1851,7 +1851,7 @@ enum/TIM15SEL:
- name: TIMPCLK
description: TIMPCLK used as TIM15 clock source
value: 0
- name: PLLQCLK
- name: PLL1_Q
description: PLLQCLK used as TIM15 clock source
value: 1
enum/TIM1SEL:
@ -1860,19 +1860,19 @@ enum/TIM1SEL:
- name: TIMPCLK
description: TIMPCLK used as TIM1 clock source
value: 0
- name: PLLQCLK
- name: PLL1_Q
description: PLLQCLK used as TIM1 clock source
value: 1
enum/USART1SEL:
bit_size: 2
variants:
- name: PCLK
- name: PCLK1
description: PCLK used as USART1 clock source
value: 0
- name: SYSCLK
- name: SYS
description: SYSCLK used as USART1 clock source
value: 1
- name: HSI16
- name: HSI
description: HSI16 used as USART1 clock source
value: 2
- name: LSE
@ -1881,13 +1881,13 @@ enum/USART1SEL:
enum/USART2SEL:
bit_size: 2
variants:
- name: PCLK
- name: PCLK1
description: PCLK used as USART2 clock source
value: 0
- name: SYSCLK
- name: SYS
description: SYSCLK used as USART2 clock source
value: 1
- name: HSI16
- name: HSI
description: HSI16 used as USART2 clock source
value: 2
- name: LSE
@ -1896,13 +1896,13 @@ enum/USART2SEL:
enum/USART3SEL:
bit_size: 2
variants:
- name: PCLK
- name: PCLK1
description: PCLK used as USART3 clock source
value: 0
- name: SYSCLK
- name: SYS
description: SYSCLK used as USART3 clock source
value: 1
- name: HSI16
- name: HSI
description: HSI16 used as USART3 clock source
value: 2
- name: LSE
@ -1914,7 +1914,7 @@ enum/USBSEL:
- name: HSI48
description: HSI48 used as USB clock source
value: 0
- name: PLLQCLK
- name: PLL1_Q
description: PLLQCLK used as USB clock source
value: 1
- name: HSE

16
data/registers/rcc_g4.yaml
View File

@ -1358,7 +1358,7 @@ enum/CLK48SEL:
- name: HSI48
description: HSI48 oscillator clock selected as 48 MHz clock
value: 0
- name: PLLQCLK
- name: PLL1_Q
description: PLLQCLK selected as 48 MHz clock
value: 2
enum/HPRE:
@ -1427,13 +1427,13 @@ enum/MCOPRE:
enum/MCOSEL:
bit_size: 4
variants:
- name: NoClock
- name: DISABLE
description: No clock, MCO output disabled
value: 0
- name: SYS
description: SYSCLK selected as MCO source
value: 1
- name: HSI16
- name: HSI
description: HSI16 selected as MCO source
value: 3
- name: HSE
@ -1824,10 +1824,10 @@ enum/PLLR:
enum/PLLSRC:
bit_size: 2
variants:
- name: NoClock
- name: DISABLE
description: No clock selected as PLL entry clock source
value: 0
- name: HSI16
- name: HSI
description: HSI16 selected as PLL entry clock source
value: 2
- name: HSE
@ -1854,7 +1854,7 @@ enum/PPRE:
enum/RTCSEL:
bit_size: 2
variants:
- name: NoClock
- name: DISABLE
description: No clock used as RTC clock
value: 0
- name: LSE
@ -1869,12 +1869,12 @@ enum/RTCSEL:
enum/SW:
bit_size: 2
variants:
- name: HSI16
- name: HSI
description: HSI16 selected as system clock
value: 1
- name: HSE
description: HSE selected as system clock
value: 2
- name: PLLRCLK
- name: PLL1_R
description: PLLRCLK selected as system clock
value: 3

26
data/registers/rcc_h5.yaml
View File

@ -2125,7 +2125,7 @@ fieldset/SECCFGR:
enum/ADCDACSEL:
bit_size: 3
variants:
- name: HCLK
- name: HCLK1
description: rcc_hclk selected as kernel clock (default after reset)
value: 0
- name: SYS
@ -2245,7 +2245,7 @@ enum/HSIDIV:
enum/ICSEL:
bit_size: 2
variants:
- name: APB1
- name: PCLK1
description: rcc_pclk1 selected as peripheral clock
value: 0
- name: PLL3_R
@ -2260,7 +2260,7 @@ enum/ICSEL:
enum/LPTIMSEL:
bit_size: 3
variants:
- name: APB3
- name: PCLK3
description: rcc_pclk3 selected as peripheral clock
value: 0
- name: PLL2_P
@ -2281,7 +2281,7 @@ enum/LPTIMSEL:
enum/LPUARTSEL:
bit_size: 3
variants:
- name: APB3
- name: PCLK3
description: rcc_pclk3 selected as kernel clock (default after reset)
value: 0
- name: PLL2_Q
@ -2431,7 +2431,7 @@ enum/NSPRIV:
enum/OCTOSPISEL:
bit_size: 2
variants:
- name: AHB4
- name: HCLK4
description: rcc_hclk4 selected as kernel clock (default after reset)
value: 0
- name: PLL1_Q
@ -3925,7 +3925,7 @@ enum/RNGSEL:
enum/RTCSEL:
bit_size: 2
variants:
- name: NoClock
- name: DISABLE
description: no clock (default after Backup domain reset)
value: 0
- name: LSE
@ -4030,7 +4030,7 @@ enum/SPI3SEL:
enum/SPI4SEL:
bit_size: 3
variants:
- name: APB2
- name: PCLK2
description: rcc_pclk2 selected as kernel clock (default after reset)
value: 0
- name: PLL2_Q
@ -4051,7 +4051,7 @@ enum/SPI4SEL:
enum/SPI5SEL:
bit_size: 3
variants:
- name: APB3
- name: PCLK3
description: rcc_pclk3 selected as kernel clock (default after reset)
value: 0
- name: PLL2_Q
@ -4072,7 +4072,7 @@ enum/SPI5SEL:
enum/SPI6SEL:
bit_size: 3
variants:
- name: APB4
- name: PCLK4
description: rcc_pclk4 selected as peripheral clock
value: 0
- name: PLL2_Q
@ -4126,13 +4126,13 @@ enum/SW:
- name: HSE
description: HSE selected as system clock
value: 2
- name: PLL1
- name: PLL1_P
description: PLL1 selected as system clock
value: 3
enum/SYSTICKSEL:
bit_size: 2
variants:
- name: HCLK_DIV_8
- name: HCLK1_DIV_8
description: rcc_hclk/8 selected as clock source (default after reset)
value: 0
- name: LSI
@ -4162,7 +4162,7 @@ enum/TIMPRE:
enum/UARTSEL:
bit_size: 3
variants:
- name: APB1
- name: PCLK1
description: rcc_pclk1 selected as peripheral clock
value: 0
- name: PLL2_Q
@ -4183,7 +4183,7 @@ enum/UARTSEL:
enum/USARTSEL:
bit_size: 3
variants:
- name: APB2
- name: PCLK2
description: rcc_pclk2 selected as peripheral clock
value: 0
- name: PLL2_Q

16
data/registers/rcc_h50.yaml
View File

@ -1335,7 +1335,7 @@ fieldset/RSR:
enum/ADCDACSEL:
bit_size: 3
variants:
- name: HCLK
- name: HCLK1
description: rcc_hclk selected as kernel clock (default after reset)
value: 0
- name: SYS
@ -1443,7 +1443,7 @@ enum/HSIDIV:
enum/ICSEL:
bit_size: 2
variants:
- name: APB1
- name: PCLK1
description: rcc_pclk1 selected as peripheral clock
value: 0
- name: PLL3_R
@ -1458,7 +1458,7 @@ enum/ICSEL:
enum/LPTIMSEL:
bit_size: 3
variants:
- name: APB3
- name: PCLK3
description: rcc_pclk3 selected as peripheral clock
value: 0
- name: PLL2_P
@ -1476,7 +1476,7 @@ enum/LPTIMSEL:
enum/LPUARTSEL:
bit_size: 3
variants:
- name: APB3
- name: PCLK3
description: rcc_pclk3 selected as kernel clock (default after reset)
value: 0
- name: PLL2_Q
@ -3093,7 +3093,7 @@ enum/RNGSEL:
enum/RTCSEL:
bit_size: 2
variants:
- name: NoClock
- name: DISABLE
description: no clock (default after Backup domain reset)
value: 0
- name: LSE
@ -3108,7 +3108,7 @@ enum/RTCSEL:
enum/SPISEL:
bit_size: 3
variants:
- name: APB4
- name: PCLK4
description: rcc_pclk4 selected as peripheral clock
value: 0
- name: PLL2_Q
@ -3147,7 +3147,7 @@ enum/SW:
- name: HSE
description: HSE selected as system clock
value: 2
- name: PLL1
- name: PLL1_P
description: PLL1 selected as system clock
value: 3
enum/SYSTICKSEL:
@ -3183,7 +3183,7 @@ enum/TIMPRE:
enum/USARTSEL:
bit_size: 3
variants:
- name: APB2
- name: PCLK2
description: rcc_pclk2 selected as peripheral clock
value: 0
- name: PLL2_Q

22
data/registers/rcc_h7.yaml
View File

@ -3535,7 +3535,7 @@ enum/CKPERSEL:
enum/DFSDMSEL:
bit_size: 1
variants:
- name: APB2
- name: PCLK2
description: rcc_pclk2 selected as peripheral clock
value: 0
- name: SYS
@ -3556,7 +3556,7 @@ enum/FDCANSEL:
enum/FMCSEL:
bit_size: 2
variants:
- name: AHB3
- name: HCLK3
description: AHB3 selected as peripheral clock
value: 0
- name: PLL1_Q
@ -3625,7 +3625,7 @@ enum/HSIDIV:
enum/I2C1235SEL:
bit_size: 2
variants:
- name: APB1
- name: PCLK1
description: rcc_pclk1 selected as peripheral clock
value: 0
- name: PLL3_R
@ -3640,7 +3640,7 @@ enum/I2C1235SEL:
enum/I2C4SEL:
bit_size: 2
variants:
- name: APB4
- name: PCLK4
description: rcc_pclk4 selected as peripheral clock
value: 0
- name: PLL3_R
@ -3655,7 +3655,7 @@ enum/I2C4SEL:
enum/LPTIM1SEL:
bit_size: 3
variants:
- name: APB1
- name: PCLK1
description: rcc_pclk1 selected as peripheral clock
value: 0
- name: PLL2_P
@ -3676,7 +3676,7 @@ enum/LPTIM1SEL:
enum/LPTIM2SEL:
bit_size: 3
variants:
- name: APB4
- name: PCLK4
description: rcc_pclk4 selected as peripheral clock
value: 0
- name: PLL2_P
@ -5299,7 +5299,7 @@ enum/RNGSEL:
enum/RTCSEL:
bit_size: 2
variants:
- name: NoClock
- name: DISABLE
description: No clock
value: 0
- name: LSE
@ -5395,7 +5395,7 @@ enum/SPI45SEL:
enum/SPI6SEL:
bit_size: 3
variants:
- name: APB4
- name: PCLK4
description: rcc_pclk4 selected as peripheral clock
value: 0
- name: PLL2_Q
@ -5434,7 +5434,7 @@ enum/SW:
- name: HSE
description: HSE selected as system clock
value: 2
- name: PLL1
- name: PLL1_P
description: PLL1 selected as system clock
value: 3
enum/SWPSEL:
@ -5458,7 +5458,7 @@ enum/TIMPRE:
enum/USART16910SEL:
bit_size: 3
variants:
- name: APB2
- name: PCLK2
description: rcc_pclk2 selected as peripheral clock
value: 0
- name: PLL2_Q
@ -5479,7 +5479,7 @@ enum/USART16910SEL:
enum/USART234578SEL:
bit_size: 3
variants:
- name: APB1
- name: PCLK1
description: rcc_pclk1 selected as peripheral clock
value: 0
- name: PLL2_Q

22
data/registers/rcc_h7ab.yaml
View File

@ -2470,7 +2470,7 @@ enum/CKPERSEL:
enum/DFSDMSEL:
bit_size: 1
variants:
- name: APB2
- name: PCLK2
description: rcc_pclk2 selected as peripheral clock
value: 0
- name: SYS
@ -2491,7 +2491,7 @@ enum/FDCANSEL:
enum/FMCSEL:
bit_size: 2
variants:
- name: AHB3
- name: HCLK3
description: rcc_hclk3 selected as peripheral clock
value: 0
- name: PLL1_Q
@ -2560,7 +2560,7 @@ enum/HSIDIV:
enum/I2C1235SEL:
bit_size: 2
variants:
- name: APB1
- name: PCLK1
description: rcc_pclk1 selected as peripheral clock
value: 0
- name: PLL3_R
@ -2575,7 +2575,7 @@ enum/I2C1235SEL:
enum/I2C4SEL:
bit_size: 2
variants:
- name: APB4
- name: PCLK4
description: rcc_pclk4 selected as peripheral clock
value: 0
- name: PLL3_R
@ -2590,7 +2590,7 @@ enum/I2C4SEL:
enum/LPTIM1SEL:
bit_size: 3
variants:
- name: APB1
- name: PCLK1
description: rcc_pclk1 selected as peripheral clock
value: 0
- name: PLL2_P
@ -2611,7 +2611,7 @@ enum/LPTIM1SEL:
enum/LPTIM2SEL:
bit_size: 3
variants:
- name: APB4
- name: PCLK4
description: rcc_pclk4 selected as peripheral clock
value: 0
- name: PLL2_P
@ -4234,7 +4234,7 @@ enum/RNGSEL:
enum/RTCSEL:
bit_size: 2
variants:
- name: NoClock
- name: DISABLE
description: No clock
value: 0
- name: LSE
@ -4330,7 +4330,7 @@ enum/SPI45SEL:
enum/SPI6SEL:
bit_size: 3
variants:
- name: APB4
- name: PCLK4
description: rcc_pclk4 selected as peripheral clock
value: 0
- name: PLL2_Q
@ -4369,7 +4369,7 @@ enum/SW:
- name: HSE
description: HSE selected as system clock
value: 2
- name: PLL1
- name: PLL1_P
description: PLL1 selected as system clock
value: 3
enum/SWPSEL:
@ -4393,7 +4393,7 @@ enum/TIMPRE:
enum/USART16910SEL:
bit_size: 3
variants:
- name: APB2
- name: PCLK2
description: rcc_pclk2 selected as peripheral clock
value: 0
- name: PLL2_Q
@ -4414,7 +4414,7 @@ enum/USART16910SEL:
enum/USART234578SEL:
bit_size: 3
variants:
- name: APB1
- name: PCLK1
description: rcc_pclk1 selected as peripheral clock
value: 0
- name: PLL2_Q

22
data/registers/rcc_h7rm0433.yaml
View File

@ -3535,7 +3535,7 @@ enum/CKPERSEL:
enum/DFSDMSEL:
bit_size: 1
variants:
- name: APB2
- name: PCLK2
description: rcc_pclk2 selected as peripheral clock
value: 0
- name: SYS
@ -3556,7 +3556,7 @@ enum/FDCANSEL:
enum/FMCSEL:
bit_size: 2
variants:
- name: AHB3
- name: HCLK3
description: rcc_hclk3 selected as peripheral clock
value: 0
- name: PLL1_Q
@ -3625,7 +3625,7 @@ enum/HSIDIV:
enum/I2C1235SEL:
bit_size: 2
variants:
- name: APB1
- name: PCLK1
description: rcc_pclk1 selected as peripheral clock
value: 0
- name: PLL3_R
@ -3640,7 +3640,7 @@ enum/I2C1235SEL:
enum/I2C4SEL:
bit_size: 2
variants:
- name: APB4
- name: PCLK4
description: rcc_pclk4 selected as peripheral clock
value: 0
- name: PLL3_R
@ -3655,7 +3655,7 @@ enum/I2C4SEL:
enum/LPTIM1SEL:
bit_size: 3
variants:
- name: APB1
- name: PCLK1
description: rcc_pclk1 selected as peripheral clock
value: 0
- name: PLL2_P
@ -3676,7 +3676,7 @@ enum/LPTIM1SEL:
enum/LPTIM2SEL:
bit_size: 3
variants:
- name: APB4
- name: PCLK4
description: rcc_pclk4 selected as peripheral clock
value: 0
- name: PLL2_P
@ -5299,7 +5299,7 @@ enum/RNGSEL:
enum/RTCSEL:
bit_size: 2
variants:
- name: NoClock
- name: DISABLE
description: No clock
value: 0
- name: LSE
@ -5395,7 +5395,7 @@ enum/SPI45SEL:
enum/SPI6SEL:
bit_size: 3
variants:
- name: APB4
- name: PCLK4
description: rcc_pclk4 selected as peripheral clock
value: 0
- name: PLL2_Q
@ -5434,7 +5434,7 @@ enum/SW:
- name: HSE
description: HSE selected as system clock
value: 2
- name: PLL1
- name: PLL1_P
description: PLL1 selected as system clock
value: 3
enum/SWPSEL:
@ -5458,7 +5458,7 @@ enum/TIMPRE:
enum/USART16910SEL:
bit_size: 3
variants:
- name: APB2
- name: PCLK2
description: rcc_pclk2 selected as peripheral clock
value: 0
- name: PLL2_Q
@ -5479,7 +5479,7 @@ enum/USART16910SEL:
enum/USART234578SEL:
bit_size: 3
variants:
- name: APB1
- name: PCLK1
description: rcc_pclk1 selected as peripheral clock
value: 0
- name: PLL2_Q

4
data/registers/rcc_l0.yaml
View File

@ -1030,7 +1030,7 @@ enum/MCOPRE:
enum/MCOSEL:
bit_size: 4
variants:
- name: NoClock
- name: DISABLE
description: No clock
value: 0
- name: SYSCLK
@ -1168,7 +1168,7 @@ enum/RTCPRE:
enum/RTCSEL:
bit_size: 2
variants:
- name: NoClock
- name: DISABLE
description: No clock
value: 0
- name: LSE

4
data/registers/rcc_l0_v2.yaml
View File

@ -1069,7 +1069,7 @@ enum/MCOPRE:
enum/MCOSEL:
bit_size: 4
variants:
- name: NoClock
- name: DISABLE
description: No clock
value: 0
- name: SYSCLK
@ -1207,7 +1207,7 @@ enum/RTCPRE:
enum/RTCSEL:
bit_size: 2
variants:
- name: NoClock
- name: DISABLE
description: No clock
value: 0
- name: LSE

4
data/registers/rcc_l1.yaml
View File

@ -883,7 +883,7 @@ enum/MCOPRE:
enum/MCOSEL:
bit_size: 4
variants:
- name: NoClock
- name: DISABLE
description: No clock
value: 0
- name: SYSCLK
@ -1021,7 +1021,7 @@ enum/RTCPRE:
enum/RTCSEL:
bit_size: 2
variants:
- name: NoClock
- name: DISABLE
description: No clock
value: 0
- name: LSE

4
data/registers/rcc_l4.yaml
View File

@ -1742,7 +1742,7 @@ enum/MCOPRE:
enum/MCOSEL:
bit_size: 4
variants:
- name: NoClock
- name: DISABLE
description: No clock
value: 0
- name: SYSCLK
@ -2214,7 +2214,7 @@ enum/PPRE:
enum/RTCSEL:
bit_size: 2
variants:
- name: NoClock
- name: DISABLE
description: No clock
value: 0
- name: LSE

2
data/registers/rcc_l5.yaml
View File

@ -2514,7 +2514,7 @@ enum/PPRE:
enum/RTCSEL:
bit_size: 2
variants:
- name: NoClock
- name: DISABLE
description: No clock
value: 0
- name: LSE

2
data/registers/rcc_u5.yaml
View File

@ -4290,7 +4290,7 @@ enum/RNGSEL:
enum/RTCSEL:
bit_size: 2
variants:
- name: NoClock
- name: DISABLE
description: No clock selected
value: 0
- name: LSE

6
data/registers/rcc_wb.yaml
View File

@ -1745,7 +1745,7 @@ enum/MCOPRE:
enum/MCOSEL:
bit_size: 4
variants:
- name: NoClock
- name: DISABLE
description: No clock
value: 0
- name: SYSCLK
@ -2140,7 +2140,7 @@ enum/PLLR:
enum/PLLSRC:
bit_size: 2
variants:
- name: NoClock
- name: DISABLE
description: No clock selected as PLL entry clock source
value: 0
- name: MSI
@ -2173,7 +2173,7 @@ enum/PPRE:
enum/RTCSEL:
bit_size: 2
variants:
- name: NoClock
- name: DISABLE
description: No clock selected
value: 0
- name: LSE

2
data/registers/rcc_wba.yaml
View File

@ -1498,7 +1498,7 @@ enum/RNGSEL:
enum/RTCSEL:
bit_size: 2
variants:
- name: NoClock
- name: DISABLE
description: no clock selected, RTC and TAMP kernel clock disabled
value: 0
- name: LSE

6
data/registers/rcc_wl5.yaml
View File

@ -1533,7 +1533,7 @@ enum/MCOPRE:
enum/MCOSEL:
bit_size: 4
variants:
- name: NoClock
- name: DISABLE
description: No clock
value: 0
- name: SYSCLK
@ -1964,7 +1964,7 @@ enum/PLLR:
enum/PLLSRC:
bit_size: 2
variants:
- name: NoClock
- name: DISABLE
description: No clock selected as PLL entry clock source
value: 0
- name: MSI
@ -1997,7 +1997,7 @@ enum/PPRE:
enum/RTCSEL:
bit_size: 2
variants:
- name: NoClock
- name: DISABLE
description: No clock selected
value: 0
- name: LSE

6
data/registers/rcc_wle.yaml
View File

@ -1154,7 +1154,7 @@ enum/MCOPRE:
enum/MCOSEL:
bit_size: 4
variants:
- name: NoClock
- name: DISABLE
description: No clock
value: 0
- name: SYSCLK
@ -1585,7 +1585,7 @@ enum/PLLR:
enum/PLLSRC:
bit_size: 2
variants:
- name: NoClock
- name: DISABLE
description: No clock selected as PLL entry clock source
value: 0
- name: MSI
@ -1618,7 +1618,7 @@ enum/PPRE:
enum/RTCSEL:
bit_size: 2
variants:
- name: NoClock
- name: DISABLE
description: No clock selected
value: 0
- name: LSE

96
stm32-data-gen/src/rcc.rs
View File

@ -15,32 +15,80 @@ pub struct PeripheralToClock(
impl PeripheralToClock {
pub fn parse(registers: &Registers) -> anyhow::Result<Self> {
let mut peripheral_to_clock = HashMap::new();
let checked_rccs = HashSet::from([
"c0", "f0", "f1", "f100", "f1c1", "f3", "f3_v2", "f7", "g0", "g4", "h5", "h50", "h7", "h7ab", "h7rm0433",
]);
let allowed_variants = HashSet::from([
"DISABLE",
"SYS",
"PCLK1",
"PCLK1_TIM",
"PCLK2",
"PCLK2_TIM",
"PCLK3",
"PCLK4",
"PCLK5",
"PCLK6",
"PCLK7",
"HCLK1",
"HCLK2",
"HCLK3",
"HCLK4",
"HCLK5",
"HCLK6",
"HCLK7",
"PLLI2S1_P",
"PLLI2S1_Q",
"PLLI2S1_R",
"PLLI2S2_P",
"PLLI2S2_Q",
"PLLI2S2_R",
"PLLSAI1_P",
"PLLSAI1_Q",
"PLLSAI1_R",
"PLLSAI2_P",
"PLLSAI2_Q",
"PLLSAI2_R",
"PLL1_P",
"PLL1_Q",
"PLL1_R",
"PLL2_P",
"PLL2_Q",
"PLL2_R",
"PLL3_P",
"PLL3_Q",
"PLL3_R",
"HSI",
"HSI48",
"LSI",
"CSI",
"HSE",
"LSE",
"AUDIOCLK",
"PER",
// TODO: variants to cleanup
"B_0x0",
"B_0x1",
"PLL",
"PLLCLK",
"TIMPCLK",
"HSI_Div244",
"CSI_DIV_122",
"HSI16_Div488",
"HSI16_Div8",
"HCLK_DIV_8",
"HCLK1_DIV_8",
"RCC_PCLK_D3",
"I2S_CKIN",
"DAC_HOLD",
"DAC_HOLD_2",
"TIMPCLK",
"RTCCLK",
"RTC_WKUP",
]);
for (rcc_name, ir) in &registers.registers {
if let Some(rcc_name) = rcc_name.strip_prefix("rcc_") {
let checked_rccs = HashSet::from(["h5", "h50", "h7", "h7ab", "h7rm0433", "g4"]);
let prohibited_variants = HashSet::from([
"RCC_PCLK1",
"RCC_PCLK2",
"RCC_PCLK3",
"RCC_PCLK4",
"HSI_KER",
"HSI48_KER",
"CSI_KER",
"LSI_KER",
"PER_CLK",
"RCC_HCLK1",
"RCC_HCLK2",
"RCC_HCLK3",
"RCC_HCLK4",
"PLL3_1",
"NOCLK",
"PLLP",
"PLLQ",
"PLLR",
"SYSCLK",
]);
let rcc_enum_map: HashMap<&String, HashMap<&String, &Enum>> = {
let rcc_blocks = &ir.blocks.get("RCC").unwrap().items;
@ -83,7 +131,7 @@ impl PeripheralToClock {
};
for v in &enumm.variants {
if prohibited_variants.contains(v.name.as_str()) {
if !allowed_variants.contains(v.name.as_str()) {
return Err(anyhow!(
"rcc: prohibited variant name {} for rcc_{}",
v.name.as_str(),