1986 lines
42 KiB
YAML
1986 lines
42 KiB
YAML
block/RCC:
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description: Reset and clock control
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items:
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- name: CR
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description: clock control register
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byte_offset: 0
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fieldset: CR
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- name: PLLCFGR
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description: PLL configuration register
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byte_offset: 4
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fieldset: PLLCFGR
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- name: CFGR
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description: clock configuration register
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byte_offset: 8
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fieldset: CFGR
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- name: CIR
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description: clock interrupt register
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byte_offset: 12
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fieldset: CIR
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- name: AHB1RSTR
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description: AHB1 peripheral reset register
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byte_offset: 16
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fieldset: AHB1RSTR
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- name: AHB2RSTR
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description: AHB2 peripheral reset register
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byte_offset: 20
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fieldset: AHB2RSTR
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- name: AHB3RSTR
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description: AHB3 peripheral reset register
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byte_offset: 24
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fieldset: AHB3RSTR
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- name: APB1RSTR
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description: APB1 peripheral reset register
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byte_offset: 32
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fieldset: APB1RSTR
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- name: APB2RSTR
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description: APB2 peripheral reset register
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byte_offset: 36
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fieldset: APB2RSTR
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- name: AHB1ENR
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description: AHB1 peripheral clock register
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byte_offset: 48
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fieldset: AHB1ENR
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- name: AHB2ENR
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description: AHB2 peripheral clock enable register
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byte_offset: 52
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fieldset: AHB2ENR
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- name: AHB3ENR
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description: AHB3 peripheral clock enable register
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byte_offset: 56
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fieldset: AHB3ENR
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- name: APB1ENR
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description: APB1 peripheral clock enable register
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byte_offset: 64
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fieldset: APB1ENR
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- name: APB2ENR
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description: APB2 peripheral clock enable register
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byte_offset: 68
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fieldset: APB2ENR
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- name: AHB1LPENR
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description: AHB1 peripheral clock enable in low power mode register
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byte_offset: 80
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fieldset: AHB1LPENR
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- name: AHB2LPENR
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description: AHB2 peripheral clock enable in low power mode register
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byte_offset: 84
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fieldset: AHB2LPENR
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- name: AHB3LPENR
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description: AHB3 peripheral clock enable in low power mode register
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byte_offset: 88
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fieldset: AHB3LPENR
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- name: APB1LPENR
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description: APB1 peripheral clock enable in low power mode register
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byte_offset: 96
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fieldset: APB1LPENR
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- name: APB2LPENR
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description: APB2 peripheral clock enabled in low power mode register
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byte_offset: 100
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fieldset: APB2LPENR
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- name: BDCR
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description: Backup domain control register
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byte_offset: 112
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fieldset: BDCR
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- name: CSR
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description: clock control & status register
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byte_offset: 116
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fieldset: CSR
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- name: SSCGR
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description: spread spectrum clock generation register
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byte_offset: 128
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fieldset: SSCGR
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- name: PLLI2SCFGR
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description: PLLI2S configuration register
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byte_offset: 132
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fieldset: PLLI2SCFGR
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fieldset/AHB1ENR:
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description: AHB1 peripheral clock register
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fields:
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- name: GPIOAEN
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description: IO port A clock enable
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bit_offset: 0
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bit_size: 1
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- name: GPIOBEN
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description: IO port B clock enable
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bit_offset: 1
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bit_size: 1
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- name: GPIOCEN
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description: IO port C clock enable
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bit_offset: 2
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bit_size: 1
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- name: GPIODEN
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description: IO port D clock enable
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bit_offset: 3
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bit_size: 1
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- name: GPIOEEN
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description: IO port E clock enable
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bit_offset: 4
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bit_size: 1
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- name: GPIOFEN
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description: IO port F clock enable
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bit_offset: 5
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bit_size: 1
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- name: GPIOGEN
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description: IO port G clock enable
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bit_offset: 6
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bit_size: 1
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- name: GPIOHEN
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description: IO port H clock enable
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bit_offset: 7
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bit_size: 1
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- name: GPIOIEN
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description: IO port I clock enable
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bit_offset: 8
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bit_size: 1
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- name: CRCEN
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description: CRC clock enable
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bit_offset: 12
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bit_size: 1
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- name: BKPSRAMEN
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description: Backup SRAM interface clock enable
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bit_offset: 18
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bit_size: 1
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- name: DMA1EN
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description: DMA1 clock enable
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bit_offset: 21
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bit_size: 1
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- name: DMA2EN
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description: DMA2 clock enable
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bit_offset: 22
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bit_size: 1
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- name: ETHEN
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description: Ethernet MAC clock enable
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bit_offset: 25
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bit_size: 1
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- name: ETHTXEN
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description: Ethernet Transmission clock enable
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bit_offset: 26
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bit_size: 1
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- name: ETHRXEN
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description: Ethernet Reception clock enable
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bit_offset: 27
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bit_size: 1
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- name: ETHPTPEN
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description: Ethernet PTP clock enable
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bit_offset: 28
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bit_size: 1
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- name: USB_OTG_HSEN
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description: USB OTG HS clock enable
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bit_offset: 29
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bit_size: 1
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- name: USB_OTG_HSULPIEN
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description: USB OTG HSULPI clock enable
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bit_offset: 30
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bit_size: 1
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fieldset/AHB1LPENR:
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description: AHB1 peripheral clock enable in low power mode register
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fields:
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- name: GPIOALPEN
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description: IO port A clock enable during sleep mode
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bit_offset: 0
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bit_size: 1
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- name: GPIOBLPEN
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description: IO port B clock enable during Sleep mode
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bit_offset: 1
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bit_size: 1
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- name: GPIOCLPEN
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description: IO port C clock enable during Sleep mode
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bit_offset: 2
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bit_size: 1
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- name: GPIODLPEN
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description: IO port D clock enable during Sleep mode
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bit_offset: 3
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bit_size: 1
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- name: GPIOELPEN
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description: IO port E clock enable during Sleep mode
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bit_offset: 4
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bit_size: 1
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- name: GPIOFLPEN
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description: IO port F clock enable during Sleep mode
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bit_offset: 5
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bit_size: 1
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- name: GPIOGLPEN
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description: IO port G clock enable during Sleep mode
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bit_offset: 6
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bit_size: 1
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- name: GPIOHLPEN
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description: IO port H clock enable during Sleep mode
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bit_offset: 7
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bit_size: 1
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- name: GPIOILPEN
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description: IO port I clock enable during Sleep mode
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bit_offset: 8
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bit_size: 1
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- name: CRCLPEN
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description: CRC clock enable during Sleep mode
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bit_offset: 12
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bit_size: 1
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- name: FLASHLPEN
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description: Flash interface clock enable during Sleep mode
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bit_offset: 15
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bit_size: 1
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- name: SRAM1LPEN
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description: SRAM 1interface clock enable during Sleep mode
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bit_offset: 16
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bit_size: 1
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- name: SRAM2LPEN
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description: SRAM 2 interface clock enable during Sleep mode
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bit_offset: 17
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bit_size: 1
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- name: BKPSRAMLPEN
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description: Backup SRAM interface clock enable during Sleep mode
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bit_offset: 18
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bit_size: 1
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- name: DMA1LPEN
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description: DMA1 clock enable during Sleep mode
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bit_offset: 21
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bit_size: 1
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- name: DMA2LPEN
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description: DMA2 clock enable during Sleep mode
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bit_offset: 22
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bit_size: 1
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- name: ETHLPEN
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description: Ethernet MAC clock enable during Sleep mode
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bit_offset: 25
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bit_size: 1
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- name: ETHTXLPEN
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description: Ethernet transmission clock enable during Sleep mode
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bit_offset: 26
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bit_size: 1
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- name: ETHRXLPEN
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description: Ethernet reception clock enable during Sleep mode
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bit_offset: 27
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bit_size: 1
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- name: ETHPTPLPEN
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description: Ethernet PTP clock enable during Sleep mode
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bit_offset: 28
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bit_size: 1
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- name: USB_OTG_HSLPEN
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description: USB OTG HS clock enable during Sleep mode
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bit_offset: 29
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bit_size: 1
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- name: USB_OTG_HSULPILPEN
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description: USB OTG HS ULPI clock enable during Sleep mode
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bit_offset: 30
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bit_size: 1
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fieldset/AHB1RSTR:
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description: AHB1 peripheral reset register
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fields:
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- name: GPIOARST
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description: IO port A reset
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bit_offset: 0
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bit_size: 1
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- name: GPIOBRST
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description: IO port B reset
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bit_offset: 1
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bit_size: 1
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- name: GPIOCRST
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description: IO port C reset
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bit_offset: 2
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bit_size: 1
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- name: GPIODRST
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description: IO port D reset
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bit_offset: 3
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bit_size: 1
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- name: GPIOERST
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description: IO port E reset
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bit_offset: 4
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bit_size: 1
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- name: GPIOFRST
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description: IO port F reset
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bit_offset: 5
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bit_size: 1
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- name: GPIOGRST
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description: IO port G reset
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bit_offset: 6
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bit_size: 1
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- name: GPIOHRST
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description: IO port H reset
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bit_offset: 7
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bit_size: 1
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- name: GPIOIRST
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description: IO port I reset
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bit_offset: 8
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bit_size: 1
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- name: CRCRST
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description: CRC reset
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bit_offset: 12
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bit_size: 1
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- name: DMA1RST
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description: DMA2 reset
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bit_offset: 21
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bit_size: 1
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- name: DMA2RST
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description: DMA2 reset
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bit_offset: 22
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bit_size: 1
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- name: ETHRST
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description: Ethernet MAC reset
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bit_offset: 25
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bit_size: 1
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- name: USB_OTG_HSRST
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description: USB OTG HS module reset
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bit_offset: 29
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bit_size: 1
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fieldset/AHB2ENR:
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description: AHB2 peripheral clock enable register
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fields:
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- name: DCMIEN
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description: Camera interface enable
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bit_offset: 0
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bit_size: 1
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- name: CRYPEN
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description: Cryptographic modules clock enable
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bit_offset: 4
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bit_size: 1
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- name: HASHEN
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description: Hash modules clock enable
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bit_offset: 5
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bit_size: 1
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- name: RNGEN
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description: Random number generator clock enable
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bit_offset: 6
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bit_size: 1
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- name: USB_OTG_FSEN
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description: USB OTG FS clock enable
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bit_offset: 7
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bit_size: 1
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fieldset/AHB2LPENR:
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description: AHB2 peripheral clock enable in low power mode register
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fields:
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- name: DCMILPEN
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description: Camera interface enable during Sleep mode
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bit_offset: 0
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bit_size: 1
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- name: CRYPLPEN
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description: Cryptography modules clock enable during Sleep mode
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bit_offset: 4
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bit_size: 1
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- name: HASHLPEN
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description: Hash modules clock enable during Sleep mode
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bit_offset: 5
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bit_size: 1
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- name: RNGLPEN
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description: Random number generator clock enable during Sleep mode
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bit_offset: 6
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bit_size: 1
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- name: USB_OTG_FSLPEN
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description: USB OTG FS clock enable during Sleep mode
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bit_offset: 7
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bit_size: 1
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fieldset/AHB2RSTR:
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description: AHB2 peripheral reset register
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fields:
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- name: DCMIRST
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description: Camera interface reset
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bit_offset: 0
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bit_size: 1
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- name: CRYPRST
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description: Cryptographic module reset
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bit_offset: 4
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bit_size: 1
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- name: HSAHRST
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description: Hash module reset
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bit_offset: 5
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bit_size: 1
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- name: RNGRST
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description: Random number generator module reset
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bit_offset: 6
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bit_size: 1
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- name: USB_OTG_FSRST
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description: USB OTG FS module reset
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bit_offset: 7
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bit_size: 1
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fieldset/AHB3ENR:
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description: AHB3 peripheral clock enable register
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fields:
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- name: FSMCEN
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description: Flexible static memory controller module clock enable
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bit_offset: 0
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bit_size: 1
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fieldset/AHB3LPENR:
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description: AHB3 peripheral clock enable in low power mode register
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fields:
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- name: FSMCLPEN
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description: Flexible static memory controller module clock enable during Sleep mode
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bit_offset: 0
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bit_size: 1
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fieldset/AHB3RSTR:
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description: AHB3 peripheral reset register
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fields:
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- name: FSMCRST
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description: Flexible static memory controller module reset
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bit_offset: 0
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bit_size: 1
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fieldset/APB1ENR:
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description: APB1 peripheral clock enable register
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fields:
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- name: TIM2EN
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description: TIM2 clock enable
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bit_offset: 0
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bit_size: 1
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- name: TIM3EN
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description: TIM3 clock enable
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bit_offset: 1
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bit_size: 1
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- name: TIM4EN
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description: TIM4 clock enable
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bit_offset: 2
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bit_size: 1
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- name: TIM5EN
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description: TIM5 clock enable
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bit_offset: 3
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bit_size: 1
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- name: TIM6EN
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description: TIM6 clock enable
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bit_offset: 4
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bit_size: 1
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- name: TIM7EN
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description: TIM7 clock enable
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bit_offset: 5
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bit_size: 1
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- name: TIM12EN
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description: TIM12 clock enable
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bit_offset: 6
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bit_size: 1
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- name: TIM13EN
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description: TIM13 clock enable
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bit_offset: 7
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bit_size: 1
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- name: TIM14EN
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description: TIM14 clock enable
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bit_offset: 8
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bit_size: 1
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- name: WWDGEN
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description: Window watchdog clock enable
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bit_offset: 11
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bit_size: 1
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- name: SPI2EN
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description: SPI2 clock enable
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bit_offset: 14
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bit_size: 1
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- name: SPI3EN
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description: SPI3 clock enable
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bit_offset: 15
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bit_size: 1
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- name: USART2EN
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description: USART 2 clock enable
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bit_offset: 17
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bit_size: 1
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- name: USART3EN
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description: USART3 clock enable
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bit_offset: 18
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bit_size: 1
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- name: UART4EN
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description: UART4 clock enable
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bit_offset: 19
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bit_size: 1
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- name: UART5EN
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description: UART5 clock enable
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bit_offset: 20
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bit_size: 1
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- name: I2C1EN
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description: I2C1 clock enable
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bit_offset: 21
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bit_size: 1
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- name: I2C2EN
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description: I2C2 clock enable
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bit_offset: 22
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bit_size: 1
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- name: I2C3EN
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description: I2C3 clock enable
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bit_offset: 23
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bit_size: 1
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- name: CAN1EN
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description: CAN 1 clock enable
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bit_offset: 25
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bit_size: 1
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- name: CAN2EN
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description: CAN 2 clock enable
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bit_offset: 26
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bit_size: 1
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- name: PWREN
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description: Power interface clock enable
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bit_offset: 28
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bit_size: 1
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- name: DACEN
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description: DAC interface clock enable
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bit_offset: 29
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bit_size: 1
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fieldset/APB1LPENR:
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description: APB1 peripheral clock enable in low power mode register
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fields:
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- name: TIM2LPEN
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description: TIM2 clock enable during Sleep mode
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bit_offset: 0
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bit_size: 1
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- name: TIM3LPEN
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description: TIM3 clock enable during Sleep mode
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bit_offset: 1
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bit_size: 1
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- name: TIM4LPEN
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description: TIM4 clock enable during Sleep mode
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bit_offset: 2
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bit_size: 1
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- name: TIM5LPEN
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description: TIM5 clock enable during Sleep mode
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bit_offset: 3
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bit_size: 1
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- name: TIM6LPEN
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description: TIM6 clock enable during Sleep mode
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bit_offset: 4
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bit_size: 1
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- name: TIM7LPEN
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description: TIM7 clock enable during Sleep mode
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bit_offset: 5
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bit_size: 1
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- name: TIM12LPEN
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description: TIM12 clock enable during Sleep mode
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bit_offset: 6
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bit_size: 1
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- name: TIM13LPEN
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description: TIM13 clock enable during Sleep mode
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bit_offset: 7
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bit_size: 1
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- name: TIM14LPEN
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description: TIM14 clock enable during Sleep mode
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bit_offset: 8
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bit_size: 1
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- name: WWDGLPEN
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description: Window watchdog clock enable during Sleep mode
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bit_offset: 11
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bit_size: 1
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- name: SPI2LPEN
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description: SPI2 clock enable during Sleep mode
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bit_offset: 14
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bit_size: 1
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- name: SPI3LPEN
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description: SPI3 clock enable during Sleep mode
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bit_offset: 15
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bit_size: 1
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- name: USART2LPEN
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description: USART2 clock enable during Sleep mode
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bit_offset: 17
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bit_size: 1
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- name: USART3LPEN
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description: USART3 clock enable during Sleep mode
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bit_offset: 18
|
|
bit_size: 1
|
|
- name: UART4LPEN
|
|
description: UART4 clock enable during Sleep mode
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: UART5LPEN
|
|
description: UART5 clock enable during Sleep mode
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: I2C1LPEN
|
|
description: I2C1 clock enable during Sleep mode
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: I2C2LPEN
|
|
description: I2C2 clock enable during Sleep mode
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: I2C3LPEN
|
|
description: I2C3 clock enable during Sleep mode
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: CAN1LPEN
|
|
description: CAN 1 clock enable during Sleep mode
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: CAN2LPEN
|
|
description: CAN 2 clock enable during Sleep mode
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: PWRLPEN
|
|
description: Power interface clock enable during Sleep mode
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: DACLPEN
|
|
description: DAC interface clock enable during Sleep mode
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
fieldset/APB1RSTR:
|
|
description: APB1 peripheral reset register
|
|
fields:
|
|
- name: TIM2RST
|
|
description: TIM2 reset
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: TIM3RST
|
|
description: TIM3 reset
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: TIM4RST
|
|
description: TIM4 reset
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: TIM5RST
|
|
description: TIM5 reset
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: TIM6RST
|
|
description: TIM6 reset
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: TIM7RST
|
|
description: TIM7 reset
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: TIM12RST
|
|
description: TIM12 reset
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: TIM13RST
|
|
description: TIM13 reset
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: TIM14RST
|
|
description: TIM14 reset
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: WWDGRST
|
|
description: Window watchdog reset
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SPI2RST
|
|
description: SPI 2 reset
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: SPI3RST
|
|
description: SPI 3 reset
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: UART2RST
|
|
description: USART 2 reset
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: UART3RST
|
|
description: USART 3 reset
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: UART4RST
|
|
description: USART 4 reset
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: UART5RST
|
|
description: USART 5 reset
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: I2C1RST
|
|
description: I2C 1 reset
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: I2C2RST
|
|
description: I2C 2 reset
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: I2C3RST
|
|
description: I2C3 reset
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: CAN1RST
|
|
description: CAN1 reset
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: CAN2RST
|
|
description: CAN2 reset
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: PWRRST
|
|
description: Power interface reset
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: DACRST
|
|
description: DAC reset
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
fieldset/APB2ENR:
|
|
description: APB2 peripheral clock enable register
|
|
fields:
|
|
- name: TIM1EN
|
|
description: TIM1 clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: TIM8EN
|
|
description: TIM8 clock enable
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: USART1EN
|
|
description: USART1 clock enable
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: USART6EN
|
|
description: USART6 clock enable
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: ADC1EN
|
|
description: ADC1 clock enable
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: ADC2EN
|
|
description: ADC2 clock enable
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: ADC3EN
|
|
description: ADC3 clock enable
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: SDIOEN
|
|
description: SDIO clock enable
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SPI1EN
|
|
description: SPI1 clock enable
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: SYSCFGEN
|
|
description: System configuration controller clock enable
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: TIM9EN
|
|
description: TIM9 clock enable
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: TIM10EN
|
|
description: TIM10 clock enable
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TIM11EN
|
|
description: TIM11 clock enable
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
fieldset/APB2LPENR:
|
|
description: APB2 peripheral clock enabled in low power mode register
|
|
fields:
|
|
- name: TIM1LPEN
|
|
description: TIM1 clock enable during Sleep mode
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: TIM8LPEN
|
|
description: TIM8 clock enable during Sleep mode
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: USART1LPEN
|
|
description: USART1 clock enable during Sleep mode
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: USART6LPEN
|
|
description: USART6 clock enable during Sleep mode
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: ADC1LPEN
|
|
description: ADC1 clock enable during Sleep mode
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: ADC2LPEN
|
|
description: ADC2 clock enable during Sleep mode
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: ADC3LPEN
|
|
description: ADC 3 clock enable during Sleep mode
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: SDIOLPEN
|
|
description: SDIO clock enable during Sleep mode
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SPI1LPEN
|
|
description: SPI 1 clock enable during Sleep mode
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: SYSCFGLPEN
|
|
description: System configuration controller clock enable during Sleep mode
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: TIM9LPEN
|
|
description: TIM9 clock enable during sleep mode
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: TIM10LPEN
|
|
description: TIM10 clock enable during Sleep mode
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TIM11LPEN
|
|
description: TIM11 clock enable during Sleep mode
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
fieldset/APB2RSTR:
|
|
description: APB2 peripheral reset register
|
|
fields:
|
|
- name: TIM1RST
|
|
description: TIM1 reset
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: TIM8RST
|
|
description: TIM8 reset
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: USART1RST
|
|
description: USART1 reset
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: USART6RST
|
|
description: USART6 reset
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: ADCRST
|
|
description: ADC interface reset (common to all ADCs)
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: SDIORST
|
|
description: SDIO reset
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SPI1RST
|
|
description: SPI 1 reset
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: SYSCFGRST
|
|
description: System configuration controller reset
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: TIM9RST
|
|
description: TIM9 reset
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: TIM10RST
|
|
description: TIM10 reset
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TIM11RST
|
|
description: TIM11 reset
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
fieldset/BDCR:
|
|
description: Backup domain control register
|
|
fields:
|
|
- name: LSEON
|
|
description: External low-speed oscillator enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDY
|
|
description: External low-speed oscillator ready
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: LSEBYP
|
|
description: External low-speed oscillator bypass
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: RTCSEL
|
|
description: RTC clock source selection
|
|
bit_offset: 8
|
|
bit_size: 2
|
|
enum: RTCSEL
|
|
- name: RTCEN
|
|
description: RTC clock enable
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: BDRST
|
|
description: Backup domain software reset
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
fieldset/CFGR:
|
|
description: clock configuration register
|
|
fields:
|
|
- name: SW
|
|
description: System clock switch
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
enum: SW
|
|
- name: SWS
|
|
description: System clock switch status
|
|
bit_offset: 2
|
|
bit_size: 2
|
|
enum: SW
|
|
- name: HPRE
|
|
description: AHB prescaler
|
|
bit_offset: 4
|
|
bit_size: 4
|
|
enum: HPRE
|
|
- name: PPRE1
|
|
description: APB Low speed prescaler (APB1)
|
|
bit_offset: 10
|
|
bit_size: 3
|
|
enum: PPRE
|
|
- name: PPRE2
|
|
description: APB high-speed prescaler (APB2)
|
|
bit_offset: 13
|
|
bit_size: 3
|
|
enum: PPRE
|
|
- name: RTCPRE
|
|
description: HSE division factor for RTC clock
|
|
bit_offset: 16
|
|
bit_size: 5
|
|
- name: MCO1SEL
|
|
description: Microcontroller clock output 1
|
|
bit_offset: 21
|
|
bit_size: 2
|
|
enum: MCO1SEL
|
|
- name: I2SSRC
|
|
description: I2S clock selection
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
enum: ISSRC
|
|
- name: MCO1PRE
|
|
description: MCO1 prescaler
|
|
bit_offset: 24
|
|
bit_size: 3
|
|
enum: MCOPRE
|
|
- name: MCO2PRE
|
|
description: MCO2 prescaler
|
|
bit_offset: 27
|
|
bit_size: 3
|
|
enum: MCOPRE
|
|
- name: MCO2SEL
|
|
description: Microcontroller clock output 2
|
|
bit_offset: 30
|
|
bit_size: 2
|
|
enum: MCO2SEL
|
|
fieldset/CIR:
|
|
description: clock interrupt register
|
|
fields:
|
|
- name: LSIRDYF
|
|
description: LSI ready interrupt flag
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDYF
|
|
description: LSE ready interrupt flag
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: HSIRDYF
|
|
description: HSI ready interrupt flag
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: HSERDYF
|
|
description: HSE ready interrupt flag
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: PLLRDYF
|
|
description: Main PLL (PLL) ready interrupt flag
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: PLLI2SRDYF
|
|
description: PLLI2S ready interrupt flag
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: CSSF
|
|
description: Clock security system interrupt flag
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: LSIRDYIE
|
|
description: LSI ready interrupt enable
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: LSERDYIE
|
|
description: LSE ready interrupt enable
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: HSIRDYIE
|
|
description: HSI ready interrupt enable
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: HSERDYIE
|
|
description: HSE ready interrupt enable
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: PLLRDYIE
|
|
description: Main PLL (PLL) ready interrupt enable
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: PLLI2SRDYIE
|
|
description: PLLI2S ready interrupt enable
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: LSIRDYC
|
|
description: LSI ready interrupt clear
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: LSERDYC
|
|
description: LSE ready interrupt clear
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: HSIRDYC
|
|
description: HSI ready interrupt clear
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: HSERDYC
|
|
description: HSE ready interrupt clear
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: PLLRDYC
|
|
description: Main PLL(PLL) ready interrupt clear
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: PLLI2SRDYC
|
|
description: PLLI2S ready interrupt clear
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: CSSC
|
|
description: Clock security system interrupt clear
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
fieldset/CR:
|
|
description: clock control register
|
|
fields:
|
|
- name: HSION
|
|
description: Internal high-speed clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: HSIRDY
|
|
description: Internal high-speed clock ready flag
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: HSITRIM
|
|
description: Internal high-speed clock trimming
|
|
bit_offset: 3
|
|
bit_size: 5
|
|
- name: HSICAL
|
|
description: Internal high-speed clock calibration
|
|
bit_offset: 8
|
|
bit_size: 8
|
|
- name: HSEON
|
|
description: HSE clock enable
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: HSERDY
|
|
description: HSE clock ready flag
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: HSEBYP
|
|
description: HSE clock bypass
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: CSSON
|
|
description: Clock security system enable
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: PLLON
|
|
description: Main PLL (PLL) enable
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: PLLRDY
|
|
description: Main PLL (PLL) clock ready flag
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: PLLI2SON
|
|
description: PLLI2S enable
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: PLLI2SRDY
|
|
description: PLLI2S clock ready flag
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
fieldset/CSR:
|
|
description: clock control & status register
|
|
fields:
|
|
- name: LSION
|
|
description: Internal low-speed oscillator enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSIRDY
|
|
description: Internal low-speed oscillator ready
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: RMVF
|
|
description: Remove reset flag
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: BORRSTF
|
|
description: BOR reset flag
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: PADRSTF
|
|
description: PIN reset flag
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: PORRSTF
|
|
description: POR/PDR reset flag
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: SFTRSTF
|
|
description: Software reset flag
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: WDGRSTF
|
|
description: Independent watchdog reset flag
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
- name: WWDGRSTF
|
|
description: Window watchdog reset flag
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
- name: LPWRRSTF
|
|
description: Low-power reset flag
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/PLLCFGR:
|
|
description: PLL configuration register
|
|
fields:
|
|
- name: PLLM
|
|
description: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
|
|
bit_offset: 0
|
|
bit_size: 6
|
|
enum: PLLM
|
|
- name: PLLN
|
|
description: Main PLL (PLL) multiplication factor for VCO
|
|
bit_offset: 6
|
|
bit_size: 9
|
|
enum: PLLN
|
|
- name: PLLP
|
|
description: Main PLL (PLL) division factor for main system clock
|
|
bit_offset: 16
|
|
bit_size: 2
|
|
enum: PLLP
|
|
- name: PLLSRC
|
|
description: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
enum: PLLSRC
|
|
- name: PLLQ
|
|
description: Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
|
|
bit_offset: 24
|
|
bit_size: 4
|
|
enum: PLLQ
|
|
fieldset/PLLI2SCFGR:
|
|
description: PLLI2S configuration register
|
|
fields:
|
|
- name: PLLI2SN
|
|
description: PLLI2S multiplication factor for VCO
|
|
bit_offset: 6
|
|
bit_size: 9
|
|
- name: PLLI2SR
|
|
description: PLLI2S division factor for I2S clocks
|
|
bit_offset: 28
|
|
bit_size: 3
|
|
fieldset/SSCGR:
|
|
description: spread spectrum clock generation register
|
|
fields:
|
|
- name: MODPER
|
|
description: Modulation period
|
|
bit_offset: 0
|
|
bit_size: 13
|
|
- name: INCSTEP
|
|
description: Incrementation step
|
|
bit_offset: 13
|
|
bit_size: 15
|
|
- name: SPREADSEL
|
|
description: Spread Select
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: SPREADSEL
|
|
- name: SSCGEN
|
|
description: Spread spectrum modulation enable
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum/HPRE:
|
|
bit_size: 4
|
|
variants:
|
|
- name: Div1
|
|
description: SYSCLK not divided
|
|
value: 0
|
|
- name: Div2
|
|
description: SYSCLK divided by 2
|
|
value: 8
|
|
- name: Div4
|
|
description: SYSCLK divided by 4
|
|
value: 9
|
|
- name: Div8
|
|
description: SYSCLK divided by 8
|
|
value: 10
|
|
- name: Div16
|
|
description: SYSCLK divided by 16
|
|
value: 11
|
|
- name: Div64
|
|
description: SYSCLK divided by 64
|
|
value: 12
|
|
- name: Div128
|
|
description: SYSCLK divided by 128
|
|
value: 13
|
|
- name: Div256
|
|
description: SYSCLK divided by 256
|
|
value: 14
|
|
- name: Div512
|
|
description: SYSCLK divided by 512
|
|
value: 15
|
|
enum/ISSRC:
|
|
bit_size: 1
|
|
variants:
|
|
- name: PLLI2S
|
|
description: PLLI2S clock used as I2S clock source
|
|
value: 0
|
|
- name: CKIN
|
|
description: External clock mapped on the I2S_CKIN pin used as I2S clock source
|
|
value: 1
|
|
enum/MCO1SEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: HSI
|
|
description: HSI clock selected
|
|
value: 0
|
|
- name: LSE
|
|
description: LSE oscillator selected
|
|
value: 1
|
|
- name: HSE
|
|
description: HSE oscillator clock selected
|
|
value: 2
|
|
- name: PLL
|
|
description: PLL clock selected
|
|
value: 3
|
|
enum/MCO2SEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: SYSCLK
|
|
description: System clock (SYSCLK) selected
|
|
value: 0
|
|
- name: PLLI2S
|
|
description: PLLI2S clock selected
|
|
value: 1
|
|
- name: HSE
|
|
description: HSE oscillator clock selected
|
|
value: 2
|
|
- name: PLL
|
|
description: PLL clock selected
|
|
value: 3
|
|
enum/MCOPRE:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Div1
|
|
description: No division
|
|
value: 0
|
|
- name: Div2
|
|
description: Division by 2
|
|
value: 4
|
|
- name: Div3
|
|
description: Division by 3
|
|
value: 5
|
|
- name: Div4
|
|
description: Division by 4
|
|
value: 6
|
|
- name: Div5
|
|
description: Division by 5
|
|
value: 7
|
|
enum/PLLM:
|
|
bit_size: 6
|
|
variants:
|
|
- name: Div2
|
|
value: 2
|
|
- name: Div3
|
|
value: 3
|
|
- name: Div4
|
|
value: 4
|
|
- name: Div5
|
|
value: 5
|
|
- name: Div6
|
|
value: 6
|
|
- name: Div7
|
|
value: 7
|
|
- name: Div8
|
|
value: 8
|
|
- name: Div9
|
|
value: 9
|
|
- name: Div10
|
|
value: 10
|
|
- name: Div11
|
|
value: 11
|
|
- name: Div12
|
|
value: 12
|
|
- name: Div13
|
|
value: 13
|
|
- name: Div14
|
|
value: 14
|
|
- name: Div15
|
|
value: 15
|
|
- name: Div16
|
|
value: 16
|
|
- name: Div17
|
|
value: 17
|
|
- name: Div18
|
|
value: 18
|
|
- name: Div19
|
|
value: 19
|
|
- name: Div20
|
|
value: 20
|
|
- name: Div21
|
|
value: 21
|
|
- name: Div22
|
|
value: 22
|
|
- name: Div23
|
|
value: 23
|
|
- name: Div24
|
|
value: 24
|
|
- name: Div25
|
|
value: 25
|
|
- name: Div26
|
|
value: 26
|
|
- name: Div27
|
|
value: 27
|
|
- name: Div28
|
|
value: 28
|
|
- name: Div29
|
|
value: 29
|
|
- name: Div30
|
|
value: 30
|
|
- name: Div31
|
|
value: 31
|
|
- name: Div32
|
|
value: 32
|
|
- name: Div33
|
|
value: 33
|
|
- name: Div34
|
|
value: 34
|
|
- name: Div35
|
|
value: 35
|
|
- name: Div36
|
|
value: 36
|
|
- name: Div37
|
|
value: 37
|
|
- name: Div38
|
|
value: 38
|
|
- name: Div39
|
|
value: 39
|
|
- name: Div40
|
|
value: 40
|
|
- name: Div41
|
|
value: 41
|
|
- name: Div42
|
|
value: 42
|
|
- name: Div43
|
|
value: 43
|
|
- name: Div44
|
|
value: 44
|
|
- name: Div45
|
|
value: 45
|
|
- name: Div46
|
|
value: 46
|
|
- name: Div47
|
|
value: 47
|
|
- name: Div48
|
|
value: 48
|
|
- name: Div49
|
|
value: 49
|
|
- name: Div50
|
|
value: 50
|
|
- name: Div51
|
|
value: 51
|
|
- name: Div52
|
|
value: 52
|
|
- name: Div53
|
|
value: 53
|
|
- name: Div54
|
|
value: 54
|
|
- name: Div55
|
|
value: 55
|
|
- name: Div56
|
|
value: 56
|
|
- name: Div57
|
|
value: 57
|
|
- name: Div58
|
|
value: 58
|
|
- name: Div59
|
|
value: 59
|
|
- name: Div60
|
|
value: 60
|
|
- name: Div61
|
|
value: 61
|
|
- name: Div62
|
|
value: 62
|
|
- name: Div63
|
|
value: 63
|
|
enum/PLLN:
|
|
bit_size: 9
|
|
variants:
|
|
- name: Mul192
|
|
value: 192
|
|
- name: Mul193
|
|
value: 193
|
|
- name: Mul194
|
|
value: 194
|
|
- name: Mul195
|
|
value: 195
|
|
- name: Mul196
|
|
value: 196
|
|
- name: Mul197
|
|
value: 197
|
|
- name: Mul198
|
|
value: 198
|
|
- name: Mul199
|
|
value: 199
|
|
- name: Mul200
|
|
value: 200
|
|
- name: Mul201
|
|
value: 201
|
|
- name: Mul202
|
|
value: 202
|
|
- name: Mul203
|
|
value: 203
|
|
- name: Mul204
|
|
value: 204
|
|
- name: Mul205
|
|
value: 205
|
|
- name: Mul206
|
|
value: 206
|
|
- name: Mul207
|
|
value: 207
|
|
- name: Mul208
|
|
value: 208
|
|
- name: Mul209
|
|
value: 209
|
|
- name: Mul210
|
|
value: 210
|
|
- name: Mul211
|
|
value: 211
|
|
- name: Mul212
|
|
value: 212
|
|
- name: Mul213
|
|
value: 213
|
|
- name: Mul214
|
|
value: 214
|
|
- name: Mul215
|
|
value: 215
|
|
- name: Mul216
|
|
value: 216
|
|
- name: Mul217
|
|
value: 217
|
|
- name: Mul218
|
|
value: 218
|
|
- name: Mul219
|
|
value: 219
|
|
- name: Mul220
|
|
value: 220
|
|
- name: Mul221
|
|
value: 221
|
|
- name: Mul222
|
|
value: 222
|
|
- name: Mul223
|
|
value: 223
|
|
- name: Mul224
|
|
value: 224
|
|
- name: Mul225
|
|
value: 225
|
|
- name: Mul226
|
|
value: 226
|
|
- name: Mul227
|
|
value: 227
|
|
- name: Mul228
|
|
value: 228
|
|
- name: Mul229
|
|
value: 229
|
|
- name: Mul230
|
|
value: 230
|
|
- name: Mul231
|
|
value: 231
|
|
- name: Mul232
|
|
value: 232
|
|
- name: Mul233
|
|
value: 233
|
|
- name: Mul234
|
|
value: 234
|
|
- name: Mul235
|
|
value: 235
|
|
- name: Mul236
|
|
value: 236
|
|
- name: Mul237
|
|
value: 237
|
|
- name: Mul238
|
|
value: 238
|
|
- name: Mul239
|
|
value: 239
|
|
- name: Mul240
|
|
value: 240
|
|
- name: Mul241
|
|
value: 241
|
|
- name: Mul242
|
|
value: 242
|
|
- name: Mul243
|
|
value: 243
|
|
- name: Mul244
|
|
value: 244
|
|
- name: Mul245
|
|
value: 245
|
|
- name: Mul246
|
|
value: 246
|
|
- name: Mul247
|
|
value: 247
|
|
- name: Mul248
|
|
value: 248
|
|
- name: Mul249
|
|
value: 249
|
|
- name: Mul250
|
|
value: 250
|
|
- name: Mul251
|
|
value: 251
|
|
- name: Mul252
|
|
value: 252
|
|
- name: Mul253
|
|
value: 253
|
|
- name: Mul254
|
|
value: 254
|
|
- name: Mul255
|
|
value: 255
|
|
- name: Mul256
|
|
value: 256
|
|
- name: Mul257
|
|
value: 257
|
|
- name: Mul258
|
|
value: 258
|
|
- name: Mul259
|
|
value: 259
|
|
- name: Mul260
|
|
value: 260
|
|
- name: Mul261
|
|
value: 261
|
|
- name: Mul262
|
|
value: 262
|
|
- name: Mul263
|
|
value: 263
|
|
- name: Mul264
|
|
value: 264
|
|
- name: Mul265
|
|
value: 265
|
|
- name: Mul266
|
|
value: 266
|
|
- name: Mul267
|
|
value: 267
|
|
- name: Mul268
|
|
value: 268
|
|
- name: Mul269
|
|
value: 269
|
|
- name: Mul270
|
|
value: 270
|
|
- name: Mul271
|
|
value: 271
|
|
- name: Mul272
|
|
value: 272
|
|
- name: Mul273
|
|
value: 273
|
|
- name: Mul274
|
|
value: 274
|
|
- name: Mul275
|
|
value: 275
|
|
- name: Mul276
|
|
value: 276
|
|
- name: Mul277
|
|
value: 277
|
|
- name: Mul278
|
|
value: 278
|
|
- name: Mul279
|
|
value: 279
|
|
- name: Mul280
|
|
value: 280
|
|
- name: Mul281
|
|
value: 281
|
|
- name: Mul282
|
|
value: 282
|
|
- name: Mul283
|
|
value: 283
|
|
- name: Mul284
|
|
value: 284
|
|
- name: Mul285
|
|
value: 285
|
|
- name: Mul286
|
|
value: 286
|
|
- name: Mul287
|
|
value: 287
|
|
- name: Mul288
|
|
value: 288
|
|
- name: Mul289
|
|
value: 289
|
|
- name: Mul290
|
|
value: 290
|
|
- name: Mul291
|
|
value: 291
|
|
- name: Mul292
|
|
value: 292
|
|
- name: Mul293
|
|
value: 293
|
|
- name: Mul294
|
|
value: 294
|
|
- name: Mul295
|
|
value: 295
|
|
- name: Mul296
|
|
value: 296
|
|
- name: Mul297
|
|
value: 297
|
|
- name: Mul298
|
|
value: 298
|
|
- name: Mul299
|
|
value: 299
|
|
- name: Mul300
|
|
value: 300
|
|
- name: Mul301
|
|
value: 301
|
|
- name: Mul302
|
|
value: 302
|
|
- name: Mul303
|
|
value: 303
|
|
- name: Mul304
|
|
value: 304
|
|
- name: Mul305
|
|
value: 305
|
|
- name: Mul306
|
|
value: 306
|
|
- name: Mul307
|
|
value: 307
|
|
- name: Mul308
|
|
value: 308
|
|
- name: Mul309
|
|
value: 309
|
|
- name: Mul310
|
|
value: 310
|
|
- name: Mul311
|
|
value: 311
|
|
- name: Mul312
|
|
value: 312
|
|
- name: Mul313
|
|
value: 313
|
|
- name: Mul314
|
|
value: 314
|
|
- name: Mul315
|
|
value: 315
|
|
- name: Mul316
|
|
value: 316
|
|
- name: Mul317
|
|
value: 317
|
|
- name: Mul318
|
|
value: 318
|
|
- name: Mul319
|
|
value: 319
|
|
- name: Mul320
|
|
value: 320
|
|
- name: Mul321
|
|
value: 321
|
|
- name: Mul322
|
|
value: 322
|
|
- name: Mul323
|
|
value: 323
|
|
- name: Mul324
|
|
value: 324
|
|
- name: Mul325
|
|
value: 325
|
|
- name: Mul326
|
|
value: 326
|
|
- name: Mul327
|
|
value: 327
|
|
- name: Mul328
|
|
value: 328
|
|
- name: Mul329
|
|
value: 329
|
|
- name: Mul330
|
|
value: 330
|
|
- name: Mul331
|
|
value: 331
|
|
- name: Mul332
|
|
value: 332
|
|
- name: Mul333
|
|
value: 333
|
|
- name: Mul334
|
|
value: 334
|
|
- name: Mul335
|
|
value: 335
|
|
- name: Mul336
|
|
value: 336
|
|
- name: Mul337
|
|
value: 337
|
|
- name: Mul338
|
|
value: 338
|
|
- name: Mul339
|
|
value: 339
|
|
- name: Mul340
|
|
value: 340
|
|
- name: Mul341
|
|
value: 341
|
|
- name: Mul342
|
|
value: 342
|
|
- name: Mul343
|
|
value: 343
|
|
- name: Mul344
|
|
value: 344
|
|
- name: Mul345
|
|
value: 345
|
|
- name: Mul346
|
|
value: 346
|
|
- name: Mul347
|
|
value: 347
|
|
- name: Mul348
|
|
value: 348
|
|
- name: Mul349
|
|
value: 349
|
|
- name: Mul350
|
|
value: 350
|
|
- name: Mul351
|
|
value: 351
|
|
- name: Mul352
|
|
value: 352
|
|
- name: Mul353
|
|
value: 353
|
|
- name: Mul354
|
|
value: 354
|
|
- name: Mul355
|
|
value: 355
|
|
- name: Mul356
|
|
value: 356
|
|
- name: Mul357
|
|
value: 357
|
|
- name: Mul358
|
|
value: 358
|
|
- name: Mul359
|
|
value: 359
|
|
- name: Mul360
|
|
value: 360
|
|
- name: Mul361
|
|
value: 361
|
|
- name: Mul362
|
|
value: 362
|
|
- name: Mul363
|
|
value: 363
|
|
- name: Mul364
|
|
value: 364
|
|
- name: Mul365
|
|
value: 365
|
|
- name: Mul366
|
|
value: 366
|
|
- name: Mul367
|
|
value: 367
|
|
- name: Mul368
|
|
value: 368
|
|
- name: Mul369
|
|
value: 369
|
|
- name: Mul370
|
|
value: 370
|
|
- name: Mul371
|
|
value: 371
|
|
- name: Mul372
|
|
value: 372
|
|
- name: Mul373
|
|
value: 373
|
|
- name: Mul374
|
|
value: 374
|
|
- name: Mul375
|
|
value: 375
|
|
- name: Mul376
|
|
value: 376
|
|
- name: Mul377
|
|
value: 377
|
|
- name: Mul378
|
|
value: 378
|
|
- name: Mul379
|
|
value: 379
|
|
- name: Mul380
|
|
value: 380
|
|
- name: Mul381
|
|
value: 381
|
|
- name: Mul382
|
|
value: 382
|
|
- name: Mul383
|
|
value: 383
|
|
- name: Mul384
|
|
value: 384
|
|
- name: Mul385
|
|
value: 385
|
|
- name: Mul386
|
|
value: 386
|
|
- name: Mul387
|
|
value: 387
|
|
- name: Mul388
|
|
value: 388
|
|
- name: Mul389
|
|
value: 389
|
|
- name: Mul390
|
|
value: 390
|
|
- name: Mul391
|
|
value: 391
|
|
- name: Mul392
|
|
value: 392
|
|
- name: Mul393
|
|
value: 393
|
|
- name: Mul394
|
|
value: 394
|
|
- name: Mul395
|
|
value: 395
|
|
- name: Mul396
|
|
value: 396
|
|
- name: Mul397
|
|
value: 397
|
|
- name: Mul398
|
|
value: 398
|
|
- name: Mul399
|
|
value: 399
|
|
- name: Mul400
|
|
value: 400
|
|
- name: Mul401
|
|
value: 401
|
|
- name: Mul402
|
|
value: 402
|
|
- name: Mul403
|
|
value: 403
|
|
- name: Mul404
|
|
value: 404
|
|
- name: Mul405
|
|
value: 405
|
|
- name: Mul406
|
|
value: 406
|
|
- name: Mul407
|
|
value: 407
|
|
- name: Mul408
|
|
value: 408
|
|
- name: Mul409
|
|
value: 409
|
|
- name: Mul410
|
|
value: 410
|
|
- name: Mul411
|
|
value: 411
|
|
- name: Mul412
|
|
value: 412
|
|
- name: Mul413
|
|
value: 413
|
|
- name: Mul414
|
|
value: 414
|
|
- name: Mul415
|
|
value: 415
|
|
- name: Mul416
|
|
value: 416
|
|
- name: Mul417
|
|
value: 417
|
|
- name: Mul418
|
|
value: 418
|
|
- name: Mul419
|
|
value: 419
|
|
- name: Mul420
|
|
value: 420
|
|
- name: Mul421
|
|
value: 421
|
|
- name: Mul422
|
|
value: 422
|
|
- name: Mul423
|
|
value: 423
|
|
- name: Mul424
|
|
value: 424
|
|
- name: Mul425
|
|
value: 425
|
|
- name: Mul426
|
|
value: 426
|
|
- name: Mul427
|
|
value: 427
|
|
- name: Mul428
|
|
value: 428
|
|
- name: Mul429
|
|
value: 429
|
|
- name: Mul430
|
|
value: 430
|
|
- name: Mul431
|
|
value: 431
|
|
- name: Mul432
|
|
value: 432
|
|
enum/PLLP:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Div2
|
|
description: PLLP=2
|
|
value: 0
|
|
- name: Div4
|
|
description: PLLP=4
|
|
value: 1
|
|
- name: Div6
|
|
description: PLLP=6
|
|
value: 2
|
|
- name: Div8
|
|
description: PLLP=8
|
|
value: 3
|
|
enum/PLLQ:
|
|
bit_size: 4
|
|
variants:
|
|
- name: Div2
|
|
value: 2
|
|
- name: Div3
|
|
value: 3
|
|
- name: Div4
|
|
value: 4
|
|
- name: Div5
|
|
value: 5
|
|
- name: Div6
|
|
value: 6
|
|
- name: Div7
|
|
value: 7
|
|
- name: Div8
|
|
value: 8
|
|
- name: Div9
|
|
value: 9
|
|
- name: Div10
|
|
value: 10
|
|
- name: Div11
|
|
value: 11
|
|
- name: Div12
|
|
value: 12
|
|
- name: Div13
|
|
value: 13
|
|
- name: Div14
|
|
value: 14
|
|
- name: Div15
|
|
value: 15
|
|
enum/PLLSRC:
|
|
bit_size: 1
|
|
variants:
|
|
- name: HSI
|
|
description: HSI clock selected as PLL and PLLI2S clock entry
|
|
value: 0
|
|
- name: HSE
|
|
description: HSE oscillator clock selected as PLL and PLLI2S clock entry
|
|
value: 1
|
|
enum/PPRE:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Div1
|
|
description: HCLK not divided
|
|
value: 0
|
|
- name: Div2
|
|
description: HCLK divided by 2
|
|
value: 4
|
|
- name: Div4
|
|
description: HCLK divided by 4
|
|
value: 5
|
|
- name: Div8
|
|
description: HCLK divided by 8
|
|
value: 6
|
|
- name: Div16
|
|
description: HCLK divided by 16
|
|
value: 7
|
|
enum/RTCSEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: DISABLE
|
|
description: No clock
|
|
value: 0
|
|
- name: LSE
|
|
description: LSE oscillator clock used as RTC clock
|
|
value: 1
|
|
- name: LSI
|
|
description: LSI oscillator clock used as RTC clock
|
|
value: 2
|
|
- name: HSE
|
|
description: HSE oscillator clock divided by a prescaler used as RTC clock
|
|
value: 3
|
|
enum/SPREADSEL:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Center
|
|
description: Center spread
|
|
value: 0
|
|
- name: Down
|
|
description: Down spread
|
|
value: 1
|
|
enum/SW:
|
|
bit_size: 2
|
|
variants:
|
|
- name: HSI
|
|
description: HSI selected as system clock
|
|
value: 0
|
|
- name: HSE
|
|
description: HSE selected as system clock
|
|
value: 1
|
|
- name: PLL
|
|
description: PLL selected as system clock
|
|
value: 2
|