Generated from stm32-data bd6bc952a2503d43ce6af87b9ad6665388e0175b

data/chips/STM32U5A5AJ.json

@@ -8326,6 +8326,11 @@
                 {
                     "name": "USB_OTG_HS",
                     "address": 1107558400,
+                    "registers": {
+                        "kind": "otg",
+                        "version": "v2",
+                        "block": "OTG"
+                    },
                     "rcc": {
                         "bus_clock": "HCLK2",
                         "kernel_clock": {

data/chips/STM32U5A5QI.json

@@ -7672,6 +7672,11 @@
                 {
                     "name": "USB_OTG_HS",
                     "address": 1107558400,
+                    "registers": {
+                        "kind": "otg",
+                        "version": "v2",
+                        "block": "OTG"
+                    },
                     "rcc": {
                         "bus_clock": "HCLK2",
                         "kernel_clock": {

data/chips/STM32U5A5QJ.json

@@ -7766,6 +7766,11 @@
                 {
                     "name": "USB_OTG_HS",
                     "address": 1107558400,
+                    "registers": {
+                        "kind": "otg",
+                        "version": "v2",
+                        "block": "OTG"
+                    },
                     "rcc": {
                         "bus_clock": "HCLK2",
                         "kernel_clock": {

data/chips/STM32U5A5RJ.json

@@ -5764,6 +5764,11 @@
                 {
                     "name": "USB_OTG_HS",
                     "address": 1107558400,
+                    "registers": {
+                        "kind": "otg",
+                        "version": "v2",
+                        "block": "OTG"
+                    },
                     "rcc": {
                         "bus_clock": "HCLK2",
                         "kernel_clock": {

data/chips/STM32U5A5VJ.json

@@ -7121,6 +7121,11 @@
                 {
                     "name": "USB_OTG_HS",
                     "address": 1107558400,
+                    "registers": {
+                        "kind": "otg",
+                        "version": "v2",
+                        "block": "OTG"
+                    },
                     "rcc": {
                         "bus_clock": "HCLK2",
                         "kernel_clock": {

data/chips/STM32U5A5ZJ.json

@@ -7910,6 +7910,11 @@
                 {
                     "name": "USB_OTG_HS",
                     "address": 1107558400,
+                    "registers": {
+                        "kind": "otg",
+                        "version": "v2",
+                        "block": "OTG"
+                    },
                     "rcc": {
                         "bus_clock": "HCLK2",
                         "kernel_clock": {

data/chips/STM32U5A9BJ.json

@@ -8767,6 +8767,11 @@
                 {
                     "name": "USB_OTG_HS",
                     "address": 1107558400,
+                    "registers": {
+                        "kind": "otg",
+                        "version": "v2",
+                        "block": "OTG"
+                    },
                     "rcc": {
                         "bus_clock": "HCLK2",
                         "kernel_clock": {

data/chips/STM32U5A9NJ.json

@@ -8822,6 +8822,11 @@
                 {
                     "name": "USB_OTG_HS",
                     "address": 1107558400,
+                    "registers": {
+                        "kind": "otg",
+                        "version": "v2",
+                        "block": "OTG"
+                    },
                     "rcc": {
                         "bus_clock": "HCLK2",
                         "kernel_clock": {

data/chips/STM32U5A9VJ.json

@@ -7216,6 +7216,11 @@
                 {
                     "name": "USB_OTG_HS",
                     "address": 1107558400,
+                    "registers": {
+                        "kind": "otg",
+                        "version": "v2",
+                        "block": "OTG"
+                    },
                     "rcc": {
                         "bus_clock": "HCLK2",
                         "kernel_clock": {

data/chips/STM32U5A9ZJ.json

@@ -8184,6 +8184,11 @@
                 {
                     "name": "USB_OTG_HS",
                     "address": 1107558400,
+                    "registers": {
+                        "kind": "otg",
+                        "version": "v2",
+                        "block": "OTG"
+                    },
                     "rcc": {
                         "bus_clock": "HCLK2",
                         "kernel_clock": {

data/registers/otg_v2.json

@@ -1,5 +1,5 @@
 {
-  "block/OTG_HS": {
+  "block/OTG": {
     "description": "OTG_HS.",
     "items": [
       {
@@ -252,6 +252,16 @@
         "byte_offset": 2320,
         "fieldset": "DIEPTSIZ"
       },
+      {
+        "name": "DIEPDMA",
+        "description": "Device IN endpoint DMA address register",
+        "array": {
+          "len": 16,
+          "stride": 32
+        },
+        "byte_offset": 2324,
+        "fieldset": "DIEPDMA"
+      },
       {
         "name": "DTXFSTS",
         "description": "Device IN endpoint transmit FIFO status register",
@@ -373,7 +383,8 @@
         "name": "DSPD",
         "description": "Device speed",
         "bit_offset": 0,
-        "bit_size": 2
+        "bit_size": 2,
+        "enum": "DSPD"
       },
       {
         "name": "NZLSOHSK",
@@ -391,7 +402,8 @@
         "name": "PFIVL",
         "description": "PFIVL.",
         "bit_offset": 11,
-        "bit_size": 2
+        "bit_size": 2,
+        "enum": "PFIVL"
       },
       {
         "name": "ERRATIM",
@@ -481,6 +493,12 @@
         "bit_offset": 0,
         "bit_size": 11
       },
+      {
+        "name": "MPSIZ0",
+        "description": "MPSIZ for endpoint 0",
+        "bit_offset": 0,
+        "bit_size": 2
+      },
       {
         "name": "USBAEP",
         "description": "USBAEP",
@@ -503,7 +521,8 @@
         "name": "EPTYP",
         "description": "EPTYP",
         "bit_offset": 18,
-        "bit_size": 2
+        "bit_size": 2,
+        "enum": "EPTYP"
       },
       {
         "name": "SNPM",
@@ -561,6 +580,17 @@
       }
     ]
   },
+  "fieldset/DIEPDMA": {
+    "description": "OTG device OUT endpoint 0 DMA address register.",
+    "fields": [
+      {
+        "name": "DMAADDR",
+        "description": "DMAADDR.",
+        "bit_offset": 0,
+        "bit_size": 32
+      }
+    ]
+  },
   "fieldset/DIEPEMPMSK": {
     "description": "This register is used to control the IN endpoint FIFO empty interrupt generation (TXFE_DIEPINTx).",
     "fields": [
@@ -697,76 +727,107 @@
         "name": "XFRSIZ",
         "description": "XFRSIZ.",
         "bit_offset": 0,
-        "bit_size": 7
+        "bit_size": 19
       },
       {
         "name": "PKTCNT",
         "description": "PKTCNT.",
         "bit_offset": 19,
+        "bit_size": 10
+      },
+      {
+        "name": "MCNT",
+        "description": "Multi count",
+        "bit_offset": 29,
         "bit_size": 2
       }
     ]
   },
   "fieldset/DOEPCTL": {
-    "description": "This section describes the DOEPCTL0 register.",
+    "description": "Device endpoint control register",
     "fields": [
       {
         "name": "MPSIZ",
-        "description": "MPSIZ.",
+        "description": "MPSIZ",
+        "bit_offset": 0,
+        "bit_size": 11
+      },
+      {
+        "name": "MPSIZ0",
+        "description": "MPSIZ for endpoint 0",
         "bit_offset": 0,
         "bit_size": 2
       },
       {
         "name": "USBAEP",
-        "description": "USBAEP.",
+        "description": "USBAEP",
         "bit_offset": 15,
         "bit_size": 1
       },
+      {
+        "name": "EONUM_DPID",
+        "description": "EONUM/DPID",
+        "bit_offset": 16,
+        "bit_size": 1
+      },
       {
         "name": "NAKSTS",
-        "description": "NAKSTS.",
+        "description": "NAKSTS",
         "bit_offset": 17,
         "bit_size": 1
       },
       {
         "name": "EPTYP",
-        "description": "EPTYP.",
+        "description": "EPTYP",
         "bit_offset": 18,
-        "bit_size": 2
+        "bit_size": 2,
+        "enum": "EPTYP"
       },
       {
         "name": "SNPM",
-        "description": "SNPM.",
+        "description": "SNPM",
         "bit_offset": 20,
         "bit_size": 1
       },
       {
         "name": "STALL",
-        "description": "STALL.",
+        "description": "STALL",
         "bit_offset": 21,
         "bit_size": 1
       },
       {
         "name": "CNAK",
-        "description": "CNAK.",
+        "description": "CNAK",
         "bit_offset": 26,
         "bit_size": 1
       },
       {
         "name": "SNAK",
-        "description": "SNAK.",
+        "description": "SNAK",
         "bit_offset": 27,
         "bit_size": 1
       },
+      {
+        "name": "SD0PID_SEVNFRM",
+        "description": "SD0PID/SEVNFRM",
+        "bit_offset": 28,
+        "bit_size": 1
+      },
+      {
+        "name": "SODDFRM",
+        "description": "SODDFRM",
+        "bit_offset": 29,
+        "bit_size": 1
+      },
       {
         "name": "EPDIS",
-        "description": "EPDIS.",
+        "description": "EPDIS",
         "bit_offset": 30,
         "bit_size": 1
       },
       {
         "name": "EPENA",
-        "description": "EPENA.",
+        "description": "EPENA",
         "bit_offset": 31,
         "bit_size": 1
       }
@@ -944,19 +1005,25 @@
         "name": "XFRSIZ",
         "description": "XFRSIZ.",
         "bit_offset": 0,
-        "bit_size": 7
+        "bit_size": 19
       },
       {
         "name": "PKTCNT",
         "description": "PKTCNT.",
         "bit_offset": 19,
-        "bit_size": 1
+        "bit_size": 10
       },
       {
         "name": "STUPCNT",
         "description": "STUPCNT.",
         "bit_offset": 29,
         "bit_size": 2
+      },
+      {
+        "name": "RXDPID",
+        "description": "RXDPID.",
+        "bit_offset": 29,
+        "bit_size": 2
       }
     ]
   },
@@ -973,7 +1040,8 @@
         "name": "ENUMSPD",
         "description": "ENUMSPD.",
         "bit_offset": 1,
-        "bit_size": 2
+        "bit_size": 2,
+        "enum": "DSPD"
       },
       {
         "name": "EERR",
@@ -1106,6 +1174,18 @@
         "bit_offset": 0,
         "bit_size": 1
       },
+      {
+        "name": "HBSTLEN",
+        "description": "Burst length/type",
+        "bit_offset": 1,
+        "bit_size": 4
+      },
+      {
+        "name": "DMAEN",
+        "description": "DMA enable",
+        "bit_offset": 5,
+        "bit_size": 1
+      },
       {
         "name": "TXFELVL",
         "description": "TXFELVL.",
@@ -1910,7 +1990,8 @@
         "name": "PKTSTSD",
         "description": "Packet status (device mode)",
         "bit_offset": 17,
-        "bit_size": 4
+        "bit_size": 4,
+        "enum": "PKTSTSD"
       },
       {
         "name": "FRMNUM",
@@ -2252,5 +2333,101 @@
         "bit_size": 1
       }
     ]
+  },
+  "enum/DSPD": {
+    "bit_size": 2,
+    "variants": [
+      {
+        "name": "HIGH_SPEED",
+        "description": "High speed",
+        "value": 0
+      },
+      {
+        "name": "FULL_SPEED_EXTERNAL",
+        "description": "Full speed using external ULPI PHY",
+        "value": 1
+      },
+      {
+        "name": "FULL_SPEED_INTERNAL",
+        "description": "Full speed using internal embedded PHY",
+        "value": 3
+      }
+    ]
+  },
+  "enum/EPTYP": {
+    "bit_size": 2,
+    "variants": [
+      {
+        "name": "CONTROL",
+        "value": 0
+      },
+      {
+        "name": "ISOCHRONOUS",
+        "value": 1
+      },
+      {
+        "name": "BULK",
+        "value": 2
+      },
+      {
+        "name": "INTERRUPT",
+        "value": 3
+      }
+    ]
+  },
+  "enum/PFIVL": {
+    "bit_size": 2,
+    "variants": [
+      {
+        "name": "FRAME_INTERVAL_80",
+        "description": "80% of the frame interval",
+        "value": 0
+      },
+      {
+        "name": "FRAME_INTERVAL_85",
+        "description": "85% of the frame interval",
+        "value": 1
+      },
+      {
+        "name": "FRAME_INTERVAL_90",
+        "description": "90% of the frame interval",
+        "value": 2
+      },
+      {
+        "name": "FRAME_INTERVAL_95",
+        "description": "95% of the frame interval",
+        "value": 3
+      }
+    ]
+  },
+  "enum/PKTSTSD": {
+    "bit_size": 4,
+    "variants": [
+      {
+        "name": "OUT_NAK",
+        "description": "Global OUT NAK (triggers an interrupt)",
+        "value": 1
+      },
+      {
+        "name": "OUT_DATA_RX",
+        "description": "OUT data packet received",
+        "value": 2
+      },
+      {
+        "name": "OUT_DATA_DONE",
+        "description": "OUT transfer completed (triggers an interrupt)",
+        "value": 3
+      },
+      {
+        "name": "SETUP_DATA_DONE",
+        "description": "SETUP transaction completed (triggers an interrupt)",
+        "value": 4
+      },
+      {
+        "name": "SETUP_DATA_RX",
+        "description": "SETUP data packet received",
+        "value": 6
+      }
+    ]
   }
 }

stm32-metapac/src/chips/metadata_0751.rs

@@ -11897,7 +11897,14 @@
     Peripheral {
         name: "USB_OTG_HS",
         address: 0x42040000,
-        registers: None,
+        registers: Some(
+            PeripheralRegisters {
+                kind: "otg",
+                version: "v2",
+                block: "OTG",
+                ir: &otg::REGISTERS,
+            },
+        ),
         rcc: Some(
             PeripheralRcc {
                 bus_clock: "HCLK2",
@@ -12707,6 +12714,7 @@
 #[path="../registers/octospi_v1.rs"] pub mod octospi;
 #[path="../registers/octospim_v1.rs"] pub mod octospim;
 #[path="../registers/otfdec_v1.rs"] pub mod otfdec;
+#[path="../registers/otg_v2.rs"] pub mod otg;
 #[path="../registers/pka_v1b.rs"] pub mod pka;
 #[path="../registers/pssi_v1.rs"] pub mod pssi;
 #[path="../registers/pwr_u5.rs"] pub mod pwr;

stm32-metapac/src/chips/metadata_0752.rs

@@ -10987,7 +10987,14 @@
     Peripheral {
         name: "USB_OTG_HS",
         address: 0x42040000,
-        registers: None,
+        registers: Some(
+            PeripheralRegisters {
+                kind: "otg",
+                version: "v2",
+                block: "OTG",
+                ir: &otg::REGISTERS,
+            },
+        ),
         rcc: Some(
             PeripheralRcc {
                 bus_clock: "HCLK2",
@@ -11797,6 +11804,7 @@
 #[path="../registers/octospi_v1.rs"] pub mod octospi;
 #[path="../registers/octospim_v1.rs"] pub mod octospim;
 #[path="../registers/otfdec_v1.rs"] pub mod otfdec;
+#[path="../registers/otg_v2.rs"] pub mod otg;
 #[path="../registers/pka_v1b.rs"] pub mod pka;
 #[path="../registers/pssi_v1.rs"] pub mod pssi;
 #[path="../registers/pwr_u5.rs"] pub mod pwr;

stm32-metapac/src/chips/metadata_0753.rs

@@ -11113,7 +11113,14 @@
     Peripheral {
         name: "USB_OTG_HS",
         address: 0x42040000,
-        registers: None,
+        registers: Some(
+            PeripheralRegisters {
+                kind: "otg",
+                version: "v2",
+                block: "OTG",
+                ir: &otg::REGISTERS,
+            },
+        ),
         rcc: Some(
             PeripheralRcc {
                 bus_clock: "HCLK2",
@@ -11923,6 +11930,7 @@
 #[path="../registers/octospi_v1.rs"] pub mod octospi;
 #[path="../registers/octospim_v1.rs"] pub mod octospim;
 #[path="../registers/otfdec_v1.rs"] pub mod otfdec;
+#[path="../registers/otg_v2.rs"] pub mod otg;
 #[path="../registers/pka_v1b.rs"] pub mod pka;
 #[path="../registers/pssi_v1.rs"] pub mod pssi;
 #[path="../registers/pwr_u5.rs"] pub mod pwr;

stm32-metapac/src/chips/metadata_0754.rs

@@ -8321,7 +8321,14 @@
     Peripheral {
         name: "USB_OTG_HS",
         address: 0x42040000,
-        registers: None,
+        registers: Some(
+            PeripheralRegisters {
+                kind: "otg",
+                version: "v2",
+                block: "OTG",
+                ir: &otg::REGISTERS,
+            },
+        ),
         rcc: Some(
             PeripheralRcc {
                 bus_clock: "HCLK2",
@@ -9131,6 +9138,7 @@
 #[path="../registers/octospi_v1.rs"] pub mod octospi;
 #[path="../registers/octospim_v1.rs"] pub mod octospim;
 #[path="../registers/otfdec_v1.rs"] pub mod otfdec;
+#[path="../registers/otg_v2.rs"] pub mod otg;
 #[path="../registers/pka_v1b.rs"] pub mod pka;
 #[path="../registers/pssi_v1.rs"] pub mod pssi;
 #[path="../registers/pwr_u5.rs"] pub mod pwr;

stm32-metapac/src/chips/metadata_0755.rs

@@ -10213,7 +10213,14 @@
     Peripheral {
         name: "USB_OTG_HS",
         address: 0x42040000,
-        registers: None,
+        registers: Some(
+            PeripheralRegisters {
+                kind: "otg",
+                version: "v2",
+                block: "OTG",
+                ir: &otg::REGISTERS,
+            },
+        ),
         rcc: Some(
             PeripheralRcc {
                 bus_clock: "HCLK2",
@@ -11023,6 +11030,7 @@
 #[path="../registers/octospi_v1.rs"] pub mod octospi;
 #[path="../registers/octospim_v1.rs"] pub mod octospim;
 #[path="../registers/otfdec_v1.rs"] pub mod otfdec;
+#[path="../registers/otg_v2.rs"] pub mod otg;
 #[path="../registers/pka_v1b.rs"] pub mod pka;
 #[path="../registers/pssi_v1.rs"] pub mod pssi;
 #[path="../registers/pwr_u5.rs"] pub mod pwr;

stm32-metapac/src/chips/metadata_0756.rs

@@ -11309,7 +11309,14 @@
     Peripheral {
         name: "USB_OTG_HS",
         address: 0x42040000,
-        registers: None,
+        registers: Some(
+            PeripheralRegisters {
+                kind: "otg",
+                version: "v2",
+                block: "OTG",
+                ir: &otg::REGISTERS,
+            },
+        ),
         rcc: Some(
             PeripheralRcc {
                 bus_clock: "HCLK2",
@@ -12119,6 +12126,7 @@
 #[path="../registers/octospi_v1.rs"] pub mod octospi;
 #[path="../registers/octospim_v1.rs"] pub mod octospim;
 #[path="../registers/otfdec_v1.rs"] pub mod otfdec;
+#[path="../registers/otg_v2.rs"] pub mod otg;
 #[path="../registers/pka_v1b.rs"] pub mod pka;
 #[path="../registers/pssi_v1.rs"] pub mod pssi;
 #[path="../registers/pwr_u5.rs"] pub mod pwr;

stm32-metapac/src/chips/metadata_0757.rs

@@ -12529,7 +12529,14 @@
     Peripheral {
         name: "USB_OTG_HS",
         address: 0x42040000,
-        registers: None,
+        registers: Some(
+            PeripheralRegisters {
+                kind: "otg",
+                version: "v2",
+                block: "OTG",
+                ir: &otg::REGISTERS,
+            },
+        ),
         rcc: Some(
             PeripheralRcc {
                 bus_clock: "HCLK2",
@@ -13369,6 +13376,7 @@
 #[path="../registers/octospi_v1.rs"] pub mod octospi;
 #[path="../registers/octospim_v1.rs"] pub mod octospim;
 #[path="../registers/otfdec_v1.rs"] pub mod otfdec;
+#[path="../registers/otg_v2.rs"] pub mod otg;
 #[path="../registers/pka_v1b.rs"] pub mod pka;
 #[path="../registers/pssi_v1.rs"] pub mod pssi;
 #[path="../registers/pwr_u5.rs"] pub mod pwr;

stm32-metapac/src/chips/metadata_0758.rs

@@ -12606,7 +12606,14 @@
     Peripheral {
         name: "USB_OTG_HS",
         address: 0x42040000,
-        registers: None,
+        registers: Some(
+            PeripheralRegisters {
+                kind: "otg",
+                version: "v2",
+                block: "OTG",
+                ir: &otg::REGISTERS,
+            },
+        ),
         rcc: Some(
             PeripheralRcc {
                 bus_clock: "HCLK2",
@@ -13446,6 +13453,7 @@
 #[path="../registers/octospi_v1.rs"] pub mod octospi;
 #[path="../registers/octospim_v1.rs"] pub mod octospim;
 #[path="../registers/otfdec_v1.rs"] pub mod otfdec;
+#[path="../registers/otg_v2.rs"] pub mod otg;
 #[path="../registers/pka_v1b.rs"] pub mod pka;
 #[path="../registers/pssi_v1.rs"] pub mod pssi;
 #[path="../registers/pwr_u5.rs"] pub mod pwr;

stm32-metapac/src/chips/metadata_0759.rs

@@ -10367,7 +10367,14 @@
     Peripheral {
         name: "USB_OTG_HS",
         address: 0x42040000,
-        registers: None,
+        registers: Some(
+            PeripheralRegisters {
+                kind: "otg",
+                version: "v2",
+                block: "OTG",
+                ir: &otg::REGISTERS,
+            },
+        ),
         rcc: Some(
             PeripheralRcc {
                 bus_clock: "HCLK2",
@@ -11207,6 +11214,7 @@
 #[path="../registers/octospi_v1.rs"] pub mod octospi;
 #[path="../registers/octospim_v1.rs"] pub mod octospim;
 #[path="../registers/otfdec_v1.rs"] pub mod otfdec;
+#[path="../registers/otg_v2.rs"] pub mod otg;
 #[path="../registers/pka_v1b.rs"] pub mod pka;
 #[path="../registers/pssi_v1.rs"] pub mod pssi;
 #[path="../registers/pwr_u5.rs"] pub mod pwr;

stm32-metapac/src/chips/metadata_0760.rs

@@ -11707,7 +11707,14 @@
     Peripheral {
         name: "USB_OTG_HS",
         address: 0x42040000,
-        registers: None,
+        registers: Some(
+            PeripheralRegisters {
+                kind: "otg",
+                version: "v2",
+                block: "OTG",
+                ir: &otg::REGISTERS,
+            },
+        ),
         rcc: Some(
             PeripheralRcc {
                 bus_clock: "HCLK2",
@@ -12547,6 +12554,7 @@
 #[path="../registers/octospi_v1.rs"] pub mod octospi;
 #[path="../registers/octospim_v1.rs"] pub mod octospim;
 #[path="../registers/otfdec_v1.rs"] pub mod otfdec;
+#[path="../registers/otg_v2.rs"] pub mod otg;
 #[path="../registers/pka_v1b.rs"] pub mod pka;
 #[path="../registers/pssi_v1.rs"] pub mod pssi;
 #[path="../registers/pwr_u5.rs"] pub mod pwr;