#include typedef struct { uint32_t start : 1; // 0 Start uint32_t susp : 1; // 1 Suspend uint32_t abort : 1; // 2 Abort uint32_t reserve0 : 3; // 3 Reserve uint32_t lom : 1; // 6 Line Offset Mode uint32_t reserve1 : 1; // 7 Reserve uint32_t teie : 1; // 8 Transfer error interrupt enable uint32_t tcie : 1; // 9 Transfer complete interrupt enable uint32_t twie : 1; // 10 Transfer watermark interrupt enable uint32_t caeie : 1; // 11 CLUT access error interrupt enable uint32_t ctcie : 1; // 12 CLUT transfer complete interrupt enable uint32_t ceie : 1; // 13 Configuration Error Interrupt Enable uint32_t reserve2 : 2; // 14 Reserve uint32_t mode : 2; // 16 DMA2D mode uint32_t reserve3 : 14; // 18 Reserve } reg_sec_dma2d_cr_t; typedef struct { uint32_t teif : 1; // 0 Transfer error interrupt flag uint32_t tcif : 1; // 1 Transfer complete interrupt flag uint32_t twif : 1; // 2 Transfer watermark interrupt flag uint32_t caeif : 1; // 3 CLUT access error interrupt flag uint32_t ctcif : 1; // 4 CLUT transfer complete interrupt flag uint32_t ceif : 1; // 5 Configuration error interrupt flag uint32_t reserve0 : 26; // 6 Reserve } reg_sec_dma2d_isr_t; typedef struct { uint32_t cteif : 1; // 0 Clear Transfer error interrupt flag uint32_t ctcif : 1; // 1 Clear transfer complete interrupt flag uint32_t ctwif : 1; // 2 Clear transfer watermark interrupt flag uint32_t caecif : 1; // 3 Clear CLUT access error interrupt flag uint32_t cctcif : 1; // 4 Clear CLUT transfer complete interrupt flag uint32_t cceif : 1; // 5 Clear configuration error interrupt flag uint32_t reserve0 : 26; // 6 Reserve } reg_sec_dma2d_ifcr_t; typedef struct { uint32_t ma : 32; // 0 Memory address } reg_sec_dma2d_fgmar_t; typedef struct { uint32_t lo : 16; // 0 Line offset uint32_t reserve0 : 16; // 16 Reserve } reg_sec_dma2d_fgor_t; typedef struct { uint32_t ma : 32; // 0 Memory address } reg_sec_dma2d_bgmar_t; typedef struct { uint32_t lo : 16; // 0 Line offset uint32_t reserve0 : 16; // 16 Reserve } reg_sec_dma2d_bgor_t; typedef struct { uint32_t cm : 4; // 0 Color mode uint32_t ccm : 1; // 4 CLUT color mode uint32_t start : 1; // 5 Start uint32_t reserve0 : 2; // 6 Reserve uint32_t cs : 8; // 8 CLUT size uint32_t am : 2; // 16 Alpha mode uint32_t reserve1 : 2; // 18 Reserve uint32_t ai : 1; // 20 Alpha Inverted uint32_t rbs : 1; // 21 Red Blue Swap uint32_t reserve2 : 2; // 22 Reserve uint32_t alpha : 8; // 24 Alpha value } reg_sec_dma2d_fgpfccr_t; typedef struct { uint32_t blue : 8; // 0 Blue Value uint32_t green : 8; // 8 Green Value uint32_t red : 8; // 16 Red Value uint32_t reserve0 : 8; // 24 Reserve } reg_sec_dma2d_fgcolr_t; typedef struct { uint32_t cm : 4; // 0 Color mode uint32_t ccm : 1; // 4 CLUT Color mode uint32_t start : 1; // 5 Start uint32_t reserve0 : 2; // 6 Reserve uint32_t cs : 8; // 8 CLUT size uint32_t am : 2; // 16 Alpha mode uint32_t reserve1 : 2; // 18 Reserve uint32_t ai : 1; // 20 Alpha Inverted uint32_t rbs : 1; // 21 Red Blue Swap uint32_t reserve2 : 2; // 22 Reserve uint32_t alpha : 8; // 24 Alpha value } reg_sec_dma2d_bgpfccr_t; typedef struct { uint32_t blue : 8; // 0 Blue Value uint32_t green : 8; // 8 Green Value uint32_t red : 8; // 16 Red Value uint32_t reserve0 : 8; // 24 Reserve } reg_sec_dma2d_bgcolr_t; typedef struct { uint32_t ma : 32; // 0 Memory Address } reg_sec_dma2d_fgcmar_t; typedef struct { uint32_t ma : 32; // 0 Memory address } reg_sec_dma2d_bgcmar_t; typedef struct { uint32_t cm : 3; // 0 Color mode uint32_t reserve0 : 6; // 3 Reserve uint32_t sb : 1; // 9 Swap Bytes uint32_t reserve1 : 10; // 10 Reserve uint32_t ai : 1; // 20 Alpha Inverted uint32_t rbs : 1; // 21 Red Blue Swap uint32_t reserve2 : 10; // 22 Reserve } reg_sec_dma2d_opfccr_t; typedef struct { uint32_t blue : 8; // 0 Blue Value uint32_t green : 8; // 8 Green Value uint32_t red : 8; // 16 Red Value uint32_t aplha : 8; // 24 Alpha Channel Value } reg_sec_dma2d_ocolr_rgb888_t; typedef struct { uint32_t blue : 5; // 0 Blue value in RGB565 mode uint32_t green : 6; // 5 Green value in RGB565 mode uint32_t red : 5; // 11 Red value in RGB565 mode uint32_t reserve0 : 16; // 16 Reserve } reg_sec_dma2d_ocolr_rgb565_t; typedef struct { uint32_t blue : 5; // 0 Blue value in ARGB1555 mode uint32_t green : 5; // 5 Green value in ARGB1555 mode uint32_t red : 5; // 10 Red value in ARGB1555 mode uint32_t a : 1; // 15 Alpha channel value in ARGB1555 mode uint32_t reserve0 : 16; // 16 Reserve } reg_sec_dma2d_ocolr_argb1555_t; typedef struct { uint32_t blue : 4; // 0 Blue value in ARGB4444 mode uint32_t green : 4; // 4 Green value in ARGB4444 mode uint32_t red : 4; // 8 Red value in ARGB4444 mode uint32_t alpha : 4; // 12 Alpha channel value in ARGB4444 uint32_t reserve0 : 16; // 16 Reserve } reg_sec_dma2d_ocolr_argb4444_t; typedef struct { uint32_t ma : 32; // 0 Memory Address } reg_sec_dma2d_omar_t; typedef struct { uint32_t lo : 16; // 0 Line Offset uint32_t reserve0 : 16; // 16 Reserve } reg_sec_dma2d_oor_t; typedef struct { uint32_t nl : 16; // 0 Number of lines uint32_t pl : 14; // 16 Pixel per lines uint32_t reserve0 : 2; // 30 Reserve } reg_sec_dma2d_nlr_t; typedef struct { uint32_t lw : 16; // 0 Line watermark uint32_t reserve0 : 16; // 16 Reserve } reg_sec_dma2d_lwr_t; typedef struct { uint32_t en : 1; // 0 Enable uint32_t reserve0 : 7; // 1 Reserve uint32_t dt : 8; // 8 Dead Time uint32_t reserve1 : 16; // 16 Reserve } reg_sec_dma2d_amtcr_t; typedef struct { uint32_t blue : 8; // 0 BLUE uint32_t green : 8; // 8 GREEN uint32_t red : 8; // 16 RED uint32_t aplha : 8; // 24 APLHA } reg_sec_dma2d_fgclut_t; typedef struct { uint32_t blue : 8; // 0 BLUE uint32_t green : 8; // 8 GREEN uint32_t red : 8; // 16 RED uint32_t aplha : 8; // 24 APLHA } reg_sec_dma2d_bgclut_t; typedef struct { volatile reg_sec_dma2d_cr_t cr; volatile reg_sec_dma2d_isr_t isr; volatile reg_sec_dma2d_ifcr_t ifcr; volatile reg_sec_dma2d_fgmar_t fgmar; volatile reg_sec_dma2d_fgor_t fgor; volatile reg_sec_dma2d_bgmar_t bgmar; volatile reg_sec_dma2d_bgor_t bgor; volatile reg_sec_dma2d_fgpfccr_t fgpfccr; volatile reg_sec_dma2d_fgcolr_t fgcolr; volatile reg_sec_dma2d_bgpfccr_t bgpfccr; volatile reg_sec_dma2d_bgcolr_t bgcolr; volatile reg_sec_dma2d_fgcmar_t fgcmar; volatile reg_sec_dma2d_bgcmar_t bgcmar; volatile reg_sec_dma2d_opfccr_t opfccr; volatile reg_sec_dma2d_ocolr_rgb888_t ocolr_rgb888; volatile uint32_t reserve0[-1]; volatile reg_sec_dma2d_ocolr_rgb565_t ocolr_rgb565; volatile uint32_t reserve1[-1]; volatile reg_sec_dma2d_ocolr_argb1555_t ocolr_argb1555; volatile uint32_t reserve2[-1]; volatile reg_sec_dma2d_ocolr_argb4444_t ocolr_argb4444; volatile reg_sec_dma2d_omar_t omar; volatile reg_sec_dma2d_oor_t oor; volatile reg_sec_dma2d_nlr_t nlr; volatile reg_sec_dma2d_lwr_t lwr; volatile reg_sec_dma2d_amtcr_t amtcr; volatile uint32_t reserve3[236]; volatile reg_sec_dma2d_fgclut_t fgclut; volatile uint32_t reserve4[255]; volatile reg_sec_dma2d_bgclut_t bgclut; } reg_sec_dma2d_t;