#include typedef struct { uint32_t rt0 : 1; // 0 Rising trigger event configuration bit of configurable event input x uint32_t rt1 : 1; // 1 Rising trigger event configuration bit of configurable event input x uint32_t rt2 : 1; // 2 Rising trigger event configuration bit of configurable event input x uint32_t rt3 : 1; // 3 Rising trigger event configuration bit of configurable event input x uint32_t rt4 : 1; // 4 Rising trigger event configuration bit of configurable event input x uint32_t rt5 : 1; // 5 Rising trigger event configuration bit of configurable event input x uint32_t rt6 : 1; // 6 Rising trigger event configuration bit of configurable event input x uint32_t rt7 : 1; // 7 Rising trigger event configuration bit of configurable event input x uint32_t rt8 : 1; // 8 Rising trigger event configuration bit of configurable event input x uint32_t rt9 : 1; // 9 Rising trigger event configuration bit of configurable event input x uint32_t rt10 : 1; // 10 Rising trigger event configuration bit of configurable event input x uint32_t rt11 : 1; // 11 Rising trigger event configuration bit of configurable event input x uint32_t rt12 : 1; // 12 Rising trigger event configuration bit of configurable event input x uint32_t rt13 : 1; // 13 Rising trigger event configuration bit of configurable event input x uint32_t rt14 : 1; // 14 Rising trigger event configuration bit of configurable event input x uint32_t rt15 : 1; // 15 Rising trigger event configuration bit of configurable event input x uint32_t rt16 : 1; // 16 Rising trigger event configuration bit of configurable event input x uint32_t rt17 : 1; // 17 Rising trigger event configuration bit of configurable event input x uint32_t rt18 : 1; // 18 Rising trigger event configuration bit of configurable event input x uint32_t rt19 : 1; // 19 Rising trigger event configuration bit of configurable event input x uint32_t rt20 : 1; // 20 Rising trigger event configuration bit of configurable event input x uint32_t rt21 : 1; // 21 Rising trigger event configuration bit of configurable event input x uint32_t rt22 : 1; // 22 Rising trigger event configuration bit of configurable event input x uint32_t reserve0 : 9; // 23 Reserve } reg_exti_rtsr1_t; typedef struct { uint32_t ft0 : 1; // 0 Falling trigger event configuration bit of configurable event input x uint32_t ft1 : 1; // 1 Falling trigger event configuration bit of configurable event input x uint32_t ft2 : 1; // 2 Falling trigger event configuration bit of configurable event input x uint32_t ft3 : 1; // 3 Falling trigger event configuration bit of configurable event input x uint32_t ft4 : 1; // 4 Falling trigger event configuration bit of configurable event input x uint32_t ft5 : 1; // 5 Falling trigger event configuration bit of configurable event input x uint32_t ft6 : 1; // 6 Falling trigger event configuration bit of configurable event input x uint32_t ft7 : 1; // 7 Falling trigger event configuration bit of configurable event input x uint32_t ft8 : 1; // 8 Falling trigger event configuration bit of configurable event input x uint32_t ft9 : 1; // 9 Falling trigger event configuration bit of configurable event input x uint32_t ft10 : 1; // 10 Falling trigger event configuration bit of configurable event input x uint32_t ft11 : 1; // 11 Falling trigger event configuration bit of configurable event input x uint32_t ft12 : 1; // 12 Falling trigger event configuration bit of configurable event input x uint32_t ft13 : 1; // 13 Falling trigger event configuration bit of configurable event input x uint32_t ft14 : 1; // 14 Falling trigger event configuration bit of configurable event input x uint32_t ft15 : 1; // 15 Falling trigger event configuration bit of configurable event input x uint32_t ft16 : 1; // 16 Falling trigger event configuration bit of configurable event input x uint32_t ft17 : 1; // 17 Falling trigger event configuration bit of configurable event input x uint32_t ft18 : 1; // 18 Falling trigger event configuration bit of configurable event input x uint32_t ft19 : 1; // 19 Falling trigger event configuration bit of configurable event input x uint32_t ft20 : 1; // 20 Falling trigger event configuration bit of configurable event input x uint32_t ft21 : 1; // 21 Falling trigger event configuration bit of configurable event input x uint32_t ft22 : 1; // 22 Falling trigger event configuration bit of configurable event input x uint32_t reserve0 : 9; // 23 Reserve } reg_exti_ftsr1_t; typedef struct { uint32_t swi0 : 1; // 0 Software interrupt on event x uint32_t swi1 : 1; // 1 Software interrupt on event x uint32_t swi2 : 1; // 2 Software interrupt on event x uint32_t swi3 : 1; // 3 Software interrupt on event x uint32_t swi4 : 1; // 4 Software interrupt on event x uint32_t swi5 : 1; // 5 Software interrupt on event x uint32_t swi6 : 1; // 6 Software interrupt on event x uint32_t swi7 : 1; // 7 Software interrupt on event x uint32_t swi8 : 1; // 8 Software interrupt on event x uint32_t swi9 : 1; // 9 Software interrupt on event x uint32_t swi10 : 1; // 10 Software interrupt on event x uint32_t swi11 : 1; // 11 Software interrupt on event x uint32_t swi12 : 1; // 12 Software interrupt on event x uint32_t swi13 : 1; // 13 Software interrupt on event x uint32_t swi14 : 1; // 14 Software interrupt on event x uint32_t swi15 : 1; // 15 Software interrupt on event x uint32_t swi16 : 1; // 16 Software interrupt on event x uint32_t swi17 : 1; // 17 Software interrupt on event x uint32_t swi18 : 1; // 18 Software interrupt on event x uint32_t swi19 : 1; // 19 Software interrupt on event x uint32_t swi20 : 1; // 20 Software interrupt on event x uint32_t swi21 : 1; // 21 Software interrupt on event x uint32_t swi22 : 1; // 22 Software interrupt on event x uint32_t reserve0 : 9; // 23 Reserve } reg_exti_swier1_t; typedef struct { uint32_t rpif0 : 1; // 0 configurable event inputs x rising edge pending bit uint32_t rpif1 : 1; // 1 configurable event inputs x rising edge pending bit uint32_t rpif2 : 1; // 2 configurable event inputs x rising edge pending bit uint32_t rpif3 : 1; // 3 configurable event inputs x rising edge pending bit uint32_t rpif4 : 1; // 4 configurable event inputs x rising edge pending bit uint32_t rpif5 : 1; // 5 configurable event inputs x rising edge pending bit uint32_t rpif6 : 1; // 6 configurable event inputs x rising edge pending bit uint32_t rpif7 : 1; // 7 configurable event inputs x rising edge pending bit uint32_t rpif8 : 1; // 8 configurable event inputs x rising edge pending bit uint32_t rpif9 : 1; // 9 configurable event inputs x rising edge pending bit uint32_t rpif10 : 1; // 10 configurable event inputs x rising edge pending bit uint32_t rpif11 : 1; // 11 configurable event inputs x rising edge pending bit uint32_t rpif12 : 1; // 12 configurable event inputs x rising edge pending bit uint32_t rpif13 : 1; // 13 configurable event inputs x rising edge pending bit uint32_t rpif14 : 1; // 14 configurable event inputs x rising edge pending bit uint32_t rpif15 : 1; // 15 configurable event inputs x rising edge pending bit uint32_t rpif16 : 1; // 16 configurable event inputs x rising edge pending bit uint32_t rpif17 : 1; // 17 configurable event inputs x rising edge pending bit uint32_t rpif18 : 1; // 18 configurable event inputs x rising edge pending bit uint32_t rpif19 : 1; // 19 configurable event inputs x rising edge pending bit uint32_t rpif20 : 1; // 20 configurable event inputs x rising edge pending bit uint32_t rpif21 : 1; // 21 configurable event inputs x rising edge pending bit uint32_t rpif22 : 1; // 22 configurable event inputs x rising edge pending bit uint32_t reserve0 : 9; // 23 Reserve } reg_exti_rpr1_t; typedef struct { uint32_t fpif0 : 1; // 0 configurable event inputs x falling edge pending bit. uint32_t fpif1 : 1; // 1 configurable event inputs x falling edge pending bit. uint32_t fpif2 : 1; // 2 configurable event inputs x falling edge pending bit. uint32_t fpif3 : 1; // 3 configurable event inputs x falling edge pending bit. uint32_t fpif4 : 1; // 4 configurable event inputs x falling edge pending bit. uint32_t fpif5 : 1; // 5 configurable event inputs x falling edge pending bit. uint32_t fpif6 : 1; // 6 configurable event inputs x falling edge pending bit. uint32_t fpif7 : 1; // 7 configurable event inputs x falling edge pending bit. uint32_t fpif8 : 1; // 8 configurable event inputs x falling edge pending bit. uint32_t fpif9 : 1; // 9 configurable event inputs x falling edge pending bit. uint32_t fpif10 : 1; // 10 configurable event inputs x falling edge pending bit. uint32_t fpif11 : 1; // 11 configurable event inputs x falling edge pending bit. uint32_t fpif12 : 1; // 12 configurable event inputs x falling edge pending bit. uint32_t fpif13 : 1; // 13 configurable event inputs x falling edge pending bit. uint32_t fpif14 : 1; // 14 configurable event inputs x falling edge pending bit. uint32_t fpif15 : 1; // 15 configurable event inputs x falling edge pending bit. uint32_t fpif16 : 1; // 16 configurable event inputs x falling edge pending bit. uint32_t fpif17 : 1; // 17 configurable event inputs x falling edge pending bit. uint32_t fpif18 : 1; // 18 configurable event inputs x falling edge pending bit. uint32_t fpif19 : 1; // 19 configurable event inputs x falling edge pending bit. uint32_t fpif20 : 1; // 20 configurable event inputs x falling edge pending bit. uint32_t fpif21 : 1; // 21 configurable event inputs x falling edge pending bit. uint32_t fpif22 : 1; // 22 configurable event inputs x falling edge pending bit. uint32_t reserve0 : 9; // 23 Reserve } reg_exti_fpr1_t; typedef struct { uint32_t sec0 : 1; // 0 Security enable on event input x uint32_t sec1 : 1; // 1 Security enable on event input x uint32_t sec2 : 1; // 2 Security enable on event input x uint32_t sec3 : 1; // 3 Security enable on event input x uint32_t sec4 : 1; // 4 Security enable on event input x uint32_t sec5 : 1; // 5 Security enable on event input x uint32_t sec6 : 1; // 6 Security enable on event input x uint32_t sec7 : 1; // 7 Security enable on event input x uint32_t sec8 : 1; // 8 Security enable on event input x uint32_t sec9 : 1; // 9 Security enable on event input x uint32_t sec10 : 1; // 10 Security enable on event input x uint32_t sec11 : 1; // 11 Security enable on event input x uint32_t sec12 : 1; // 12 Security enable on event input x uint32_t sec13 : 1; // 13 Security enable on event input x uint32_t sec14 : 1; // 14 Security enable on event input x uint32_t sec15 : 1; // 15 Security enable on event input x uint32_t sec16 : 1; // 16 Security enable on event input x uint32_t sec17 : 1; // 17 Security enable on event input x uint32_t sec18 : 1; // 18 Security enable on event input x uint32_t sec19 : 1; // 19 Security enable on event input x uint32_t sec20 : 1; // 20 Security enable on event input x uint32_t sec21 : 1; // 21 Security enable on event input x uint32_t sec22 : 1; // 22 Security enable on event input x uint32_t reserve0 : 9; // 23 Reserve } reg_exti_seccfgr1_t; typedef struct { uint32_t priv0 : 1; // 0 Security enable on event input x uint32_t priv1 : 1; // 1 Security enable on event input x uint32_t priv2 : 1; // 2 Security enable on event input x uint32_t priv3 : 1; // 3 Security enable on event input x uint32_t priv4 : 1; // 4 Security enable on event input x uint32_t priv5 : 1; // 5 Security enable on event input x uint32_t priv6 : 1; // 6 Security enable on event input x uint32_t priv7 : 1; // 7 Security enable on event input x uint32_t priv8 : 1; // 8 Security enable on event input x uint32_t priv9 : 1; // 9 Security enable on event input x uint32_t priv10 : 1; // 10 Security enable on event input x uint32_t priv11 : 1; // 11 Security enable on event input x uint32_t priv12 : 1; // 12 Security enable on event input x uint32_t priv13 : 1; // 13 Security enable on event input x uint32_t priv14 : 1; // 14 Security enable on event input x uint32_t priv15 : 1; // 15 Security enable on event input x uint32_t priv16 : 1; // 16 Security enable on event input x uint32_t priv17 : 1; // 17 Security enable on event input x uint32_t priv18 : 1; // 18 Security enable on event input x uint32_t priv19 : 1; // 19 Security enable on event input x uint32_t priv20 : 1; // 20 Security enable on event input x uint32_t priv21 : 1; // 21 Security enable on event input x uint32_t priv22 : 1; // 22 Security enable on event input x uint32_t reserve0 : 9; // 23 Reserve } reg_exti_privcfgr1_t; typedef struct { uint32_t exti0_7 : 8; // 0 EXTIm GPIO port selection uint32_t exti8_15 : 8; // 8 EXTIm+1 GPIO port selection uint32_t exti16_23 : 8; // 16 EXTIm+2 GPIO port selection uint32_t exti24_31 : 8; // 24 EXTIm+3 GPIO port selection } reg_exti_r1_t; typedef struct { uint32_t exti0_7 : 8; // 0 EXTIm GPIO port selection uint32_t exti8_15 : 8; // 8 EXTIm+1 GPIO port selection uint32_t exti16_23 : 8; // 16 EXTIm+2 GPIO port selection uint32_t exti24_31 : 8; // 24 EXTIm+3 GPIO port selection } reg_exti_r2_t; typedef struct { uint32_t exti0_7 : 8; // 0 EXTIm GPIO port selection uint32_t exti8_15 : 8; // 8 EXTIm+1 GPIO port selection uint32_t exti16_23 : 8; // 16 EXTIm+2 GPIO port selection uint32_t exti24_31 : 8; // 24 EXTIm+3 GPIO port selection } reg_exti_r3_t; typedef struct { uint32_t exti0_7 : 8; // 0 EXTIm GPIO port selection uint32_t exti8_15 : 8; // 8 EXTIm+1 GPIO port selection uint32_t exti16_23 : 8; // 16 EXTIm+2 GPIO port selection uint32_t exti24_31 : 8; // 24 EXTIm+3 GPIO port selection } reg_exti_r4_t; typedef struct { uint32_t lock : 1; // 0 LOCK uint32_t reserve0 : 31; // 1 Reserve } reg_exti_lockr_t; typedef struct { uint32_t im0 : 1; // 0 CPU wakeup with interrupt mask on event input uint32_t im1 : 1; // 1 CPU wakeup with interrupt mask on event input uint32_t im2 : 1; // 2 CPU wakeup with interrupt mask on event input uint32_t im3 : 1; // 3 CPU wakeup with interrupt mask on event input uint32_t im4 : 1; // 4 CPU wakeup with interrupt mask on event input uint32_t im5 : 1; // 5 CPU wakeup with interrupt mask on event input uint32_t im6 : 1; // 6 CPU wakeup with interrupt mask on event input uint32_t im7 : 1; // 7 CPU wakeup with interrupt mask on event input uint32_t im8 : 1; // 8 CPU wakeup with interrupt mask on event input uint32_t im9 : 1; // 9 CPU wakeup with interrupt mask on event input uint32_t im10 : 1; // 10 CPU wakeup with interrupt mask on event input uint32_t im11 : 1; // 11 CPU wakeup with interrupt mask on event input uint32_t im12 : 1; // 12 CPU wakeup with interrupt mask on event input uint32_t im13 : 1; // 13 CPU wakeup with interrupt mask on event input uint32_t im14 : 1; // 14 CPU wakeup with interrupt mask on event input uint32_t im15 : 1; // 15 CPU wakeup with interrupt mask on event input uint32_t im16 : 1; // 16 CPU wakeup with interrupt mask on event input uint32_t im17 : 1; // 17 CPU wakeup with interrupt mask on event input uint32_t im18 : 1; // 18 CPU wakeup with interrupt mask on event input uint32_t im19 : 1; // 19 CPU wakeup with interrupt mask on event input uint32_t im20 : 1; // 20 CPU wakeup with interrupt mask on event input uint32_t im21 : 1; // 21 CPU wakeup with interrupt mask on event input uint32_t im22 : 1; // 22 CPU wakeup with interrupt mask on event input uint32_t reserve0 : 9; // 23 Reserve } reg_exti_imr1_t; typedef struct { uint32_t em0 : 1; // 0 CPU wakeup with event generation mask on event input uint32_t em1 : 1; // 1 CPU wakeup with event generation mask on event input uint32_t em2 : 1; // 2 CPU wakeup with event generation mask on event input uint32_t em3 : 1; // 3 CPU wakeup with event generation mask on event input uint32_t em4 : 1; // 4 CPU wakeup with event generation mask on event input uint32_t em5 : 1; // 5 CPU wakeup with event generation mask on event input uint32_t em6 : 1; // 6 CPU wakeup with event generation mask on event input uint32_t em7 : 1; // 7 CPU wakeup with event generation mask on event input uint32_t em8 : 1; // 8 CPU wakeup with event generation mask on event input uint32_t em9 : 1; // 9 CPU wakeup with event generation mask on event input uint32_t em10 : 1; // 10 CPU wakeup with event generation mask on event input uint32_t em11 : 1; // 11 CPU wakeup with event generation mask on event input uint32_t em12 : 1; // 12 CPU wakeup with event generation mask on event input uint32_t em13 : 1; // 13 CPU wakeup with event generation mask on event input uint32_t em14 : 1; // 14 CPU wakeup with event generation mask on event input uint32_t em15 : 1; // 15 CPU wakeup with event generation mask on event input uint32_t em16 : 1; // 16 CPU wakeup with event generation mask on event input uint32_t em17 : 1; // 17 CPU wakeup with event generation mask on event input uint32_t em18 : 1; // 18 CPU wakeup with event generation mask on event input uint32_t em19 : 1; // 19 CPU wakeup with event generation mask on event input uint32_t em20 : 1; // 20 CPU wakeup with event generation mask on event input uint32_t em21 : 1; // 21 CPU wakeup with event generation mask on event input uint32_t em22 : 1; // 22 CPU wakeup with event generation mask on event input uint32_t reserve0 : 9; // 23 Reserve } reg_exti_emr1_t; typedef struct { volatile reg_exti_rtsr1_t rtsr1; volatile reg_exti_ftsr1_t ftsr1; volatile reg_exti_swier1_t swier1; volatile reg_exti_rpr1_t rpr1; volatile reg_exti_fpr1_t fpr1; volatile reg_exti_seccfgr1_t seccfgr1; volatile reg_exti_privcfgr1_t privcfgr1; volatile uint32_t reserve0[17]; volatile reg_exti_r1_t r1; volatile reg_exti_r2_t r2; volatile reg_exti_r3_t r3; volatile reg_exti_r4_t r4; volatile reg_exti_lockr_t lockr; volatile uint32_t reserve1[3]; volatile reg_exti_imr1_t imr1; volatile reg_exti_emr1_t emr1; } reg_exti_t;