#include <stdint.h>

typedef struct {
    uint32_t  key       : 16; // 0	 Key value (write only, read 0x0000)
    uint32_t  reserve0  : 16; // 16   Reserve
} reg_iwdg_kr_t;

typedef struct {
    uint32_t  pr        : 4;  // 0	 Prescaler divider
    uint32_t  reserve0  : 28; // 4    Reserve
} reg_iwdg_pr_t;

typedef struct {
    uint32_t  rl        : 12; // 0	 Watchdog counter reload value
    uint32_t  reserve0  : 20; // 12   Reserve
} reg_iwdg_rlr_t;

typedef struct {
    uint32_t  pvu       : 1;  // 0	 Watchdog prescaler value update
    uint32_t  rvu       : 1;  // 1	 Watchdog counter reload value update
    uint32_t  wvu       : 1;  // 2	 Watchdog counter window value update
    uint32_t  ewu       : 1;  // 3	 Watchdog interrupt comparator value update
    uint32_t  reserve0  : 10; // 4    Reserve
    uint32_t  ewif      : 1;  // 14	 Watchdog Early interrupt flag
    uint32_t  reserve1  : 17; // 15   Reserve
} reg_iwdg_sr_t;

typedef struct {
    uint32_t  win       : 12; // 0	 Watchdog counter window value
    uint32_t  reserve0  : 20; // 12   Reserve
} reg_iwdg_winr_t;

typedef struct {
    uint32_t  ewit      : 12; // 0	 Watchdog counter window value
    uint32_t  reserve0  : 2; // 12   Reserve
    uint32_t  ewic      : 1;  // 14	 Watchdog early interrupt acknowledge
    uint32_t  ewie      : 1;  // 15	 Watchdog early interrupt enable
    uint32_t  reserve1  : 16; // 16   Reserve
} reg_iwdg_ewcr_t;

typedef struct {
    volatile reg_iwdg_kr_t kr;
    volatile reg_iwdg_pr_t pr;
    volatile reg_iwdg_rlr_t rlr;
    volatile reg_iwdg_sr_t sr;
    volatile reg_iwdg_winr_t winr;
    volatile reg_iwdg_ewcr_t ewcr;
} reg_iwdg_t;