#include typedef struct { uint32_t en1 : 1; // 0 DAC channel1 enable uint32_t ten1 : 1; // 1 DAC channel1 trigger enable uint32_t tsel1 : 4; // 2 DAC channel1 trigger selection uint32_t wave1 : 2; // 6 DAC channel1 noise/triangle wave generation enable uint32_t mamp1 : 4; // 8 DAC channel1 mask/amplitude selector uint32_t dmaen1 : 1; // 12 DAC channel1 DMA enable uint32_t dmaudrie1 : 1; // 13 DAC channel1 DMA Underrun Interrupt enable uint32_t cen1 : 1; // 14 DAC channel1 calibration enable uint32_t reserve0 : 1; // 15 Reserve uint32_t en2 : 1; // 16 DAC channel2 enable uint32_t ten2 : 1; // 17 DAC channel2 trigger enable uint32_t tsel2 : 4; // 18 DAC channel2 trigger selection uint32_t wave2 : 2; // 22 DAC channel2 noise/triangle wave generation enable uint32_t mamp2 : 4; // 24 DAC channel2 mask/amplitude selector uint32_t dmaen2 : 1; // 28 DAC channel2 DMA enable uint32_t dmaudrie2 : 1; // 29 DAC channel2 DMA underrun interrupt enable uint32_t cen2 : 1; // 30 DAC channel2 calibration enable uint32_t reserve1 : 1; // 31 Reserve } reg_dac_cr_t; typedef struct { uint32_t swtrig1 : 1; // 0 DAC channel1 software trigger uint32_t swtrig2 : 1; // 1 DAC channel2 software trigger uint32_t reserve0 : 30; // 2 Reserve } reg_dac_swtrgr_t; typedef struct { uint32_t dacc1dhr : 12; // 0 DAC channel1 12-bit right-aligned data uint32_t reserve0 : 4; // 12 Reserve uint32_t dacc1dhrb : 12; // 16 DAC channel1 12-bit right-aligned data B uint32_t reserve1 : 4; // 28 Reserve } reg_dac_dhr12r1_t; typedef struct { uint32_t reserve0 : 4; // 0 Reserve uint32_t dacc1dhr : 12; // 4 DAC channel1 12-bit left-aligned data uint32_t reserve1 : 4; // 16 Reserve uint32_t dacc1dhrb : 12; // 20 DAC channel1 12-bit left-aligned data B } reg_dac_dhr12l1_t; typedef struct { uint32_t dacc1dhr : 8; // 0 DAC channel1 8-bit right-aligned data uint32_t dacc1dhrb : 8; // 8 DAC channel1 8-bit right-aligned Sdata uint32_t reserve0 : 16; // 16 Reserve } reg_dac_dhr8r1_t; typedef struct { uint32_t dacc2dhr : 12; // 0 DAC channel2 12-bit right-aligned data uint32_t reserve0 : 4; // 12 Reserve uint32_t dacc2dhrb : 12; // 16 DAC channel2 12-bit right-aligned data uint32_t reserve1 : 4; // 28 Reserve } reg_dac_dhr12r2_t; typedef struct { uint32_t reserve0 : 4; // 0 Reserve uint32_t dacc2dhr : 12; // 4 DAC channel2 12-bit left-aligned data uint32_t reserve1 : 4; // 16 Reserve uint32_t dacc2dhrb : 12; // 20 DAC channel2 12-bit left-aligned data B } reg_dac_dhr12l2_t; typedef struct { uint32_t dacc2dhr : 8; // 0 DAC channel2 8-bit right-aligned data uint32_t dacc2dhrb : 8; // 8 DAC channel2 8-bit right-aligned data uint32_t reserve0 : 16; // 16 Reserve } reg_dac_dhr8r2_t; typedef struct { uint32_t dacc1dhr : 12; // 0 DAC channel1 12-bit right-aligned data uint32_t reserve0 : 4; // 12 Reserve uint32_t dacc2dhr : 12; // 16 DAC channel2 12-bit right-aligned data uint32_t reserve1 : 4; // 28 Reserve } reg_dac_dhr12rd_t; typedef struct { uint32_t reserve0 : 4; // 0 Reserve uint32_t dacc1dhr : 12; // 4 DAC channel1 12-bit left-aligned data uint32_t reserve1 : 4; // 16 Reserve uint32_t dacc2dhr : 12; // 20 DAC channel2 12-bit left-aligned data } reg_dac_dhr12ld_t; typedef struct { uint32_t dacc1dhr : 8; // 0 DAC channel1 8-bit right-aligned data uint32_t dacc2dhr : 8; // 8 DAC channel2 8-bit right-aligned data uint32_t reserve0 : 16; // 16 Reserve } reg_dac_dhr8rd_t; typedef struct { uint32_t dacc1dor : 12; // 0 DAC channel1 data output uint32_t reserve0 : 4; // 12 Reserve uint32_t dacc1dorb : 12; // 16 DAC channel1 data output uint32_t reserve1 : 4; // 28 Reserve } reg_dac_dor1_t; typedef struct { uint32_t dacc2dor : 12; // 0 DAC channel2 data output uint32_t reserve0 : 4; // 12 Reserve uint32_t dacc2dorb : 12; // 16 DAC channel2 data output uint32_t reserve1 : 4; // 28 Reserve } reg_dac_dor2_t; typedef struct { uint32_t reserve0 : 11; // 0 Reserve uint32_t dac1rdy : 1; // 11 DAC channel1 ready status bit uint32_t dorstat1 : 1; // 12 DAC channel1 output register status bit uint32_t dmaudr1 : 1; // 13 DAC channel1 DMA underrun flag uint32_t cal_flag1 : 1; // 14 DAC Channel 1 calibration offset status uint32_t bwst1 : 1; // 15 DAC Channel 1 busy writing sample time flag uint32_t reserve1 : 11; // 16 Reserve uint32_t dac2rdy : 1; // 27 DAC channel 2 ready status bit uint32_t dorstat2 : 1; // 28 DAC channel 2 output register status bit uint32_t dmaudr2 : 1; // 29 DAC channel2 DMA underrun flag uint32_t cal_flag2 : 1; // 30 DAC Channel 2 calibration offset status uint32_t bwst2 : 1; // 31 DAC Channel 2 busy writing sample time flag } reg_dac_sr_t; typedef struct { uint32_t otrim1 : 5; // 0 DAC Channel 1 offset trimming value uint32_t reserve0 : 11; // 5 Reserve uint32_t otrim2 : 5; // 16 DAC Channel 2 offset trimming value uint32_t reserve1 : 11; // 21 Reserve } reg_dac_ccr_t; typedef struct { uint32_t mode1 : 3; // 0 DAC Channel 1 mode uint32_t reserve0 : 5; // 3 Reserve uint32_t dmadouble1: 1; // 8 DAC Channel1 DMA double data mode uint32_t sinformat1: 1; // 9 Enable signed format for DAC channel1 uint32_t reserve1 : 4; // 10 Reserve uint32_t hfsel : 2; // 14 High frequency interface mode selection uint32_t mode2 : 3; // 16 DAC Channel 2 mode uint32_t reserve2 : 5; // 19 Reserve uint32_t dmadouble2: 1; // 24 DAC Channel2 DMA double data mode uint32_t sinformat2: 1; // 25 Enable signed format for DAC channel2 uint32_t reserve3 : 6; // 26 Reserve } reg_dac_mcr_t; typedef struct { uint32_t tsample1 : 10; // 0 DAC Channel 1 sample Time (only valid in sample & hold mode) uint32_t reserve0 : 22; // 10 Reserve } reg_dac_shsr1_t; typedef struct { uint32_t tsample2 : 10; // 0 DAC Channel 2 sample Time (only valid in sample and hold mode) uint32_t reserve0 : 22; // 10 Reserve } reg_dac_shsr2_t; typedef struct { uint32_t thold1 : 10; // 0 DAC Channel 1 hold Time (only valid in sample and hold mode) uint32_t reserve0 : 6; // 10 Reserve uint32_t thold2 : 10; // 16 DAC Channel 2 hold time (only valid in sample and hold mode) uint32_t reserve1 : 6; // 26 Reserve } reg_dac_shhr_t; typedef struct { uint32_t trefresh1 : 8; // 0 DAC Channel 1 refresh Time (only valid in sample and hold mode) uint32_t reserve0 : 8; // 8 Reserve uint32_t trefresh2 : 8; // 16 DAC Channel 2 refresh Time (only valid in sample and hold mode) uint32_t reserve1 : 8; // 24 Reserve } reg_dac_shrr_t; typedef struct { uint32_t reserve0 : 22; // 0 Reserve uint32_t automode : 1; // 22 DAC Autonomous mode uint32_t reserve1 : 9; // 23 Reserve } reg_dac_autocr_t; typedef struct { volatile reg_dac_cr_t cr; volatile reg_dac_swtrgr_t swtrgr; volatile reg_dac_dhr12r1_t dhr12r1; volatile reg_dac_dhr12l1_t dhr12l1; volatile reg_dac_dhr8r1_t dhr8r1; volatile reg_dac_dhr12r2_t dhr12r2; volatile reg_dac_dhr12l2_t dhr12l2; volatile reg_dac_dhr8r2_t dhr8r2; volatile reg_dac_dhr12rd_t dhr12rd; volatile reg_dac_dhr12ld_t dhr12ld; volatile reg_dac_dhr8rd_t dhr8rd; volatile reg_dac_dor1_t dor1; volatile reg_dac_dor2_t dor2; volatile reg_dac_sr_t sr; volatile reg_dac_ccr_t ccr; volatile reg_dac_mcr_t mcr; volatile reg_dac_shsr1_t shsr1; volatile reg_dac_shsr2_t shsr2; volatile reg_dac_shhr_t shhr; volatile reg_dac_shrr_t shrr; volatile uint32_t reserve0[1]; volatile reg_dac_autocr_t autocr; } reg_dac_t;