#ifndef REG_DMA_H #define REG_DMA_H #include typedef __PACKED_STRUCT { uint32_t BR1; uint32_t SAR; uint32_t DAR; uint32_t LLR; } list_node_s; typedef enum { DMA_DATA_WIDTH_8_BITS = 0, // 1 byte DMA_DATA_WIDTH_16_BITS = 1, // 2 bytes DMA_DATA_WIDTH_32_BITS = 2, // 4 bytes } dma_data_width_e; typedef enum { DMA_ADDR_FIX = 0, // address fixed DMA_ADDR_INC = 1, // address increment } dma_addr_inc_e; typedef enum { DMA_TYPE_PREPHERIAL = 0, DMA_TYPE_MEMORY = 1, } dma_type_e; typedef enum { DMA_EVENT_TRANSFER_COMPLETE = DMA_CFCR_TCF, } dma_event_e; typedef enum { DMA_ERROR_TRANSFER_ERROR = DMA_CFCR_DTEF, } dma_error_e; static dma_data_width_e get_max_data_width(dma_data_width_e width, dma_data_width_e width1) { if (width > width1) return width; else return width1; } typedef struct { uint32_t seccfgr; // secure configuration register uint32_t privcfgr; // priviledged configuration register uint32_t rcfglockr; // configuration lock register uint32_t misr; // interrupt status register uint32_t smisr; // secure interrupt status register } reg_dma_s; typedef struct { uint32_t resv: 16; uint32_t lba: 16; } reg_dma_lba_t; // channel linked list base address typedef struct { uint32_t resv: 8; uint32_t tcf: 1; // transfer complete flag uint32_t htf: 1; // half transfer flag uint32_t dtef: 1; // data transfer error flag uint32_t ulef: 1; // update linked list error flag uint32_t usef: 1; // update secure error flag uint32_t suspf: 1; // suspend flag uint32_t tof: 1; // timeout flag uint32_t resv1: 17; } reg_dma_fcr_t; // channel flag clear register // tcf htf dtef ulef usef suspf tof typedef struct { uint32_t idlef: 1; // idle flag uint32_t resv: 7; uint32_t tcf: 1; // transfer complete flag uint32_t htf: 1; // half transfer flag uint32_t dtef: 1; // data transfer error flag uint32_t ulef: 1; // update linked list error flag uint32_t usef: 1; // update secure error flag uint32_t suspf: 1; // suspend flag uint32_t tof: 1; // timeout flag uint32_t resv1: 1; uint32_t fifol: 8; // fifo level uint32_t resv2: 8; } reg_dma_sr_t; // channel status register // en 1 reset 1 susp 1 resv 5 // tcie 1 htie 1 dteie 1 uleie 1 useie 1 suspie 1 toie 1 resv 1 // lsm 1 lap 1 resv 4 prio 2 resv 8 typedef struct { uint32_t en: 1; // channel enable uint32_t reset: 1; // channel reset uint32_t susp: 1; // channel suspend uint32_t resv: 5; uint32_t tcie: 1; // transfer complete interrupt enable uint32_t htie: 1; // half transfer interrupt enable uint32_t dteie: 1; // data transfer error interrupt enable uint32_t uleie: 1; // update linked list error interrupt enable uint32_t useie: 1; // update secure error interrupt enable uint32_t suspie: 1; // suspend interrupt enable uint32_t toie: 1; // timeout interrupt enable uint32_t resv1: 1; uint32_t lsm: 1; // lock secure mode uint32_t lap: 1; // lock access protection uint32_t resv2: 4; uint32_t prio: 2; // channel priority level uint32_t resv3: 8; } reg_dma_cr_t; // channel configuration register typedef struct { uint32_t sdw_log2: 2; // source data width uint32_t resv: 1; uint32_t sinc: 1; // source increment mode uint32_t sbl_1: 6; // source burst length uint32_t resv1: 1; uint32_t pam: 2; // peripheral address mode uint32_t sbx: 1; // source burst length uint32_t sap: 1; // source address protection uint32_t ssec: 1; // source secure mode uint32_t ddw_log2: 2; // destination data width uint32_t resv2: 1; uint32_t dinc: 1; // destination increment mode uint32_t dbl_1: 6; // destination burst length uint32_t dbx: 1; // destination burst length uint32_t dhx: 1; // destination handshake uint32_t resv3: 2; uint32_t dap: 1; // destination address protection uint32_t dsec: 1; // destination secure mode } reg_dma_tr1_t; // channel transfer register typedef struct { uint32_t reqsel: 7; // request selection uint32_t resv: 2; uint32_t swreq: 1; // software request uint32_t dreq: 1; // DMA request uint32_t breq: 1; // block request uint32_t resv1: 2; uint32_t trigm: 2; // trigger mode uint32_t trigsel: 7; // trigger selection uint32_t resv2: 1; uint32_t trigpol: 2; // trigger polarity uint32_t resv3: 4; uint32_t tcem: 2; // transfer complete event mode } reg_dma_tr2_t; // channel transfer register typedef struct { uint32_t bndt: 16; // block number uint32_t resv: 16; } reg_dma_br1_t; // channel block register typedef struct { uint32_t sao: 13; // source address offset uint32_t resv: 3; uint32_t dao: 13; // destination address offset uint32_t resv1: 3; } reg_dma_tr3_t; // channel transfer register typedef struct { uint32_t brsao: 16; // block repeat source address offset uint32_t brdao: 16; // block repeat destination address offset } reg_dma_br2_t; // channel block register typedef struct { uint32_t resv: 2; uint32_t la: 14; // linked list address uint32_t ull: 1; uint32_t resv1: 10; uint32_t uda: 1; uint32_t usa: 2; uint32_t ub1: 1; uint32_t ut2: 1; uint32_t ut1: 1; } reg_dma_llr_t; // channel linked list register typedef struct { volatile reg_dma_lba_t clbar; volatile uint32_t reserved1[2]; volatile reg_dma_fcr_t cfcr; volatile reg_dma_sr_t csr; volatile reg_dma_cr_t ccr; volatile uint32_t reserved2[10]; volatile reg_dma_tr1_t ctr1; volatile reg_dma_tr2_t ctr2; volatile reg_dma_br1_t cbr1; volatile uint32_t csar; volatile uint32_t cdar; volatile reg_dma_tr3_t ctr3; volatile reg_dma_br2_t cbr2; volatile uint32_t reserved3[8]; volatile reg_dma_llr_t cllr; } reg_dma_ch_s; #endif