#include typedef struct { uint32_t tim2ie : 1; // 0 TIM2IE uint32_t tim3ie : 1; // 1 TIM3IE uint32_t tim4ie : 1; // 2 TIM4IE uint32_t tim5ie : 1; // 3 TIM5IE uint32_t tim6ie : 1; // 4 TIM6IE uint32_t tim7ie : 1; // 5 TIM7IE uint32_t wwdgie : 1; // 6 WWDGIE uint32_t iwdgie : 1; // 7 IWDGIE uint32_t spi2ie : 1; // 8 SPI2IE uint32_t usart2ie : 1; // 9 illegal access interrupt enable for USART2 uint32_t usart3ie : 1; // 10 illegal access interrupt enable for USART3 uint32_t usart4ie : 1; // 11 illegal access interrupt enable for UART4 uint32_t uart5ie : 1; // 12 illegal access interrupt enable for UART5 uint32_t i2c1ie : 1; // 13 illegal access interrupt enable for I2C1 uint32_t i2c2ie : 1; // 14 illegal access interrupt enable for I2C2 uint32_t crsie : 1; // 15 illegal access interrupt enable for CRS uint32_t i2c4ie : 1; // 16 illegal access interrupt enable for I2C4 uint32_t lptim2ie : 1; // 17 illegal access interrupt enable for LPTIM2 uint32_t fdcan1ie : 1; // 18 illegal access interrupt enable for FDCAN1 uint32_t ucpd1ie : 1; // 19 illegal access interrupt enable for UCPD1 uint32_t reserve0 : 12; // 20 Reserve } reg_sec_gtzc1_tzic_ier1_t; typedef struct { uint32_t tim1ie : 1; // 0 illegal access interrupt enable for TIM1 uint32_t spi1ie : 1; // 1 illegal access interrupt enable for SPI1 uint32_t tim8ie : 1; // 2 illegal access interrupt enable for TIM8 uint32_t usart1ie : 1; // 3 illegal access interrupt enable for USART1 uint32_t tim15ie : 1; // 4 illegal access interrupt enable for TIM5 uint32_t tim16ie : 1; // 5 illegal access interrupt enable for TIM6 uint32_t tim17ie : 1; // 6 illegal access interrupt enable for TIM7 uint32_t sai1ie : 1; // 7 illegal access interrupt enable for SAI1 uint32_t sai2ie : 1; // 8 illegal access interrupt enable for SAI2 uint32_t reserve0 : 23; // 9 Reserve } reg_sec_gtzc1_tzic_ier2_t; typedef struct { uint32_t mdf1ie : 1; // 0 illegal access interrupt enable for MDF1 uint32_t cordicie : 1; // 1 illegal access interrupt enable for CORDIC uint32_t fmacie : 1; // 2 illegal access interrupt enable for FMAC uint32_t crcie : 1; // 3 illegal access interrupt enable for CRC uint32_t tscie : 1; // 4 illegal access interrupt enable for TSC uint32_t dma2die : 1; // 5 illegal access interrupt enable for register of DMA2D uint32_t icacheie : 1; // 6 illegal access interrupt enable for ICACHE registers uint32_t dcacheie : 1; // 7 illegal access interrupt enable for DCACHE registers uint32_t adc1ie : 1; // 8 illegal access interrupt enable for ADC1 uint32_t dcmiie : 1; // 9 illegal access interrupt enable for DCMI uint32_t otgfsie : 1; // 10 illegal access interrupt enable for OTG_FS uint32_t aesie : 1; // 11 illegal access interrupt enable for AES uint32_t hashie : 1; // 12 illegal access interrupt enable for HASH uint32_t rngie : 1; // 13 illegal access interrupt enable for RNG uint32_t pkaie : 1; // 14 illegal access interrupt enable for PKA uint32_t saesie : 1; // 15 illegal access interrupt enable for SAES uint32_t octospimie: 1; // 16 illegal access interrupt enable for OCTOSPIM uint32_t sdmmc1ie : 1; // 17 illegal access interrupt enable for SDMMC2 uint32_t sdmmc2ie : 1; // 18 illegal access interrupt enable for SDMMC1 uint32_t fsmcie : 1; // 19 illegal access interrupt enable for FSMC registers uint32_t octospi1ie: 1; // 20 illegal access interrupt enable for OCTOSPI1 registers uint32_t octospi2ie: 1; // 21 illegal access interrupt enable for OCTOSPI2 registers uint32_t ramcfgie : 1; // 22 illegal access interrupt enable for RAMCFG uint32_t reserve0 : 9; // 23 Reserve } reg_sec_gtzc1_tzic_ier3_t; typedef struct { uint32_t gpdma1ie : 1; // 0 illegal access interrupt enable for GPDMA1 uint32_t flashie : 1; // 1 illegal access interrupt enable for FLASH memory uint32_t flash_regie: 1; // 2 illegal access interrupt enable for FLASH registers uint32_t otfdec1ie : 1; // 3 illegal access interrupt enable for OTFDEC1 uint32_t otfdec2ie : 1; // 4 illegal access interrupt enable for OTFDEC2 uint32_t reserve0 : 9; // 5 Reserve uint32_t tzsc1ie : 1; // 14 illegal access interrupt enable for GTZC1 TZSC registers uint32_t tzic1ie : 1; // 15 illegal access interrupt enable for GTZC1 TZIC registers uint32_t octospi1_memie: 1; // 16 illegal access interrupt enable for MPCWM1 (OCTOSPI1) memory bank uint32_t fsmc_memie: 1; // 17 illegal access interrupt enable for MPCWM2 (FSMC NAND) and MPCWM3 uint32_t bkpsramie : 1; // 18 illegal access interrupt enable for MPCWM3 (BKPSRAM) memory bank uint32_t octospi2_memie: 1; // 19 illegal access interrupt enable for OCTOSPI2 memory bank uint32_t reserve1 : 4; // 20 Reserve uint32_t sram1ie : 1; // 24 illegal access interrupt enable for SRAM1 uint32_t mpcbb1_regie: 1; // 25 illegal access interrupt enable for MPCBB1 registers uint32_t sram2ie : 1; // 26 illegal access interrupt enable for SRAM2 uint32_t mpcbb2_regie: 1; // 27 illegal access interrupt enable for MPCBB2 registers uint32_t sram3ie : 1; // 28 illegal access interrupt enable for SRAM3 uint32_t mpcbb3_regie: 1; // 29 illegal access interrupt enable for MPCBB3 registers uint32_t reserve2 : 2; // 30 Reserve } reg_sec_gtzc1_tzic_ier4_t; typedef struct { uint32_t tim2f : 1; // 0 illegal access flag for TIM2 uint32_t tim3f : 1; // 1 illegal access flag for TIM3 uint32_t tim4f : 1; // 2 illegal access flag for TIM4 uint32_t tim5f : 1; // 3 illegal access flag for TIM5 uint32_t tim6f : 1; // 4 illegal access flag for TIM6 uint32_t tim7f : 1; // 5 illegal access flag for TIM7 uint32_t wwdgf : 1; // 6 illegal access flag for WWDG uint32_t iwdgf : 1; // 7 illegal access flag for IWDG uint32_t spi2f : 1; // 8 illegal access flag for SPI2 uint32_t usart2f : 1; // 9 illegal access flag for USART2 uint32_t usart3f : 1; // 10 illegal access flag for USART3 uint32_t uart4f : 1; // 11 illegal access flag for UART4 uint32_t uart5f : 1; // 12 illegal access flag for UART5 uint32_t i2c1f : 1; // 13 illegal access flag for I2C1 uint32_t i2c2f : 1; // 14 illegal access flag for I2C2 uint32_t crsf : 1; // 15 illegal access flag for CRS uint32_t i2c4f : 1; // 16 illegal access flag for I2C4 uint32_t lptim2f : 1; // 17 illegal access flag for LPTIM2 uint32_t fdcan1f : 1; // 18 illegal access flag for FDCAN1 uint32_t ucpd1f : 1; // 19 illegal access flag for UCPD1 uint32_t reserve0 : 12; // 20 Reserve } reg_sec_gtzc1_tzic_sr1_t; typedef struct { uint32_t tim1f : 1; // 0 illegal access flag for TIM1 uint32_t spi1f : 1; // 1 illegal access flag for SPI1 uint32_t tim8f : 1; // 2 illegal access flag for TIM8 uint32_t usart1f : 1; // 3 illegal access flag for USART1 uint32_t tim15f : 1; // 4 illegal access flag for TIM5 uint32_t tim16f : 1; // 5 illegal access flag for TIM6 uint32_t tim17f : 1; // 6 illegal access flag for TIM7 uint32_t sai1f : 1; // 7 illegal access flag for SAI1 uint32_t sai2f : 1; // 8 illegal access flag for SAI2 uint32_t reserve0 : 23; // 9 Reserve } reg_sec_gtzc1_tzic_sr2_t; typedef struct { uint32_t mdf1f : 1; // 0 illegal access flag for MDF1 uint32_t cordicf : 1; // 1 illegal access flag for CORDIC uint32_t fmacf : 1; // 2 illegal access flag for FMAC uint32_t crcf : 1; // 3 illegal access flag for CRC uint32_t tscf : 1; // 4 illegal access flag for TSC uint32_t dma2df : 1; // 5 illegal access flag for register of DMA2D uint32_t icachef : 1; // 6 illegal access flag for ICACHE registers uint32_t dcachef : 1; // 7 illegal access flag for DCACHE registers uint32_t adc1f : 1; // 8 illegal access flag for ADC1 uint32_t dcmif : 1; // 9 illegal access flag for DCMI uint32_t otgfsf : 1; // 10 illegal access flag for OTG_FS uint32_t aesf : 1; // 11 illegal access flag for AES uint32_t hashf : 1; // 12 illegal access flag for HASH uint32_t rngf : 1; // 13 illegal access flag for RNG uint32_t pkaf : 1; // 14 illegal access flag for PKA uint32_t saesf : 1; // 15 illegal access flag for SAES uint32_t octospimf : 1; // 16 illegal access flag for OCTOSPIM uint32_t sdmmc1f : 1; // 17 illegal access flag for SDMMC2 uint32_t sdmmc2f : 1; // 18 illegal access flag for SDMMC1 uint32_t fsmcf : 1; // 19 illegal access flag for FSMC registers uint32_t octospi1f : 1; // 20 illegal access flag for OCTOSPI1 registers uint32_t octospi2f : 1; // 21 illegal access flag for OCTOSPI2 registers uint32_t ramcfgf : 1; // 22 illegal access flag for RAMCFG uint32_t reserve0 : 9; // 23 Reserve } reg_sec_gtzc1_tzic_sr3_t; typedef struct { uint32_t gpdma1f : 1; // 0 illegal access flag for GPDMA1 uint32_t flashf : 1; // 1 illegal access flag for FLASH memory uint32_t flash_regf: 1; // 2 illegal access flag for FLASH registers uint32_t otfdec1f : 1; // 3 illegal access flag for OTFDEC1 uint32_t otfdec2f : 1; // 4 illegal access flag for OTFDEC2 uint32_t reserve0 : 9; // 5 Reserve uint32_t tzsc1f : 1; // 14 illegal access flag for GTZC1 TZSC registers uint32_t tzic1f : 1; // 15 illegal access flag for GTZC1 TZIC registers uint32_t octospi1_memf: 1; // 16 illegal access flag for MPCWM1 (OCTOSPI1) memory bank uint32_t fsmc_memf : 1; // 17 illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3 (FSMC NOR) uint32_t bkpsramf : 1; // 18 illegal access flag for MPCWM3 (BKPSRAM) memory bank uint32_t octospi2_memf: 1; // 19 illegal access flag for OCTOSPI2 memory bank uint32_t reserve1 : 4; // 20 Reserve uint32_t sram1f : 1; // 24 illegal access flag for SRAM1 uint32_t mpcbb1_regf: 1; // 25 illegal access flag for MPCBB1 registers uint32_t sram2f : 1; // 26 illegal access flag for SRAM2 uint32_t mpcbb2_regf: 1; // 27 illegal access flag for MPCBB2 registers uint32_t sram3f : 1; // 28 illegal access flag for SRAM3 uint32_t mpcbb3_regf: 1; // 29 illegal access flag for MPCBB3 registers uint32_t reserve2 : 2; // 30 Reserve } reg_sec_gtzc1_tzic_sr4_t; typedef struct { uint32_t ctim2f : 1; // 0 clear the illegal access flag for TIM2 uint32_t ctim3f : 1; // 1 clear the illegal access flag for TIM3 uint32_t ctim4f : 1; // 2 clear the illegal access flag for TIM4 uint32_t ctim5f : 1; // 3 clear the illegal access flag for TIM5 uint32_t ctim6f : 1; // 4 clear the illegal access flag for TIM6 uint32_t ctim7f : 1; // 5 clear the illegal access flag for TIM7 uint32_t cwwdgf : 1; // 6 clear the illegal access flag for WWDG uint32_t ciwdgf : 1; // 7 clear the illegal access flag for IWDG uint32_t cspi2f : 1; // 8 clear the illegal access flag for SPI2 uint32_t cusart2f : 1; // 9 clear the illegal access flag for USART2 uint32_t cusart3f : 1; // 10 clear the illegal access flag for USART3 uint32_t cuart4f : 1; // 11 clear the illegal access flag for UART4 uint32_t cuart5f : 1; // 12 clear the illegal access flag for UART5 uint32_t ci2c1f : 1; // 13 clear the illegal access flag for I2C1 uint32_t ci2c2f : 1; // 14 clear the illegal access flag for I2C2 uint32_t ccrsf : 1; // 15 clear the illegal access flag for CRS uint32_t ci2c4f : 1; // 16 clear the illegal access flag for I2C4 uint32_t clptim2f : 1; // 17 clear the illegal access flag for LPTIM2 uint32_t cfdcan1f : 1; // 18 clear the illegal access flag for FDCAN1 uint32_t cucpd1f : 1; // 19 clear the illegal access flag for UCPD1 uint32_t reserve0 : 12; // 20 Reserve } reg_sec_gtzc1_tzic_fcr1_t; typedef struct { uint32_t ctim1f : 1; // 0 clear the illegal access flag for TIM1 uint32_t cspi1f : 1; // 1 clear the illegal access flag for SPI1 uint32_t ctim8f : 1; // 2 clear the illegal access flag for TIM8 uint32_t cusart1f : 1; // 3 clear the illegal access flag for USART1 uint32_t ctim15f : 1; // 4 clear the illegal access flag for TIM5 uint32_t ctim16f : 1; // 5 clear the illegal access flag for TIM6 uint32_t ctim17f : 1; // 6 clear the illegal access flag for TIM7 uint32_t csai1f : 1; // 7 clear the illegal access flag for SAI1 uint32_t csai2f : 1; // 8 clear the illegal access flag for SAI2 uint32_t reserve0 : 23; // 9 Reserve } reg_sec_gtzc1_tzic_fcr2_t; typedef struct { uint32_t cmdf1f : 1; // 0 clear the illegal access flag for MDF1 uint32_t ccordicf : 1; // 1 clear the illegal access flag for CORDIC uint32_t cfmacf : 1; // 2 clear the illegal access flag for FMAC uint32_t ccrcf : 1; // 3 clear the illegal access flag for CRC uint32_t ctscf : 1; // 4 clear the illegal access flag for TSC uint32_t cdma2df : 1; // 5 clear the illegal access flag for register of DMA2D uint32_t cicachef : 1; // 6 clear the illegal access flag for ICACHE registers uint32_t cdcachef : 1; // 7 clear the illegal access flag for DCACHE registers uint32_t cadc1f : 1; // 8 clear the illegal access flag for ADC1 uint32_t cdcmif : 1; // 9 clear the illegal access flag for DCMI uint32_t cotgfsf : 1; // 10 clear the illegal access flag for OTG_FS uint32_t caesf : 1; // 11 clear the illegal access flag for AES uint32_t chashf : 1; // 12 clear the illegal access flag for HASH uint32_t crngf : 1; // 13 clear the illegal access flag for RNG uint32_t cpkaf : 1; // 14 clear the illegal access flag for PKA uint32_t csaesf : 1; // 15 clear the illegal access flag for SAES uint32_t coctospimf: 1; // 16 clear the illegal access flag for OCTOSPIM uint32_t csdmmc1f : 1; // 17 clear the illegal access flag for SDMMC2 uint32_t csdmmc2f : 1; // 18 clear the illegal access flag for SDMMC1 uint32_t cfsmcf : 1; // 19 clear the illegal access flag for FSMC registers uint32_t coctospi1f: 1; // 20 clear the illegal access flag for OCTOSPI1 registers uint32_t coctospi2f: 1; // 21 clear the illegal access flag for OCTOSPI2 registers uint32_t cramcfgf : 1; // 22 clear the illegal access flag for RAMCFG uint32_t reserve0 : 9; // 23 Reserve } reg_sec_gtzc1_tzic_fcr3_t; typedef struct { uint32_t cgpdma1f : 1; // 0 clear the illegal access flag for GPDMA1 uint32_t cflashf : 1; // 1 clear the illegal access flag for FLASH memory uint32_t cflash_regf: 1; // 2 clear the illegal access flag for FLASH registers uint32_t cotfdec1f : 1; // 3 clear the illegal access flag for OTFDEC1 uint32_t cotfdec2f : 1; // 4 clear the illegal access flag for OTFDEC2 uint32_t reserve0 : 9; // 5 Reserve uint32_t ctzsc1f : 1; // 14 clear the illegal access flag for GTZC1 TZSC registers uint32_t ctzic1f : 1; // 15 clear the illegal access flag for GTZC1 TZIC registers uint32_t coctospi1_memf: 1; // 16 clear the illegal access flag for MPCWM1 (OCTOSPI1) memory bank uint32_t cfsmc_memf: 1; // 17 clear the illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3 uint32_t cbkpsramf : 1; // 18 clear the illegal access flag for MPCWM3 (BKPSRAM) memory bank uint32_t coctospi2_memf: 1; // 19 clear the illegal access flag for OCTOSPI2 memory bank uint32_t reserve1 : 4; // 20 Reserve uint32_t csram1f : 1; // 24 clear the illegal access flag for SRAM1 uint32_t cmpcbb1_regf: 1; // 25 clear the illegal access flag for MPCBB1 registers uint32_t csram2f : 1; // 26 clear the illegal access flag for SRAM2 uint32_t cmpcbb2_regf: 1; // 27 clear the illegal access flag for MPCBB2 registers uint32_t csram3f : 1; // 28 clear the illegal access flag for SRAM3 uint32_t cmpcbb3_regf: 1; // 29 clear the illegal access flag for MPCBB3 registers uint32_t reserve2 : 2; // 30 Reserve } reg_sec_gtzc1_tzic_fcr4_t; typedef struct { volatile reg_sec_gtzc1_tzic_ier1_t ier1; volatile reg_sec_gtzc1_tzic_ier2_t ier2; volatile reg_sec_gtzc1_tzic_ier3_t ier3; volatile reg_sec_gtzc1_tzic_ier4_t ier4; volatile reg_sec_gtzc1_tzic_sr1_t sr1; volatile reg_sec_gtzc1_tzic_sr2_t sr2; volatile reg_sec_gtzc1_tzic_sr3_t sr3; volatile reg_sec_gtzc1_tzic_sr4_t sr4; volatile reg_sec_gtzc1_tzic_fcr1_t fcr1; volatile reg_sec_gtzc1_tzic_fcr2_t fcr2; volatile reg_sec_gtzc1_tzic_fcr3_t fcr3; volatile reg_sec_gtzc1_tzic_fcr4_t fcr4; } reg_sec_gtzc1_tzic_t;