#include <stdint.h>

typedef struct {
    uint32_t  capture   : 1;  // 0	 Capture enable
    uint32_t  cm        : 1;  // 1	 Capture mode
    uint32_t  crop      : 1;  // 2	 Crop feature
    uint32_t  jpeg      : 1;  // 3	 JPEG format
    uint32_t  ess       : 1;  // 4	 Embedded synchronization select
    uint32_t  pckpol    : 1;  // 5	 Pixel clock polarity
    uint32_t  hspol     : 1;  // 6	 Horizontal synchronization polarity
    uint32_t  vspol     : 1;  // 7	 Vertical synchronization polarity
    uint32_t  fcrc      : 2;  // 8	 Frame capture rate control
    uint32_t  edm       : 2;  // 10	 Extended data mode
    uint32_t  reserve0  : 2; // 12   Reserve
    uint32_t  enable    : 1;  // 14	 DCMI enable
    uint32_t  reserve1  : 1; // 15   Reserve
    uint32_t  bsm       : 2;  // 16	 Byte Select mode
    uint32_t  oebs      : 1;  // 18	 Odd/Even Byte Select (Byte Select Start)
    uint32_t  lsm       : 1;  // 19	 Line Select mode
    uint32_t  oels      : 1;  // 20	 Odd/Even Line Select (Line Select Start)
    uint32_t  reserve2  : 11; // 21   Reserve
} reg_sec_dcmi_cr_t;

typedef struct {
    uint32_t  hsync     : 1;  // 0	 Horizontal synchronization
    uint32_t  vsync     : 1;  // 1	 Vertical synchronization
    uint32_t  fne       : 1;  // 2	 FIFO not empty
    uint32_t  reserve0  : 29; // 3    Reserve
} reg_sec_dcmi_sr_t;

typedef struct {
    uint32_t  frame_ris : 1;  // 0	 Capture complete raw interrupt status
    uint32_t  ovr_ris   : 1;  // 1	 Overrun raw interrupt status
    uint32_t  err_ris   : 1;  // 2	 Synchronization error raw interrupt status
    uint32_t  vsync_ris : 1;  // 3	 DCMI_VSYNC raw interrupt status
    uint32_t  line_ris  : 1;  // 4	 Line raw interrupt status
    uint32_t  reserve0  : 27; // 5    Reserve
} reg_sec_dcmi_ris_t;

typedef struct {
    uint32_t  frame_ie  : 1;  // 0	 Capture complete interrupt enable
    uint32_t  ovr_ie    : 1;  // 1	 Overrun interrupt enable
    uint32_t  err_ie    : 1;  // 2	 Synchronization error interrupt enable
    uint32_t  vsync_ie  : 1;  // 3	 DCMI_VSYNC interrupt enable
    uint32_t  line_ie   : 1;  // 4	 Line interrupt enable
    uint32_t  reserve0  : 27; // 5    Reserve
} reg_sec_dcmi_ier_t;

typedef struct {
    uint32_t  frame_mis : 1;  // 0	 Capture complete masked interrupt status
    uint32_t  ovr_mis   : 1;  // 1	 Overrun masked interrupt status
    uint32_t  err_mis   : 1;  // 2	 Synchronization error masked interrupt status
    uint32_t  vsync_mis : 1;  // 3	 VSYNC masked interrupt status
    uint32_t  line_mis  : 1;  // 4	 Line masked interrupt status
    uint32_t  reserve0  : 27; // 5    Reserve
} reg_sec_dcmi_mis_t;

typedef struct {
    uint32_t  frame_isc : 1;  // 0	 Capture complete interrupt status clear
    uint32_t  ovr_isc   : 1;  // 1	 Overrun interrupt status clear
    uint32_t  err_isc   : 1;  // 2	 Synchronization error interrupt status clear
    uint32_t  vsync_isc : 1;  // 3	 Vertical Synchronization interrupt status clear
    uint32_t  line_isc  : 1;  // 4	 line interrupt status clear
    uint32_t  reserve0  : 27; // 5    Reserve
} reg_sec_dcmi_icr_t;

typedef struct {
    uint32_t  fsc       : 8;  // 0	 Frame start delimiter code
    uint32_t  lsc       : 8;  // 8	 Line start delimiter code
    uint32_t  lec       : 8;  // 16	 Line end delimiter code
    uint32_t  fec       : 8;  // 24	 Frame end delimiter code
} reg_sec_dcmi_escr_t;

typedef struct {
    uint32_t  fsu       : 8;  // 0	 Frame start delimiter unmask
    uint32_t  lsu       : 8;  // 8	 Line start delimiter unmask
    uint32_t  leu       : 8;  // 16	 Line end delimiter unmask
    uint32_t  feu       : 8;  // 24	 Frame end delimiter unmask
} reg_sec_dcmi_esur_t;

typedef struct {
    uint32_t  hoffcnt   : 14; // 0	 Horizontal offset count
    uint32_t  reserve0  : 2; // 14   Reserve
    uint32_t  vst       : 13; // 16	 Vertical start line count
    uint32_t  reserve1  : 3;  // 29   Reserve
} reg_sec_dcmi_cwstrt_t;

typedef struct {
    uint32_t  capcnt    : 14; // 0	 Capture count
    uint32_t  reserve0  : 2; // 14   Reserve
    uint32_t  vline     : 14; // 16	 Vertical line count
    uint32_t  reserve1  : 2;  // 30   Reserve
} reg_sec_dcmi_cwsize_t;

typedef struct {
    uint32_t  byte0     : 8;  // 0	 Data byte 0
    uint32_t  byte1     : 8;  // 8	 Data byte 1
    uint32_t  byte2     : 8;  // 16	 Data byte 2
    uint32_t  byte3     : 8;  // 24	 Data byte 3
} reg_sec_dcmi_dr_t;

typedef struct {
    volatile reg_sec_dcmi_cr_t cr;
    volatile reg_sec_dcmi_sr_t sr;
    volatile reg_sec_dcmi_ris_t ris;
    volatile reg_sec_dcmi_ier_t ier;
    volatile reg_sec_dcmi_mis_t mis;
    volatile reg_sec_dcmi_icr_t icr;
    volatile reg_sec_dcmi_escr_t escr;
    volatile reg_sec_dcmi_esur_t esur;
    volatile reg_sec_dcmi_cwstrt_t cwstrt;
    volatile reg_sec_dcmi_cwsize_t cwsize;
    volatile reg_sec_dcmi_dr_t dr;
} reg_sec_dcmi_t;