#ifndef REG_TIM_H #define REG_TIM_H #include "stm32u5xx.h" #include typedef struct { uint32_t cen: 1; // counter enable uint32_t udis: 1; // update disable uint32_t urs: 1; // update request source uint32_t opm: 1; // one pulse mode uint32_t dir: 1; // direction uint32_t cms: 2; // center-aligned mode selection uint32_t arpe: 1; // auto-reload preload enable uint32_t ckd: 2; // clock division uint32_t reserved: 1; // reserved uint32_t uifremap: 1; // UIF status bit remapping uint32_t dithen: 1; // Dither enable uint32_t reserved2: 19; // reserved } reg_tim_cr1_t; typedef struct { uint32_t ccpc: 1; // capture/compare preloaded control uint32_t resv1: 1; // reserved uint32_t ccus: 1; // capture/compare control update selection uint32_t ccds: 1; // capture/compare DMA selection uint32_t mms: 3; // master mode selection uint32_t ti1s: 1; // TI1 selection uint32_t ois1: 1; // output idle state 1 uint32_t ois1n: 1; // output idle state 1 uint32_t ois2: 1; // output idle state 2 uint32_t ois2n: 1; // output idle state 2 uint32_t ois3: 1; // output idle state 3 uint32_t ois3n: 1; // output idle state 3 uint32_t ois4: 1; // output idle state 4 uint32_t ois4n: 1; // output idle state 4 uint32_t ois5: 1; // output idle state 5 uint32_t resv2: 1; // reserved uint32_t ois6: 1; // output idle state 6 uint32_t resv3: 1; // reserved uint32_t mms2: 4; // master mode selection 2 uint32_t resv4: 1; // reserved uint32_t mms3: 1; // master mode selection 3 uint32_t resv5: 6; // reserved } reg_tim_cr2_t; typedef struct { uint32_t sms: 3; // slave mode selection uint32_t occs: 1; // OCREF clear selection uint32_t ts: 3; // trigger selection uint32_t msm: 1; // master/slave mode uint32_t etf: 4; // external trigger filter uint32_t etps: 2; // external trigger prescaler uint32_t ece: 1; // external clock enable uint32_t etp: 1; // external trigger polarity uint32_t sms3: 1; // slave mode selection 3 uint32_t resv1: 3; // reserved uint32_t ts2: 2; // trigger selection uint32_t resv2: 2; // reserved uint32_t smspe: 1; // slave mode selection uint32_t smsps: 1; // slave mode selection uint32_t resv3: 6; // reserved } reg_tim_smcr_t; // slave mode control register typedef struct { uint32_t uie: 1; // update interrupt enable uint32_t cc1ie: 1; // capture/compare 1 interrupt enable uint32_t cc2ie: 1; // capture/compare 2 interrupt enable uint32_t cc3ie: 1; // capture/compare 3 interrupt enable uint32_t cc4ie: 1; // capture/compare 4 interrupt enable uint32_t comie: 1; // commutation interrupt enable uint32_t tie: 1; // trigger interrupt enable uint32_t bie: 1; // break interrupt enable uint32_t ude: 1; // update DMA request enable uint32_t cc1de: 1; // capture/compare 1 DMA request enable uint32_t cc2de: 1; // capture/compare 2 DMA request enable uint32_t cc3de: 1; // capture/compare 3 DMA request enable uint32_t cc4de: 1; // capture/compare 4 DMA request enable uint32_t comde: 1; // commutation DMA request enable uint32_t tde: 1; // trigger DMA request enable uint32_t resv: 5; // reserved uint32_t idxie: 1; // index interrupt enable uint32_t dirie: 1; // direction interrupt enable uint32_t ierrie: 1; // input capture interrupt enable uint32_t terr: 1; // trigger error interrupt enable uint32_t resv2: 8; // reserved } reg_tim_dier_t; // DMA/Interrupt enable register typedef struct { uint32_t uif: 1; // update interrupt flag uint32_t cc1if: 1; // capture/compare 1 interrupt flag uint32_t cc2if: 1; // capture/compare 2 interrupt flag uint32_t cc3if: 1; // capture/compare 3 interrupt flag uint32_t cc4if: 1; // capture/compare 4 interrupt flag uint32_t comif: 1; // commutation interrupt flag uint32_t tif: 1; // trigger interrupt flag uint32_t bif: 1; // break interrupt flag uint32_t b2if: 1; // break 2 interrupt flag uint32_t cc1of: 1; // capture/compare 1 overcapture flag uint32_t cc2of: 1; // capture/compare 2 overcapture flag uint32_t cc3of: 1; // capture/compare 3 overcapture flag uint32_t cc4of: 1; // capture/compare 4 overcapture flag uint32_t sbif: 1; // system break interrupt flag uint32_t resv: 2; // reserved uint32_t cc5if: 1; // capture/compare 5 interrupt flag uint32_t cc6if: 1; // capture/compare 6 interrupt flag uint32_t resv2: 2; // reserved uint32_t idxf: 1; // index interrupt flag uint32_t dirf: 1; // direction interrupt flag uint32_t ierrf: 1; // input capture interrupt flag uint32_t terrf: 1; // trigger error interrupt flag uint32_t resv3: 8; // reserved } reg_tim_sr_t; // status register typedef struct { uint32_t ug: 1; // update generation uint32_t cc1g: 1; // capture/compare 1 generation uint32_t cc2g: 1; // capture/compare 2 generation uint32_t cc3g: 1; // capture/compare 3 generation uint32_t cc4g: 1; // capture/compare 4 generation uint32_t comg: 1; // capture/compare control update generation uint32_t tg: 1; // trigger generation uint32_t bg: 1; // break generation uint32_t b2g: 1; // break 2 generation uint32_t resv: 23; // reserved } reg_tim_egr_t; // event generation register typedef struct { uint32_t cc1s: 2; // capture/compare 1 selection uint32_t ic1psc: 2; // input capture 1 prescaler uint32_t ic1f: 4; // input capture 1 filter uint32_t cc2s: 2; // capture/compare 2 selection uint32_t ic2psc: 2; // input capture 2 prescaler uint32_t ic2f: 4; // input capture 2 filter uint32_t resv: 16; // reserved } reg_tim_ccmr1_in_t; // capture/compare mode register 1 typedef struct { uint32_t cc1s: 2; // capture/compare 1 selection uint32_t oc1fe: 1; // output compare 1 fast enable uint32_t oc1pe: 1; // output compare 1 preload enable uint32_t oc1m: 3; // output compare 1 mode uint32_t oc1ce: 1; // output compare 1 clear enable uint32_t cc2s: 2; // capture/compare 2 selection uint32_t oc2fe: 1; // output compare 2 fast enable uint32_t oc2pe: 1; // output compare 2 preload enable uint32_t oc2m: 3; // output compare 2 mode uint32_t oc2ce: 1; // output compare 2 clear enable uint32_t oc1m3: 1; // output compare 1 mode bit 3 uint32_t resv: 7; // reserved uint32_t oc2m3: 1; // output compare 2 mode bit 3 uint32_t resv2: 7; // reserved } reg_tim_ccmr1_out_t; // capture/compare mode register 1 union reg_tim_ccmr1_t { reg_tim_ccmr1_in_t in; reg_tim_ccmr1_out_t out; }; typedef struct { uint32_t cc3s: 2; // capture/compare 3 selection uint32_t ic3psc: 2; // input capture 3 prescaler uint32_t ic3f: 4; // input capture 3 filter uint32_t cc4s: 2; // capture/compare 4 selection uint32_t ic4psc: 2; // input capture 4 prescaler uint32_t ic4f: 4; // input capture 4 filter uint32_t resv: 16; // reserved } reg_tim_ccmr2_in_t; // capture/compare mode register 2 typedef struct { uint32_t cc3s: 2; // capture/compare 3 selection uint32_t oc3fe: 1; // output compare 3 fast enable uint32_t oc3pe: 1; // output compare 3 preload enable uint32_t oc3m: 3; // output compare 3 mode uint32_t oc3ce: 1; // output compare 3 clear enable uint32_t cc4s: 2; // capture/compare 4 selection uint32_t oc4fe: 1; // output compare 4 fast enable uint32_t oc4pe: 1; // output compare 4 preload enable uint32_t oc4m: 3; // output compare 4 mode uint32_t oc4ce: 1; // output compare 4 clear enable uint32_t oc3m3: 1; // output compare 3 mode bit 3 uint32_t resv: 7; // reserved uint32_t oc4m3: 1; // output compare 4 mode bit 3 uint32_t resv2: 7; // reserved } reg_tim_ccmr2_out_t; // capture/compare mode register 2 union reg_tim_ccmr2_t { reg_tim_ccmr2_in_t in; reg_tim_ccmr2_out_t out; }; typedef struct { uint32_t cc1e: 1; // capture/compare 1 output enable uint32_t cc1p: 1; // capture/compare 1 output polarity uint32_t cc1ne: 1; // capture/compare 1 complementary output enable uint32_t cc1np: 1; // capture/compare 1 complementary output polarity uint32_t cc2e: 1; // capture/compare 2 output enable uint32_t cc2p: 1; // capture/compare 2 output polarity uint32_t cc2ne: 1; // capture/compare 2 complementary output enable uint32_t cc2np: 1; // capture/compare 2 complementary output polarity uint32_t cc3e: 1; // capture/compare 3 output enable uint32_t cc3p: 1; // capture/compare 3 output polarity uint32_t cc3ne: 1; // capture/compare 3 complementary output enable uint32_t cc3np: 1; // capture/compare 3 complementary output polarity uint32_t cc4e: 1; // capture/compare 4 output enable uint32_t cc4p: 1; // capture/compare 4 output polarity uint32_t cc4ne: 1; // capture/compare 4 complementary output enable uint32_t cc4np: 1; // capture/compare 4 complementary output polarity uint32_t cc5e: 1; // capture/compare 5 output enable uint32_t cc5p: 1; // capture/compare 5 output polarity uint32_t resv: 2; // reserved uint32_t cc6e: 1; // capture/compare 6 output enable uint32_t cc6p: 1; // capture/compare 6 output polarity uint32_t resv2: 10; // reserved } reg_tim_ccer_t; // capture/compare enable register typedef struct { uint32_t cnt: 16; // counter value uint32_t resv: 15; // reserved uint32_t uifcpy: 1; // UIF copy } reg_tim_cnt_t; // counter typedef struct { uint32_t psc: 16; // prescaler value uint32_t resv: 16; // reserved } reg_tim_psc_t; // prescaler typedef struct { uint32_t arr: 20; // auto-reload value uint32_t resv: 12; // reserved } reg_tim_arr_t; // auto-reload register typedef struct { uint32_t rep: 16; // repetition counter value uint32_t resv: 16; // reserved } reg_tim_rcr_t; // repetition counter register typedef struct { uint32_t ccr1: 20; // capture/compare 1 value uint32_t resv: 12; // reserved } reg_tim_ccr1_t; // capture/compare register 1 typedef struct { uint32_t ccr2: 20; // capture/compare 2 value uint32_t resv: 12; // reserved } reg_tim_ccr2_t; // capture/compare register 2 typedef struct { uint32_t ccr3: 20; // capture/compare 3 value uint32_t resv: 12; // reserved } reg_tim_ccr3_t; // capture/compare register 3 typedef struct { uint32_t ccr4: 20; // capture/compare 4 value uint32_t resv: 12; // reserved } reg_tim_ccr4_t; // capture/compare register 4 typedef struct { uint32_t dtg: 8; // dead-time generator setup uint32_t lock: 2; // lock configuration uint32_t ossi: 1; // off-state selection for idle mode uint32_t ossr: 1; // off-state selection for run mode uint32_t bke: 1; // break enable uint32_t bkp: 1; // break polarity uint32_t aoe: 1; // automatic output enable uint32_t moe: 1; // main output enable uint32_t bkf: 4; // break filter uint32_t bk2f: 4; // break 2 filter uint32_t bk2e: 1; // break 2 enable uint32_t bk2p: 1; // break 2 polarity uint32_t bkdsrm: 1; // break disarming uint32_t bk2dsrm: 1; // break 2 disarming uint32_t bkbid: 1; // break bidirectional uint32_t bk2bid: 1; // break 2 bidirectional uint32_t resv: 2; // reserved } reg_tim_bdtr_t; // break and dead-time register typedef struct { uint32_t ccr5: 20; // capture/compare 5 value uint32_t resv: 9; // reserved uint32_t gc5c1: 1; // group channel 5 and channel 1 uint32_t gc5c2: 1; // group channel 5 and channel 2 uint32_t gc5c3: 1; // group channel 5 and channel 3 } reg_tim_ccr5_t; // capture/compare register 5 typedef struct { uint32_t cc6: 20; // capture/compare 6 value uint32_t resv: 12; // reserved } reg_tim_ccr6_t; // capture/compare register 6 // cmmr3 typedef struct { uint32_t resv: 24; // reserved uint32_t oc5fe: 1; // output compare 5 fast enable uint32_t oc5pe: 1; // output compare 5 preload enable uint32_t oc5m: 3; // output compare 5 mode uint32_t oc5ce: 1; // output compare 5 clear enable uint32_t resv2: 2; // reserved uint32_t oc6fe: 1; // output compare 6 fast enable uint32_t oc6pe: 1; // output compare 6 preload enable uint32_t oc6m: 3; // output compare 6 mode uint32_t oc6ce: 1; // output compare 6 clear enable uint32_t oc5m3: 1; // output compare 5 mode bit 3 uint32_t resv3: 7; // reserved uint32_t oc6m3: 1; // output compare 6 mode bit 3 uint32_t resv4: 7; // reserved } reg_tim_ccmr3_t; // capture/compare mode register 3 typedef struct { uint32_t dtgf: 8; // dead-time generator setup uint32_t resv: 8; // reserved uint32_t dtae: 1; // dead-time active on idle uint32_t dtpe: 1; // dead-time preload uint32_t resv2: 14; // reserved } reg_tim_dtr2_t; // DMA/interrupt enable register 2 // ECR typedef struct { uint32_t ie: 1; // internal trigger polarity uint32_t idir: 2; // internal trigger prescaler uint32_t iblk: 2; // internal trigger filter uint32_t fidx: 1; // filter index uint32_t ipos: 2; // internal trigger prescaler uint32_t resv: 8; // reserved uint32_t pw: 8; // pulse width uint32_t pwprsc: 3; // pulse width prescaler uint32_t resv2: 5; // reserved } reg_tim_ecr_t; // external clock register typedef struct { uint32_t ti1sel: 4; // TI1 selection uint32_t resv: 4; // reserved uint32_t ti2sel: 4; // TI2 selection uint32_t resv2: 4; // reserved uint32_t ti3sel: 4; // TI3 selection uint32_t resv3: 4; // reserved uint32_t ti4sel: 4; // TI4 selection uint32_t resv4: 4; // reserved } reg_tim_tisel_t; // TIx external clock source selection register typedef struct { reg_tim_cr1_t cr1; // control register 1 reg_tim_cr2_t cr2; // control register 2 reg_tim_smcr_t smcr; // slave mode control register reg_tim_dier_t dier; // DMA/Interrupt enable register reg_tim_sr_t sr; // status register reg_tim_egr_t egr; // event generation register reg_tim_ccmr1_t ccmr1; // capture/compare mode register 1 reg_tim_ccmr2_t ccmr2; // capture/compare mode register 2 reg_tim_ccer_t ccer; // capture/compare enable register reg_tim_cnt_t cnt; // counter reg_tim_psc_t psc; // prescaler reg_tim_arr_t arr; // auto-reload register reg_tim_rcr_t rcr; // repetition counter register reg_tim_ccr1_t ccr1; // capture/compare register 1 reg_tim_ccr2_t ccr2; // capture/compare register 2 reg_tim_ccr3_t ccr3; // capture/compare register 3 reg_tim_ccr4_t ccr4; // capture/compare register 4 reg_tim_bdtr_t bdtr; // break and dead-time register reg_tim_ccr5_t ccr5; // capture/compare register 5 reg_tim_ccr6_t ccr6; // capture/compare register 6 reg_tim_ccmr3_t ccmr3; // capture/compare mode register 3 reg_tim_dtr2_t dtr2; // DMA/interrupt enable register 2 reg_tim_ecr_t ecr; // external clock register reg_tim_tisel_t tisel; // TIx external clock source selection register uint32_t af1; // alternate function register 1 uint32_t af2; // alternate function register 2 uint32_t or1; // option register 1 uint32_t resv[220]; // reserved uint32_t dcr; // DMA control register uint32_t dmar; // DMA address for full transfer } reg_tim_t; #endif // REG_TIM_H