#include typedef struct { uint32_t syncin : 2; // 0 Synchronization inputs uint32_t reserve0 : 2; // 2 Reserve uint32_t syncout : 2; // 4 Synchronization outputs uint32_t reserve1 : 26; // 6 Reserve } reg_sai_gcr_t; typedef struct { uint32_t mode : 2; // 0 Audio block mode uint32_t prtcfg : 2; // 2 Protocol configuration uint32_t reserve0 : 1; // 4 Reserve uint32_t ds : 3; // 5 Data size uint32_t lsbfirst : 1; // 8 Least significant bit first uint32_t ckstr : 1; // 9 Clock strobing edge uint32_t syncen : 2; // 10 Synchronization enable uint32_t mono : 1; // 12 Mono mode uint32_t outdriv : 1; // 13 Output drive uint32_t reserve1 : 2; // 14 Reserve uint32_t saiaen : 1; // 16 Audio block A enable uint32_t dmaen : 1; // 17 DMA enable uint32_t reserve2 : 1; // 18 Reserve uint32_t nodiv : 1; // 19 No divider uint32_t mckdiv : 6; // 20 Master clock divider uint32_t osr : 1; // 26 OSR uint32_t mcken : 1; // 27 MCKEN uint32_t reserve3 : 4; // 28 Reserve } reg_sai_acr1_t; typedef struct { uint32_t mode : 2; // 0 Audio block mode uint32_t prtcfg : 2; // 2 Protocol configuration uint32_t reserve0 : 1; // 4 Reserve uint32_t ds : 3; // 5 Data size uint32_t lsbfirst : 1; // 8 Least significant bit first uint32_t ckstr : 1; // 9 Clock strobing edge uint32_t syncen : 2; // 10 Synchronization enable uint32_t mono : 1; // 12 Mono mode uint32_t outdriv : 1; // 13 Output drive uint32_t reserve1 : 2; // 14 Reserve uint32_t saiaen : 1; // 16 Audio block A enable uint32_t dmaen : 1; // 17 DMA enable uint32_t reserve2 : 1; // 18 Reserve uint32_t nodiv : 1; // 19 No divider uint32_t mckdiv : 6; // 20 Master clock divider uint32_t osr : 1; // 26 OSR uint32_t mcken : 1; // 27 MCKEN uint32_t reserve3 : 4; // 28 Reserve } reg_sai_bcr1_t; typedef struct { uint32_t fth : 3; // 0 FIFO threshold uint32_t fflush : 1; // 3 FIFO flush uint32_t tris : 1; // 4 Tristate management on data line uint32_t mute : 1; // 5 Mute uint32_t muteval : 1; // 6 Mute value uint32_t mutecn : 6; // 7 Mute counter uint32_t cpl : 1; // 13 Complement bit uint32_t comp : 2; // 14 Companding mode uint32_t reserve0 : 16; // 16 Reserve } reg_sai_acr2_t; typedef struct { uint32_t fth : 3; // 0 FIFO threshold uint32_t fflush : 1; // 3 FIFO flush uint32_t tris : 1; // 4 Tristate management on data line uint32_t mute : 1; // 5 Mute uint32_t muteval : 1; // 6 Mute value uint32_t mutecn : 6; // 7 Mute counter uint32_t cpl : 1; // 13 Complement bit uint32_t comp : 2; // 14 Companding mode uint32_t reserve0 : 16; // 16 Reserve } reg_sai_bcr2_t; typedef struct { uint32_t frl : 8; // 0 Frame length uint32_t fsall : 7; // 8 Frame synchronization active level length uint32_t reserve0 : 1; // 15 Reserve uint32_t fsdef : 1; // 16 Frame synchronization definition uint32_t fspol : 1; // 17 Frame synchronization polarity uint32_t fsoff : 1; // 18 Frame synchronization offset uint32_t reserve1 : 13; // 19 Reserve } reg_sai_afrcr_t; typedef struct { uint32_t frl : 8; // 0 Frame length uint32_t fsall : 7; // 8 Frame synchronization active level length uint32_t reserve0 : 1; // 15 Reserve uint32_t fsdef : 1; // 16 Frame synchronization definition uint32_t fspol : 1; // 17 Frame synchronization polarity uint32_t fsoff : 1; // 18 Frame synchronization offset uint32_t reserve1 : 13; // 19 Reserve } reg_sai_bfrcr_t; typedef struct { uint32_t fboff : 5; // 0 First bit offset uint32_t reserve0 : 1; // 5 Reserve uint32_t slotsz : 2; // 6 Slot size uint32_t nbslot : 4; // 8 Number of slots in an audio frame uint32_t reserve1 : 4; // 12 Reserve uint32_t sloten : 16; // 16 Slot enable } reg_sai_aslotr_t; typedef struct { uint32_t fboff : 5; // 0 First bit offset uint32_t reserve0 : 1; // 5 Reserve uint32_t slotsz : 2; // 6 Slot size uint32_t nbslot : 4; // 8 Number of slots in an audio frame uint32_t reserve1 : 4; // 12 Reserve uint32_t sloten : 16; // 16 Slot enable } reg_sai_bslotr_t; typedef struct { uint32_t ovrudrie : 1; // 0 Overrun/underrun interrupt enable uint32_t mutedetie : 1; // 1 Mute detection interrupt enable uint32_t wckcfgie : 1; // 2 Wrong clock configuration interrupt enable uint32_t freqie : 1; // 3 FIFO request interrupt enable uint32_t cnrdyie : 1; // 4 Codec not ready interrupt enable uint32_t afsdetie : 1; // 5 Anticipated frame synchronization detection interrupt enable uint32_t lfsdetie : 1; // 6 Late frame synchronization detection interrupt enable uint32_t reserve0 : 25; // 7 Reserve } reg_sai_aim_t; typedef struct { uint32_t ovrudrie : 1; // 0 Overrun/underrun interrupt enable uint32_t mutedetie : 1; // 1 Mute detection interrupt enable uint32_t wckcfgie : 1; // 2 Wrong clock configuration interrupt enable uint32_t freqie : 1; // 3 FIFO request interrupt enable uint32_t cnrdyie : 1; // 4 Codec not ready interrupt enable uint32_t afsdetie : 1; // 5 Anticipated frame synchronization detection interrupt enable uint32_t lfsdetie : 1; // 6 Late frame synchronization detection interrupt enable uint32_t reserve0 : 25; // 7 Reserve } reg_sai_bim_t; typedef struct { uint32_t ovrudr : 1; // 0 Overrun / underrun uint32_t mutedet : 1; // 1 Mute detection uint32_t wckcfg : 1; // 2 Wrong clock configuration flag. This bit is read only uint32_t freq : 1; // 3 FIFO request uint32_t cnrdy : 1; // 4 Codec not ready uint32_t afsdet : 1; // 5 Anticipated frame synchronization detection uint32_t lfsdet : 1; // 6 Late frame synchronization detection uint32_t reserve0 : 9; // 7 Reserve uint32_t flvl : 3; // 16 FIFO level threshold uint32_t reserve1 : 13; // 19 Reserve } reg_sai_asr_t; typedef struct { uint32_t ovrudr : 1; // 0 Overrun / underrun uint32_t mutedet : 1; // 1 Mute detection uint32_t wckcfg : 1; // 2 Wrong clock configuration flag uint32_t freq : 1; // 3 FIFO request uint32_t cnrdy : 1; // 4 Codec not ready uint32_t afsdet : 1; // 5 Anticipated frame synchronization detection uint32_t lfsdet : 1; // 6 Late frame synchronization detection uint32_t reserve0 : 9; // 7 Reserve uint32_t flvl : 3; // 16 FIFO level threshold uint32_t reserve1 : 13; // 19 Reserve } reg_sai_bsr_t; typedef struct { uint32_t covrudr : 1; // 0 Clear overrun / underrun uint32_t cmutedet : 1; // 1 Mute detection flag uint32_t cwckcfg : 1; // 2 Clear wrong clock configuration flag uint32_t reserve0 : 1; // 3 Reserve uint32_t ccnrdy : 1; // 4 Clear codec not ready flag uint32_t cafsdet : 1; // 5 Clear anticipated frame synchronization detection flag uint32_t clfsdet : 1; // 6 Clear late frame synchronization detection flag uint32_t reserve1 : 25; // 7 Reserve } reg_sai_aclrfr_t; typedef struct { uint32_t covrudr : 1; // 0 Clear overrun / underrun uint32_t cmutedet : 1; // 1 Mute detection flag uint32_t cwckcfg : 1; // 2 Clear wrong clock configuration flag uint32_t reserve0 : 1; // 3 Reserve uint32_t ccnrdy : 1; // 4 Clear codec not ready flag uint32_t cafsdet : 1; // 5 Clear anticipated frame synchronization detection flag uint32_t clfsdet : 1; // 6 Clear late frame synchronization detection flag uint32_t reserve1 : 25; // 7 Reserve } reg_sai_bclrfr_t; typedef struct { uint32_t data : 32; // 0 Data } reg_sai_adr_t; typedef struct { uint32_t data : 32; // 0 Data } reg_sai_bdr_t; typedef struct { uint32_t pdmen : 1; // 0 PDM enable uint32_t reserve0 : 3; // 1 Reserve uint32_t micnbr : 2; // 4 MICNBR uint32_t reserve1 : 2; // 6 Reserve uint32_t cken1 : 1; // 8 Clock enable of bitstream clock number 1 uint32_t cken2 : 1; // 9 CKEN2 uint32_t cken3 : 1; // 10 CKEN3 uint32_t cken4 : 1; // 11 CKEN4 uint32_t reserve2 : 20; // 12 Reserve } reg_sai_pdmcr_t; typedef struct { uint32_t dlym1l : 3; // 0 Delay line adjust for first microphone of pair 1 uint32_t reserve0 : 1; // 3 Reserve uint32_t dlym1r : 3; // 4 Delay line adjust for second microphone of pair 1 uint32_t reserve1 : 1; // 7 Reserve uint32_t dlym2l : 3; // 8 Delay line for first microphone of pair 2 uint32_t reserve2 : 1; // 11 Reserve uint32_t dlym2r : 3; // 12 Delay line for second microphone of pair 2 uint32_t reserve3 : 1; // 15 Reserve uint32_t dlym3l : 3; // 16 DLYM3L uint32_t reserve4 : 1; // 19 Reserve uint32_t dlym3r : 3; // 20 DLYM3R uint32_t reserve5 : 1; // 23 Reserve uint32_t dlym4l : 3; // 24 DLYM4L uint32_t reserve6 : 1; // 27 Reserve uint32_t dlym4r : 3; // 28 DLYM4R uint32_t reserve7 : 1; // 31 Reserve } reg_sai_pdmdly_t; typedef struct { volatile reg_sai_gcr_t gcr; volatile reg_sai_acr1_t acr1; volatile uint32_t reserve0[7]; volatile reg_sai_bcr1_t bcr1; volatile uint32_t reserve1[-8]; volatile reg_sai_acr2_t acr2; volatile uint32_t reserve2[7]; volatile reg_sai_bcr2_t bcr2; volatile uint32_t reserve3[-8]; volatile reg_sai_afrcr_t afrcr; volatile uint32_t reserve4[7]; volatile reg_sai_bfrcr_t bfrcr; volatile uint32_t reserve5[-8]; volatile reg_sai_aslotr_t aslotr; volatile uint32_t reserve6[7]; volatile reg_sai_bslotr_t bslotr; volatile uint32_t reserve7[-8]; volatile reg_sai_aim_t aim; volatile uint32_t reserve8[7]; volatile reg_sai_bim_t bim; volatile uint32_t reserve9[-8]; volatile reg_sai_asr_t asr; volatile uint32_t reserve10[7]; volatile reg_sai_bsr_t bsr; volatile uint32_t reserve11[-8]; volatile reg_sai_aclrfr_t aclrfr; volatile uint32_t reserve12[7]; volatile reg_sai_bclrfr_t bclrfr; volatile uint32_t reserve13[-8]; volatile reg_sai_adr_t adr; volatile uint32_t reserve14[7]; volatile reg_sai_bdr_t bdr; volatile reg_sai_pdmcr_t pdmcr; volatile reg_sai_pdmdly_t pdmdly; } reg_sai_t;